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-rw-r--r--A5.1/Verilog/Piotr/Documentation/a51.odgbin0 -> 14632 bytes
-rw-r--r--A5.1/Verilog/Piotr/Documentation/a51.pngbin0 -> 48694 bytes
-rw-r--r--A5.1/Verilog/Piotr/Documentation/steps.odgbin0 -> 16329 bytes
-rw-r--r--A5.1/Verilog/Piotr/Documentation/steps.pngbin0 -> 35539 bytes
-rw-r--r--A5.1/Verilog/Piotr/Makefile49
-rw-r--r--A5.1/Verilog/Piotr/a51.v327
-rw-r--r--A5.1/Verilog/Piotr/gen_a51.py17
-rw-r--r--A5.1/Verilog/Piotr/majority.v35
-rw-r--r--A5.1/Verilog/Piotr/majority_tb.sav11
-rw-r--r--A5.1/Verilog/Piotr/majority_tb.v67
-rw-r--r--A5.1/Verilog/Piotr/one_step.v86
-rw-r--r--A5.1/Verilog/Piotr/one_step_tb.sav32
-rw-r--r--A5.1/Verilog/Piotr/one_step_tb.v51
13 files changed, 675 insertions, 0 deletions
diff --git a/A5.1/Verilog/Piotr/Documentation/a51.odg b/A5.1/Verilog/Piotr/Documentation/a51.odg
new file mode 100644
index 0000000..816b897
--- /dev/null
+++ b/A5.1/Verilog/Piotr/Documentation/a51.odg
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diff --git a/A5.1/Verilog/Piotr/Documentation/a51.png b/A5.1/Verilog/Piotr/Documentation/a51.png
new file mode 100644
index 0000000..bc8bdc7
--- /dev/null
+++ b/A5.1/Verilog/Piotr/Documentation/a51.png
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diff --git a/A5.1/Verilog/Piotr/Documentation/steps.odg b/A5.1/Verilog/Piotr/Documentation/steps.odg
new file mode 100644
index 0000000..f581010
--- /dev/null
+++ b/A5.1/Verilog/Piotr/Documentation/steps.odg
Binary files differ
diff --git a/A5.1/Verilog/Piotr/Documentation/steps.png b/A5.1/Verilog/Piotr/Documentation/steps.png
new file mode 100644
index 0000000..7acd37f
--- /dev/null
+++ b/A5.1/Verilog/Piotr/Documentation/steps.png
Binary files differ
diff --git a/A5.1/Verilog/Piotr/Makefile b/A5.1/Verilog/Piotr/Makefile
new file mode 100644
index 0000000..7f074a7
--- /dev/null
+++ b/A5.1/Verilog/Piotr/Makefile
@@ -0,0 +1,49 @@
+T = one_step
+TGT = ${T}_tb
+
+LIB="./"
+
+INCLUDE_DIR=./
+
+VERILOG_SOURCES = ${TGT}.v \
+${T}.v
+
+SIMFILE = ${TGT}.vvp
+VCDFILE = ${TGT}.vcd
+
+WAVERC = gtkwaverc
+WAVECFG = ${TGT}.sav
+
+ICARUS = iverilog
+IFLAGS = -v
+
+VVP = vvp
+VFLAGS = -v
+VFLAGSEXTRA =
+
+GTKWAVE = gtkwave
+GFLAGS = --save=${WAVECFG} --rcfile=${WAVERC}
+
+all: compile simulate gtkwave
+
+${TGT}.vvp: ${VERILOG_SOURCES}
+ @ echo Compiling verilog files...
+ @ ${ICARUS} ${IFLAGS} -s ${TGT} -o ${SIMFILE} -y ${LIB} ${VERILOG_SOURCES} -I${INCLUDE_DIR}
+
+compile : ${TGT}.vvp
+
+${TGT}.vcd: compile
+ @ echo Simulating design...
+ @ ${VVP} ${VFLAGS} ${SIMFILE} ${VFLAGSEXTRA}
+
+simulate : ${TGT}.vcd
+
+gtkwave : compile simulate
+ @ echo Viewing waveforms in gtkwave...
+ @ ${GTKWAVE} ${GFLAGS} ${VCDFILE}
+
+clean:
+ @ echo Cleaning up...
+ @rm -f *.vvp *.vcd *~ *.log
+
+
diff --git a/A5.1/Verilog/Piotr/a51.v b/A5.1/Verilog/Piotr/a51.v
new file mode 100644
index 0000000..e6b23f0
--- /dev/null
+++ b/A5.1/Verilog/Piotr/a51.v
@@ -0,0 +1,327 @@
+// -*- Mode: Verilog -*-
+// Filename : a51.v
+// Description : A5/1 algorithm (without mixing of the Kc and Fn)
+// Author : piotr
+// Created On : Mon Jan 19 20:55:38 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count : 0
+// Status : Unknown, Use with caution!
+
+
+module a51(
+ clk,
+ enable,
+ in_state,
+ keystream
+ );
+
+ parameter StateWidth = 64;
+
+ input clk, enable;
+ input [StateWidth:1] in_state;
+ output [StateWidth:1] keystream;
+
+
+ wire [StateWidth:1] step1_out;
+ one_step step1(.clk(clk), .enable(enable), .in_state(in_state), .out_state(step1_out));
+
+ wire [StateWidth:1] step2_out;
+ one_step step2(.clk(clk), .enable(enable), .in_state(step1_out), .out_state(step2_out));
+
+ wire [StateWidth:1] step3_out;
+ one_step step3(.clk(clk), .enable(enable), .in_state(step2_out), .out_state(step3_out));
+
+ wire [StateWidth:1] step4_out;
+ one_step step4(.clk(clk), .enable(enable), .in_state(step3_out), .out_state(step4_out));
+
+ wire [StateWidth:1] step5_out;
+ one_step step5(.clk(clk), .enable(enable), .in_state(step4_out), .out_state(step5_out));
+
+ wire [StateWidth:1] step6_out;
+ one_step step6(.clk(clk), .enable(enable), .in_state(step5_out), .out_state(step6_out));
+
+ wire [StateWidth:1] step7_out;
+ one_step step7(.clk(clk), .enable(enable), .in_state(step6_out), .out_state(step7_out));
+
+ wire [StateWidth:1] step8_out;
+ one_step step8(.clk(clk), .enable(enable), .in_state(step7_out), .out_state(step8_out));
+
+ wire [StateWidth:1] step9_out;
+ one_step step9(.clk(clk), .enable(enable), .in_state(step8_out), .out_state(step9_out));
+
+ wire [StateWidth:1] step10_out;
+ one_step step10(.clk(clk), .enable(enable), .in_state(step9_out), .out_state(step10_out));
+
+ wire [StateWidth:1] step11_out;
+ one_step step11(.clk(clk), .enable(enable), .in_state(step10_out), .out_state(step11_out));
+
+ wire [StateWidth:1] step12_out;
+ one_step step12(.clk(clk), .enable(enable), .in_state(step11_out), .out_state(step12_out));
+
+ wire [StateWidth:1] step13_out;
+ one_step step13(.clk(clk), .enable(enable), .in_state(step12_out), .out_state(step13_out));
+
+ wire [StateWidth:1] step14_out;
+ one_step step14(.clk(clk), .enable(enable), .in_state(step13_out), .out_state(step14_out));
+
+ wire [StateWidth:1] step15_out;
+ one_step step15(.clk(clk), .enable(enable), .in_state(step14_out), .out_state(step15_out));
+
+ wire [StateWidth:1] step16_out;
+ one_step step16(.clk(clk), .enable(enable), .in_state(step15_out), .out_state(step16_out));
+
+ wire [StateWidth:1] step17_out;
+ one_step step17(.clk(clk), .enable(enable), .in_state(step16_out), .out_state(step17_out));
+
+ wire [StateWidth:1] step18_out;
+ one_step step18(.clk(clk), .enable(enable), .in_state(step17_out), .out_state(step18_out));
+
+ wire [StateWidth:1] step19_out;
+ one_step step19(.clk(clk), .enable(enable), .in_state(step18_out), .out_state(step19_out));
+
+ wire [StateWidth:1] step20_out;
+ one_step step20(.clk(clk), .enable(enable), .in_state(step19_out), .out_state(step20_out));
+
+ wire [StateWidth:1] step21_out;
+ one_step step21(.clk(clk), .enable(enable), .in_state(step20_out), .out_state(step21_out));
+
+ wire [StateWidth:1] step22_out;
+ one_step step22(.clk(clk), .enable(enable), .in_state(step21_out), .out_state(step22_out));
+
+ wire [StateWidth:1] step23_out;
+ one_step step23(.clk(clk), .enable(enable), .in_state(step22_out), .out_state(step23_out));
+
+ wire [StateWidth:1] step24_out;
+ one_step step24(.clk(clk), .enable(enable), .in_state(step23_out), .out_state(step24_out));
+
+ wire [StateWidth:1] step25_out;
+ one_step step25(.clk(clk), .enable(enable), .in_state(step24_out), .out_state(step25_out));
+
+ wire [StateWidth:1] step26_out;
+ one_step step26(.clk(clk), .enable(enable), .in_state(step25_out), .out_state(step26_out));
+
+ wire [StateWidth:1] step27_out;
+ one_step step27(.clk(clk), .enable(enable), .in_state(step26_out), .out_state(step27_out));
+
+ wire [StateWidth:1] step28_out;
+ one_step step28(.clk(clk), .enable(enable), .in_state(step27_out), .out_state(step28_out));
+
+ wire [StateWidth:1] step29_out;
+ one_step step29(.clk(clk), .enable(enable), .in_state(step28_out), .out_state(step29_out));
+
+ wire [StateWidth:1] step30_out;
+ one_step step30(.clk(clk), .enable(enable), .in_state(step29_out), .out_state(step30_out));
+
+ wire [StateWidth:1] step31_out;
+ one_step step31(.clk(clk), .enable(enable), .in_state(step30_out), .out_state(step31_out));
+
+ wire [StateWidth:1] step32_out;
+ one_step step32(.clk(clk), .enable(enable), .in_state(step31_out), .out_state(step32_out));
+
+ wire [StateWidth:1] step33_out;
+ one_step step33(.clk(clk), .enable(enable), .in_state(step32_out), .out_state(step33_out));
+
+ wire [StateWidth:1] step34_out;
+ one_step step34(.clk(clk), .enable(enable), .in_state(step33_out), .out_state(step34_out));
+
+ wire [StateWidth:1] step35_out;
+ one_step step35(.clk(clk), .enable(enable), .in_state(step34_out), .out_state(step35_out));
+
+ wire [StateWidth:1] step36_out;
+ one_step step36(.clk(clk), .enable(enable), .in_state(step35_out), .out_state(step36_out));
+
+ wire [StateWidth:1] step37_out;
+ one_step step37(.clk(clk), .enable(enable), .in_state(step36_out), .out_state(step37_out));
+
+ wire [StateWidth:1] step38_out;
+ one_step step38(.clk(clk), .enable(enable), .in_state(step37_out), .out_state(step38_out));
+
+ wire [StateWidth:1] step39_out;
+ one_step step39(.clk(clk), .enable(enable), .in_state(step38_out), .out_state(step39_out));
+
+ wire [StateWidth:1] step40_out;
+ one_step step40(.clk(clk), .enable(enable), .in_state(step39_out), .out_state(step40_out));
+
+ wire [StateWidth:1] step41_out;
+ one_step step41(.clk(clk), .enable(enable), .in_state(step40_out), .out_state(step41_out));
+
+ wire [StateWidth:1] step42_out;
+ one_step step42(.clk(clk), .enable(enable), .in_state(step41_out), .out_state(step42_out));
+
+ wire [StateWidth:1] step43_out;
+ one_step step43(.clk(clk), .enable(enable), .in_state(step42_out), .out_state(step43_out));
+
+ wire [StateWidth:1] step44_out;
+ one_step step44(.clk(clk), .enable(enable), .in_state(step43_out), .out_state(step44_out));
+
+ wire [StateWidth:1] step45_out;
+ one_step step45(.clk(clk), .enable(enable), .in_state(step44_out), .out_state(step45_out));
+
+ wire [StateWidth:1] step46_out;
+ one_step step46(.clk(clk), .enable(enable), .in_state(step45_out), .out_state(step46_out));
+
+ wire [StateWidth:1] step47_out;
+ one_step step47(.clk(clk), .enable(enable), .in_state(step46_out), .out_state(step47_out));
+
+ wire [StateWidth:1] step48_out;
+ one_step step48(.clk(clk), .enable(enable), .in_state(step47_out), .out_state(step48_out));
+
+ wire [StateWidth:1] step49_out;
+ one_step step49(.clk(clk), .enable(enable), .in_state(step48_out), .out_state(step49_out));
+
+ wire [StateWidth:1] step50_out;
+ one_step step50(.clk(clk), .enable(enable), .in_state(step49_out), .out_state(step50_out));
+
+ wire [StateWidth:1] step51_out;
+ one_step step51(.clk(clk), .enable(enable), .in_state(step50_out), .out_state(step51_out));
+
+ wire [StateWidth:1] step52_out;
+ one_step step52(.clk(clk), .enable(enable), .in_state(step51_out), .out_state(step52_out));
+
+ wire [StateWidth:1] step53_out;
+ one_step step53(.clk(clk), .enable(enable), .in_state(step52_out), .out_state(step53_out));
+
+ wire [StateWidth:1] step54_out;
+ one_step step54(.clk(clk), .enable(enable), .in_state(step53_out), .out_state(step54_out));
+
+ wire [StateWidth:1] step55_out;
+ one_step step55(.clk(clk), .enable(enable), .in_state(step54_out), .out_state(step55_out));
+
+ wire [StateWidth:1] step56_out;
+ one_step step56(.clk(clk), .enable(enable), .in_state(step55_out), .out_state(step56_out));
+
+ wire [StateWidth:1] step57_out;
+ one_step step57(.clk(clk), .enable(enable), .in_state(step56_out), .out_state(step57_out));
+
+ wire [StateWidth:1] step58_out;
+ one_step step58(.clk(clk), .enable(enable), .in_state(step57_out), .out_state(step58_out));
+
+ wire [StateWidth:1] step59_out;
+ one_step step59(.clk(clk), .enable(enable), .in_state(step58_out), .out_state(step59_out));
+
+ wire [StateWidth:1] step60_out;
+ one_step step60(.clk(clk), .enable(enable), .in_state(step59_out), .out_state(step60_out));
+
+ wire [StateWidth:1] step61_out;
+ one_step step61(.clk(clk), .enable(enable), .in_state(step60_out), .out_state(step61_out));
+
+ wire [StateWidth:1] step62_out;
+ one_step step62(.clk(clk), .enable(enable), .in_state(step61_out), .out_state(step62_out));
+
+ wire [StateWidth:1] step63_out;
+ one_step step63(.clk(clk), .enable(enable), .in_state(step62_out), .out_state(step63_out));
+
+ wire [StateWidth:1] step64_out;
+ one_step step64(.clk(clk), .enable(enable), .in_state(step63_out), .out_state(step64_out));
+
+ wire [StateWidth:1] step65_out;
+ one_step step65(.clk(clk), .enable(enable), .in_state(step64_out), .out_state(step65_out));
+
+ wire [StateWidth:1] step66_out;
+ one_step step66(.clk(clk), .enable(enable), .in_state(step65_out), .out_state(step66_out));
+
+ wire [StateWidth:1] step67_out;
+ one_step step67(.clk(clk), .enable(enable), .in_state(step66_out), .out_state(step67_out));
+
+ wire [StateWidth:1] step68_out;
+ one_step step68(.clk(clk), .enable(enable), .in_state(step67_out), .out_state(step68_out));
+
+ wire [StateWidth:1] step69_out;
+ one_step step69(.clk(clk), .enable(enable), .in_state(step68_out), .out_state(step69_out));
+
+ wire [StateWidth:1] step70_out;
+ one_step step70(.clk(clk), .enable(enable), .in_state(step69_out), .out_state(step70_out));
+
+ wire [StateWidth:1] step71_out;
+ one_step step71(.clk(clk), .enable(enable), .in_state(step70_out), .out_state(step71_out));
+
+ wire [StateWidth:1] step72_out;
+ one_step step72(.clk(clk), .enable(enable), .in_state(step71_out), .out_state(step72_out));
+
+ wire [StateWidth:1] step73_out;
+ one_step step73(.clk(clk), .enable(enable), .in_state(step72_out), .out_state(step73_out));
+
+ wire [StateWidth:1] step74_out;
+ one_step step74(.clk(clk), .enable(enable), .in_state(step73_out), .out_state(step74_out));
+
+ wire [StateWidth:1] step75_out;
+ one_step step75(.clk(clk), .enable(enable), .in_state(step74_out), .out_state(step75_out));
+
+ wire [StateWidth:1] step76_out;
+ one_step step76(.clk(clk), .enable(enable), .in_state(step75_out), .out_state(step76_out));
+
+ wire [StateWidth:1] step77_out;
+ one_step step77(.clk(clk), .enable(enable), .in_state(step76_out), .out_state(step77_out));
+
+ wire [StateWidth:1] step78_out;
+ one_step step78(.clk(clk), .enable(enable), .in_state(step77_out), .out_state(step78_out));
+
+ wire [StateWidth:1] step79_out;
+ one_step step79(.clk(clk), .enable(enable), .in_state(step78_out), .out_state(step79_out));
+
+ wire [StateWidth:1] step80_out;
+ one_step step80(.clk(clk), .enable(enable), .in_state(step79_out), .out_state(step80_out));
+
+ wire [StateWidth:1] step81_out;
+ one_step step81(.clk(clk), .enable(enable), .in_state(step80_out), .out_state(step81_out));
+
+ wire [StateWidth:1] step82_out;
+ one_step step82(.clk(clk), .enable(enable), .in_state(step81_out), .out_state(step82_out));
+
+ wire [StateWidth:1] step83_out;
+ one_step step83(.clk(clk), .enable(enable), .in_state(step82_out), .out_state(step83_out));
+
+ wire [StateWidth:1] step84_out;
+ one_step step84(.clk(clk), .enable(enable), .in_state(step83_out), .out_state(step84_out));
+
+ wire [StateWidth:1] step85_out;
+ one_step step85(.clk(clk), .enable(enable), .in_state(step84_out), .out_state(step85_out));
+
+ wire [StateWidth:1] step86_out;
+ one_step step86(.clk(clk), .enable(enable), .in_state(step85_out), .out_state(step86_out));
+
+ wire [StateWidth:1] step87_out;
+ one_step step87(.clk(clk), .enable(enable), .in_state(step86_out), .out_state(step87_out));
+
+ wire [StateWidth:1] step88_out;
+ one_step step88(.clk(clk), .enable(enable), .in_state(step87_out), .out_state(step88_out));
+
+ wire [StateWidth:1] step89_out;
+ one_step step89(.clk(clk), .enable(enable), .in_state(step88_out), .out_state(step89_out));
+
+ wire [StateWidth:1] step90_out;
+ one_step step90(.clk(clk), .enable(enable), .in_state(step89_out), .out_state(step90_out));
+
+ wire [StateWidth:1] step91_out;
+ one_step step91(.clk(clk), .enable(enable), .in_state(step90_out), .out_state(step91_out));
+
+ wire [StateWidth:1] step92_out;
+ one_step step92(.clk(clk), .enable(enable), .in_state(step91_out), .out_state(step92_out));
+
+ wire [StateWidth:1] step93_out;
+ one_step step93(.clk(clk), .enable(enable), .in_state(step92_out), .out_state(step93_out));
+
+ wire [StateWidth:1] step94_out;
+ one_step step94(.clk(clk), .enable(enable), .in_state(step93_out), .out_state(step94_out));
+
+ wire [StateWidth:1] step95_out;
+ one_step step95(.clk(clk), .enable(enable), .in_state(step94_out), .out_state(step95_out));
+
+ wire [StateWidth:1] step96_out;
+ one_step step96(.clk(clk), .enable(enable), .in_state(step95_out), .out_state(step96_out));
+
+ wire [StateWidth:1] step97_out;
+ one_step step97(.clk(clk), .enable(enable), .in_state(step96_out), .out_state(step97_out));
+
+ wire [StateWidth:1] step98_out;
+ one_step step98(.clk(clk), .enable(enable), .in_state(step97_out), .out_state(step98_out));
+
+ wire [StateWidth:1] step99_out;
+ one_step step99(.clk(clk), .enable(enable), .in_state(step98_out), .out_state(step99_out));
+
+ wire [StateWidth:1] step100_out;
+ one_step step100(.clk(clk), .enable(enable), .in_state(step99_out), .out_state(step100_out));
+
+
+endmodule \ No newline at end of file
diff --git a/A5.1/Verilog/Piotr/gen_a51.py b/A5.1/Verilog/Piotr/gen_a51.py
new file mode 100644
index 0000000..77c54da
--- /dev/null
+++ b/A5.1/Verilog/Piotr/gen_a51.py
@@ -0,0 +1,17 @@
+def gen_a51():
+ first_100_steps= []
+ first_100_steps.append(" wire [StateWidth:1] step1_out;")
+ first_100_steps.append(" one_step step1(.clk(clk), .enable(enable), .in_state(in_state), .out_state(step1_out));\n")
+
+ for i in xrange(2,101):
+ first_100_steps.append(" wire [StateWidth:1] step%d_out;"%(i))
+ first_100_steps.append(" one_step step%d(.clk(clk), .enable(enable), .in_state(step%d_out), .out_state(step%d_out));\n"%(i,(i-1),i))
+
+
+ for line in first_100_steps:
+ print line
+
+
+gen_a51()
+
+
diff --git a/A5.1/Verilog/Piotr/majority.v b/A5.1/Verilog/Piotr/majority.v
new file mode 100644
index 0000000..c957d93
--- /dev/null
+++ b/A5.1/Verilog/Piotr/majority.v
@@ -0,0 +1,35 @@
+// -*- Mode: Verilog -*-
+// Filename : majority.v
+// Description : Majority function
+// Author : piotr
+// Created On : Sun Jan 18 23:16:04 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count : 0
+// Status : Unknown, Use with caution!
+
+module majority(
+ R1_clk_bit,
+ R2_clk_bit,
+ R3_clk_bit,
+ R1_clk_out,
+ R2_clk_out,
+ R3_clk_out,
+ );
+
+ input R1_clk_bit;
+ input R2_clk_bit;
+ input R3_clk_bit;
+ output R1_clk_out;
+ output R2_clk_out;
+ output R3_clk_out;
+
+ wire majority_bit;
+
+ assign majority_bit = ( R1_clk_bit & R2_clk_bit ) ^ ( R2_clk_bit & R3_clk_bit ) ^ ( R1_clk_bit & R3_clk_bit );
+
+ assign R1_clk_out = ! majority_bit ^ R1_clk_bit;
+ assign R2_clk_out = ! majority_bit ^ R2_clk_bit;
+ assign R3_clk_out = ! majority_bit ^ R3_clk_bit;
+
+endmodule \ No newline at end of file
diff --git a/A5.1/Verilog/Piotr/majority_tb.sav b/A5.1/Verilog/Piotr/majority_tb.sav
new file mode 100644
index 0000000..7af49a8
--- /dev/null
+++ b/A5.1/Verilog/Piotr/majority_tb.sav
@@ -0,0 +1,11 @@
+[size] 1279 725
+[pos] -1 -1
+*-4.381813 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@29
+majority_tb.majority_inst.R1_clk_bit
+majority_tb.majority_inst.R2_clk_bit
+majority_tb.majority_inst.R3_clk_bit
+majority_tb.majority_inst.majority_bit
+majority_tb.majority_inst.R1_clk_out
+majority_tb.majority_inst.R2_clk_out
+majority_tb.majority_inst.R3_clk_out
diff --git a/A5.1/Verilog/Piotr/majority_tb.v b/A5.1/Verilog/Piotr/majority_tb.v
new file mode 100644
index 0000000..3d19a06
--- /dev/null
+++ b/A5.1/Verilog/Piotr/majority_tb.v
@@ -0,0 +1,67 @@
+// -*- Mode: Verilog -*-
+// Filename : majority_tb.v
+// Description :
+// Author : piotr
+// Created On : Mon Jan 19 16:41:43 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count : 0
+// Status : Unknown, Use with caution!
+
+module majority_tb();
+ reg R1_clk_bit, R2_clk_bit, R3_clk_bit;
+ wire R1_clk_out, R2_clk_out, R3_clk_out;
+
+ majority majority_inst(
+ .R1_clk_bit(R1_clk_bit),
+ .R2_clk_bit(R2_clk_bit),
+ .R3_clk_bit(R3_clk_bit),
+ .R1_clk_out(R1_clk_out),
+ .R2_clk_out(R2_clk_out),
+ .R3_clk_out(R3_clk_out)
+ );
+
+ initial
+ begin
+ R1_clk_bit = 0;
+ R2_clk_bit = 0;
+ R3_clk_bit = 0;
+
+ #10 R1_clk_bit = 1;
+ R2_clk_bit = 0;
+ R3_clk_bit = 0;
+
+ #10 R1_clk_bit = 0;
+ R2_clk_bit = 1;
+ R3_clk_bit = 0;
+
+ #10 R1_clk_bit = 1;
+ R2_clk_bit = 1;
+ R3_clk_bit = 0;
+
+ #10 R1_clk_bit = 0;
+ R2_clk_bit = 0;
+ R3_clk_bit = 1;
+
+ #10 R1_clk_bit = 1;
+ R2_clk_bit = 0;
+ R3_clk_bit = 1;
+
+ #10 R1_clk_bit = 0;
+ R2_clk_bit = 1;
+ R3_clk_bit = 1;
+
+ #10 R1_clk_bit = 1;
+ R2_clk_bit = 1;
+ R3_clk_bit = 1;
+ end
+
+ initial
+ begin
+ $dumpvars;
+ $dumpfile("majority_tb.vcd");
+ $dumpon;
+ #90 $dumpoff;
+ end
+
+endmodule \ No newline at end of file
diff --git a/A5.1/Verilog/Piotr/one_step.v b/A5.1/Verilog/Piotr/one_step.v
new file mode 100644
index 0000000..df0605e
--- /dev/null
+++ b/A5.1/Verilog/Piotr/one_step.v
@@ -0,0 +1,86 @@
+// -*- Mode: Verilog -*-
+// Filename : one_step.v
+// Description : One step of the pipelined A5/1 algorithm
+// Author : piotr
+// Created On : Fri Jan 16 19:21:34 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count : 0
+// Status : Work in progress
+
+module one_step(
+ clk,
+ enable,
+ in_state,
+ out_state,
+ keystream_bit
+ );
+
+ parameter StateWidth = 64;
+ parameter R1Width = 19;
+ parameter R2Width = 22;
+ parameter R3Width = 23;
+
+ input clk, enable;
+ input [StateWidth:1] in_state;
+ output keystream_bit;
+ output [StateWidth:1] out_state;
+
+ wire [R1Width:1] R1in;
+ wire [R2Width:1] R2in;
+ wire [R3Width:1] R3in;
+
+ wire R1_feedback;
+ wire R2_feedback;
+ wire R3_feedback;
+
+ wire R1_clk_out;
+ wire R2_clk_out;
+ wire R3_clk_out;
+
+ reg [R1Width:1] R1;
+ reg [R2Width:1] R2;
+ reg [R3Width:1] R3;
+
+ assign R1in = in_state[R1Width:1];
+ assign R2in = in_state[R2Width+R1Width:R1Width+1];
+ assign R3in = in_state[StateWidth:R1Width+R2Width+1];
+
+ assign R1_feedback = R1in[19] ^ R1in[18] ^ R1in[17] ^ R1in[14];
+ assign R2_feedback = R2in[22] ^ R2in[21];
+ assign R3_feedback = R3in[23] ^ R3in[22] ^ R3in[21] ^ R3in[7];
+
+ assign out_state = {R3,R2,R1};
+
+ assign keystream_bit = R1[R1Width] ^ R2[R2Width] ^ R3[R3Width];
+
+ majority majority_instance(
+ .R1_clk_bit(R1in[9]),
+ .R2_clk_bit(R2in[11]),
+ .R3_clk_bit(R3in[11]),
+ .R1_clk_out(R1_clk_out),
+ .R2_clk_out(R2_clk_out),
+ .R3_clk_out(R3_clk_out)
+ );
+
+ always @(posedge clk)
+ begin
+ if(enable == 1'b1)
+ begin
+ if(R1_clk_out == 1'b1)
+ R1 <= {R1in[R1Width-1:1], R1_feedback};
+ else
+ R1 <= R1in;
+
+ if(R2_clk_out == 1'b1)
+ R2 <= {R2in[R2Width-1:1], R2_feedback};
+ else
+ R2 <= R2in;
+
+ if(R3_clk_out == 1'b1)
+ R3 <= {R3in[R3Width-1:1], R3_feedback};
+ else
+ R3 <= R3in;
+ end
+ end
+endmodule
diff --git a/A5.1/Verilog/Piotr/one_step_tb.sav b/A5.1/Verilog/Piotr/one_step_tb.sav
new file mode 100644
index 0000000..947a334
--- /dev/null
+++ b/A5.1/Verilog/Piotr/one_step_tb.sav
@@ -0,0 +1,32 @@
+[size] 1270 532
+[pos] 0 188
+*-2.928085 21 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+@28
+one_step_tb.one_step_inst.R1_feedback
+one_step_tb.one_step_inst.R2_feedback
+one_step_tb.one_step_inst.R3_feedback
+one_step_tb.one_step_inst.clk
+@22
+one_step_tb.one_step_inst.in_state[64:1]
+one_step_tb.one_step_inst.out_state[64:1]
+@28
+one_step_tb.one_step_inst.R1_clk_out
+one_step_tb.one_step_inst.R2_clk_out
+one_step_tb.one_step_inst.R3_clk_out
+@22
+one_step_tb.one_step_inst.R1in[19:1]
+one_step_tb.one_step_inst.R1[19:1]
+one_step_tb.one_step_inst.R2in[22:1]
+one_step_tb.one_step_inst.R2[22:1]
+one_step_tb.one_step_inst.R3in[23:1]
+one_step_tb.one_step_inst.R3[23:1]
+@28
+one_step_tb.one_step_inst.majority_instance.R1_clk_bit
+one_step_tb.one_step_inst.majority_instance.R2_clk_bit
+one_step_tb.one_step_inst.majority_instance.R3_clk_bit
+@29
+one_step_tb.one_step_inst.majority_instance.majority_bit
+@28
+one_step_tb.one_step_inst.majority_instance.R1_clk_out
+one_step_tb.one_step_inst.majority_instance.R2_clk_out
+one_step_tb.one_step_inst.majority_instance.R3_clk_out
diff --git a/A5.1/Verilog/Piotr/one_step_tb.v b/A5.1/Verilog/Piotr/one_step_tb.v
new file mode 100644
index 0000000..7ca6e86
--- /dev/null
+++ b/A5.1/Verilog/Piotr/one_step_tb.v
@@ -0,0 +1,51 @@
+// -*- Mode: Verilog -*-
+// Filename : one_step_tb.v
+// Description : Testbench for one step of A5/1 module
+// Author : piotr
+// Created On : Mon Jan 19 15:16:40 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count : 0
+// Status : Unknown, Use with caution!
+`define InternalStateWidth 64
+
+module one_step_tb();
+ reg clk, enable;
+ reg [`InternalStateWidth:1] in_state;
+ wire[`InternalStateWidth:1] out_state;
+
+ one_step one_step_inst(
+ .clk(clk),
+ .enable(enable),
+ .in_state(in_state),
+ .out_state(out_state)
+ );
+ always
+ begin
+ #5 clk = !clk;
+ end
+
+ initial
+ begin
+ clk = 1'b1;
+ enable = 1'b1;
+ in_state = `InternalStateWidth'd1;
+ #5 in_state = `InternalStateWidth'b1110010110111111000110110101111000000111001010000110010010100010;
+ #10 in_state = `InternalStateWidth'b1110010110111111000110101011110000001110010110001100100101000101;
+ #10 in_state = `InternalStateWidth'b1100101101111110001101001011110000001110010110011001001010001010;
+ #10 in_state = `InternalStateWidth'b1100101101111110001101010111100000011100101110110010010100010101;
+ #10 in_state = `InternalStateWidth'b1001011011111100011010010111100000011100101111100100101000101011;
+ #10 in_state = `InternalStateWidth'b1001011011111100011010001111000000111001011111001001010001010110;
+ #10 in_state = `InternalStateWidth'b0010110111111000110100111110000001110010111111001001010001010110;
+
+ #20 $finish;
+ end
+
+ initial
+ begin
+ $dumpvars;
+ $dumpfile("one_step_tb.vcd");
+ $dumpon;
+ #90 $dumpoff;
+ end
+endmodule \ No newline at end of file
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