diff options
Diffstat (limited to 'A5.1/Verilog/Piotr/majority_tb.v')
| -rw-r--r-- | A5.1/Verilog/Piotr/majority_tb.v | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/A5.1/Verilog/Piotr/majority_tb.v b/A5.1/Verilog/Piotr/majority_tb.v new file mode 100644 index 0000000..3d19a06 --- /dev/null +++ b/A5.1/Verilog/Piotr/majority_tb.v @@ -0,0 +1,67 @@ +// -*- Mode: Verilog -*- +// Filename : majority_tb.v +// Description : +// Author : piotr +// Created On : Mon Jan 19 16:41:43 2009 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +module majority_tb(); + reg R1_clk_bit, R2_clk_bit, R3_clk_bit; + wire R1_clk_out, R2_clk_out, R3_clk_out; + + majority majority_inst( + .R1_clk_bit(R1_clk_bit), + .R2_clk_bit(R2_clk_bit), + .R3_clk_bit(R3_clk_bit), + .R1_clk_out(R1_clk_out), + .R2_clk_out(R2_clk_out), + .R3_clk_out(R3_clk_out) + ); + + initial + begin + R1_clk_bit = 0; + R2_clk_bit = 0; + R3_clk_bit = 0; + + #10 R1_clk_bit = 1; + R2_clk_bit = 0; + R3_clk_bit = 0; + + #10 R1_clk_bit = 0; + R2_clk_bit = 1; + R3_clk_bit = 0; + + #10 R1_clk_bit = 1; + R2_clk_bit = 1; + R3_clk_bit = 0; + + #10 R1_clk_bit = 0; + R2_clk_bit = 0; + R3_clk_bit = 1; + + #10 R1_clk_bit = 1; + R2_clk_bit = 0; + R3_clk_bit = 1; + + #10 R1_clk_bit = 0; + R2_clk_bit = 1; + R3_clk_bit = 1; + + #10 R1_clk_bit = 1; + R2_clk_bit = 1; + R3_clk_bit = 1; + end + + initial + begin + $dumpvars; + $dumpfile("majority_tb.vcd"); + $dumpon; + #90 $dumpoff; + end + +endmodule
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