From c8747f28d85fcc6c9f431fb2afc9627c4356826d Mon Sep 17 00:00:00 2001 From: Andreas Bogk Date: Sat, 24 Jan 2009 17:06:16 +0100 Subject: Piotr's pipelined implementation. --- A5.1/Verilog/Piotr/majority.v | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 A5.1/Verilog/Piotr/majority.v (limited to 'A5.1/Verilog/Piotr/majority.v') diff --git a/A5.1/Verilog/Piotr/majority.v b/A5.1/Verilog/Piotr/majority.v new file mode 100644 index 0000000..c957d93 --- /dev/null +++ b/A5.1/Verilog/Piotr/majority.v @@ -0,0 +1,35 @@ +// -*- Mode: Verilog -*- +// Filename : majority.v +// Description : Majority function +// Author : piotr +// Created On : Sun Jan 18 23:16:04 2009 +// Last Modified By: . +// Last Modified On: . +// Update Count : 0 +// Status : Unknown, Use with caution! + +module majority( + R1_clk_bit, + R2_clk_bit, + R3_clk_bit, + R1_clk_out, + R2_clk_out, + R3_clk_out, + ); + + input R1_clk_bit; + input R2_clk_bit; + input R3_clk_bit; + output R1_clk_out; + output R2_clk_out; + output R3_clk_out; + + wire majority_bit; + + assign majority_bit = ( R1_clk_bit & R2_clk_bit ) ^ ( R2_clk_bit & R3_clk_bit ) ^ ( R1_clk_bit & R3_clk_bit ); + + assign R1_clk_out = ! majority_bit ^ R1_clk_bit; + assign R2_clk_out = ! majority_bit ^ R2_clk_bit; + assign R3_clk_out = ! majority_bit ^ R3_clk_bit; + +endmodule \ No newline at end of file -- cgit v1.2.3