From c8747f28d85fcc6c9f431fb2afc9627c4356826d Mon Sep 17 00:00:00 2001 From: Andreas Bogk Date: Sat, 24 Jan 2009 17:06:16 +0100 Subject: Piotr's pipelined implementation. --- A5.1/Verilog/Piotr/one_step_tb.sav | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 A5.1/Verilog/Piotr/one_step_tb.sav (limited to 'A5.1/Verilog/Piotr/one_step_tb.sav') diff --git a/A5.1/Verilog/Piotr/one_step_tb.sav b/A5.1/Verilog/Piotr/one_step_tb.sav new file mode 100644 index 0000000..947a334 --- /dev/null +++ b/A5.1/Verilog/Piotr/one_step_tb.sav @@ -0,0 +1,32 @@ +[size] 1270 532 +[pos] 0 188 +*-2.928085 21 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +@28 +one_step_tb.one_step_inst.R1_feedback +one_step_tb.one_step_inst.R2_feedback +one_step_tb.one_step_inst.R3_feedback +one_step_tb.one_step_inst.clk +@22 +one_step_tb.one_step_inst.in_state[64:1] +one_step_tb.one_step_inst.out_state[64:1] +@28 +one_step_tb.one_step_inst.R1_clk_out +one_step_tb.one_step_inst.R2_clk_out +one_step_tb.one_step_inst.R3_clk_out +@22 +one_step_tb.one_step_inst.R1in[19:1] +one_step_tb.one_step_inst.R1[19:1] +one_step_tb.one_step_inst.R2in[22:1] +one_step_tb.one_step_inst.R2[22:1] +one_step_tb.one_step_inst.R3in[23:1] +one_step_tb.one_step_inst.R3[23:1] +@28 +one_step_tb.one_step_inst.majority_instance.R1_clk_bit +one_step_tb.one_step_inst.majority_instance.R2_clk_bit +one_step_tb.one_step_inst.majority_instance.R3_clk_bit +@29 +one_step_tb.one_step_inst.majority_instance.majority_bit +@28 +one_step_tb.one_step_inst.majority_instance.R1_clk_out +one_step_tb.one_step_inst.majority_instance.R2_clk_out +one_step_tb.one_step_inst.majority_instance.R3_clk_out -- cgit v1.2.3