From c8747f28d85fcc6c9f431fb2afc9627c4356826d Mon Sep 17 00:00:00 2001
From: Andreas Bogk <andreas@pt141.(none)>
Date: Sat, 24 Jan 2009 17:06:16 +0100
Subject: Piotr's pipelined implementation.

---
 A5.1/Verilog/Piotr/one_step_tb.v | 51 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)
 create mode 100644 A5.1/Verilog/Piotr/one_step_tb.v

(limited to 'A5.1/Verilog/Piotr/one_step_tb.v')

diff --git a/A5.1/Verilog/Piotr/one_step_tb.v b/A5.1/Verilog/Piotr/one_step_tb.v
new file mode 100644
index 0000000..7ca6e86
--- /dev/null
+++ b/A5.1/Verilog/Piotr/one_step_tb.v
@@ -0,0 +1,51 @@
+//                              -*- Mode: Verilog -*-
+// Filename        : one_step_tb.v
+// Description     : Testbench for one step of A5/1 module
+// Author          : piotr
+// Created On      : Mon Jan 19 15:16:40 2009
+// Last Modified By: .
+// Last Modified On: .
+// Update Count    : 0
+// Status          : Unknown, Use with caution!
+`define InternalStateWidth 64
+
+module one_step_tb();
+   reg clk, enable;
+   reg [`InternalStateWidth:1] in_state;
+   wire[`InternalStateWidth:1] out_state;
+
+   one_step one_step_inst(
+			  .clk(clk),
+			  .enable(enable),
+			  .in_state(in_state),
+			  .out_state(out_state)
+			  );
+   always
+   begin
+      #5 clk = !clk;
+   end
+
+   initial
+   begin
+      clk = 1'b1;
+      enable = 1'b1;
+      in_state = `InternalStateWidth'd1;
+      #5  in_state = `InternalStateWidth'b1110010110111111000110110101111000000111001010000110010010100010;
+      #10 in_state = `InternalStateWidth'b1110010110111111000110101011110000001110010110001100100101000101;
+      #10 in_state = `InternalStateWidth'b1100101101111110001101001011110000001110010110011001001010001010;
+      #10 in_state = `InternalStateWidth'b1100101101111110001101010111100000011100101110110010010100010101;
+      #10 in_state = `InternalStateWidth'b1001011011111100011010010111100000011100101111100100101000101011;
+      #10 in_state = `InternalStateWidth'b1001011011111100011010001111000000111001011111001001010001010110;
+      #10 in_state = `InternalStateWidth'b0010110111111000110100111110000001110010111111001001010001010110;
+      
+      #20 $finish;
+   end
+  
+   initial
+   begin    
+      $dumpvars;
+      $dumpfile("one_step_tb.vcd");
+      $dumpon;
+      #90 $dumpoff;
+   end   
+endmodule
\ No newline at end of file
-- 
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