From 98f9d442b44dbe2e3e4b3c8296be7e78d5d05450 Mon Sep 17 00:00:00 2001 From: Harald Welte Date: Sun, 24 Jul 2011 09:39:28 +0200 Subject: initial import of the usb ccid example for the sam7s --- resources/gdb/at91sam9263-ek-sdram.gdb | 78 ++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) create mode 100644 resources/gdb/at91sam9263-ek-sdram.gdb (limited to 'resources/gdb/at91sam9263-ek-sdram.gdb') diff --git a/resources/gdb/at91sam9263-ek-sdram.gdb b/resources/gdb/at91sam9263-ek-sdram.gdb new file mode 100644 index 0000000..b0e139f --- /dev/null +++ b/resources/gdb/at91sam9263-ek-sdram.gdb @@ -0,0 +1,78 @@ +# SDRAM initialization script for the AT91SAM9263 +#------------------------------------------------ +# Configure master clock +echo Configuring the master clock...\n +# Enable main oscillator +set *0xFFFFFC20 = 0x00004001 +while ((*0xFFFFFC68 & 0x1) == 0) +end + +# Set PLLA to 200MHz +set *0xFFFFFC28 = 0x206DBF09 +while ((*0xFFFFFC68 & 0x2) == 0) +end + +# Set PLLB for USB usage +set *0xFFFFFC2C = 0x20AF3F0F +while ((*0xFFFFFC68 & 0x4) == 0) +end + +# Select prescaler +set *0xFFFFFC30 = 0x00000100 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +# Select master clock +set *0xFFFFFC30 = 0x00000102 +while ((*0xFFFFFC68 & 0x8) == 0) +end + +echo Master clock ok.\n +echo Configuring the SDRAM controller...\n + +# Configure PIOD as peripheral (D16/D31) +# __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory"); +set *0xFFFFF870 = 0xFFFF0000 +# __writeMemory32(0x00000000,0xFFFFF874,"Memory"); +set *0xFFFFF874 = 0x00000000 +# __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory"); +set *0xFFFFF804 = 0xFFFF0000 + +# Enable EBI chip select for the SDRAM +set *0xFFFFED20 = 0x2 + +# SDRAM configuration +set *0xFFFFE208 = 0x85227259 + +set *0xFFFFE200 = 0x1 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x2 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 +set *0xFFFFE200 = 0x4 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x3 +set *0x20000000 = 0 + +set *0xFFFFE200 = 0x0 +set *0x20000000 = 0 + +set *0xFFFFE204 = 0x2B7 + +echo SDRAM configuration ok.\n -- cgit v1.2.3