openpcd/openpicc/os, branch masterFirmware for the OpenPCD, OpenPICC and SIMtrace hardwarehttps://git.gnumonks.org/cgit/openpcd/atom?h=master2008-03-05T01:59:58+00:00Copy over the relevant changes from the sniffonly branch pending integration2008-03-05T01:59:58+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12008-03-05T01:59:58+00:00urn:sha1:3ee3c4a649545d1f132bca61cc7484f0d5c92638
git-svn-id: https://svn.openpcd.org:2342/trunk@442 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
New cleaned-up (and then messed up again) SSC code2008-02-29T08:53:20+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12008-02-29T08:53:20+00:00urn:sha1:ad5b96d584fc9962a9d8504067cd59697fb9a580
Better layering separation
git-svn-id: https://svn.openpcd.org:2342/trunk@434 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Modifications to USB code to allow blocks of more than 1 byte to be more efficiently sent.2008-02-20T10:58:58+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12008-02-20T10:58:58+00:00urn:sha1:3639a49edf440277793a608b251be4340c750b24
Should affect existing byte base code only marginally.
(Note: Not compliant with FreeRTOS' braindead coding style)
git-svn-id: https://svn.openpcd.org:2342/trunk@416 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Commit status quo. Partly or severely broken.2008-02-02T06:16:31+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12008-02-02T06:16:31+00:00urn:sha1:fa61e60d06e7a50fd3d681822a5f637f14582d80
git-svn-id: https://svn.openpcd.org:2342/trunk@402 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
New hardware version2007-12-19T05:04:39+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-19T05:04:39+00:00urn:sha1:5ec39e9732ba29d641c37b7739fbc97643ac1b9d
git-svn-id: https://svn.openpcd.org:2342/trunk@398 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Implement unrolled loop, have not yet measured performance2007-12-15T12:53:04+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-15T12:53:04+00:00urn:sha1:86c7c1ea486d01cb6f0cbd5f3bd8ab91e643489b
git-svn-id: https://svn.openpcd.org:2342/trunk@389 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Add complicated mechanism that should have brought clock cycle accurate measurement. Doesn't seem to work properly2007-12-12T04:44:38+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-12T04:44:38+00:00urn:sha1:e777e32afb32f8863d495eff68ea0a91b0793fac
git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Add new miller decoder (not working yet)2007-12-12T01:50:14+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-12T01:50:14+00:00urn:sha1:202b56a42c5e6a171ee43b469be48525d0e8e350
Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction
git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Several modifications to enable spinning until the correct phase is reached in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv)2007-12-11T18:48:39+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-11T18:48:39+00:00urn:sha1:d88d1207732a80156b5d2725b4c22869ef0b3d36
Still too much jitter (some bug in this code?)
git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Prevent late frames by spinning in SSC CP0 IRQ till end of short frame reception2007-12-09T06:10:56+00:00henrykhenryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed12007-12-09T06:10:56+00:00urn:sha1:ceb643380b02d0d8289e3ad75a495123414ace8c
Fix tc_cdiv_set_divider. again.
Reverse the polarity! (of the ssc transmit clock)
git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1