one step further to make it compile...

git-svn-id: https://svn.openpcd.org:2342/trunk@6 6dc7ffe9-61d6-0310-9af1-9938baff3ed1

8 files changed, 283 insertions, 22 deletions

diff --git a/openpcd/firmware/include/cl_rc632.h b/openpcd/firmware/include/cl_rc632.h
new file mode 100644
index 0000000..627e281
--- /dev/null
+++ b/openpcd/firmware/include/cl_rc632.h
@@ -0,0 +1,226 @@
+/* Register definitions for Philips CL RC632 RFID Reader IC
+ *
+ * (C) 2005 Harald Welte <laforge@gnumonks.org>
+ *
+ * Licensed under GNU General Public License, Version 2
+ */
+
+#ifndef _CLRC632_H
+#define _CLRC632_H
+
+enum rc632_registers {
+	RC632_REG_PAGE0			= 0x00,
+	RC632_REG_COMMAND		= 0x01,
+	RC632_REG_FIFO_DATA		= 0x02,
+	RC632_REG_PRIMARY_STATUS	= 0x03,
+	RC632_REG_FIFO_LENGTH		= 0x04,
+	RC632_REG_SECONDARY_STATUS	= 0x05,
+	RC632_REG_INTERRUPT_EN		= 0x06,
+	RC632_REG_INTERRUPT_RQ		= 0x07,
+
+	RC632_REG_PAGE1			= 0x08,
+	RC632_REG_CONTROL		= 0x09,
+	RC632_REG_ERROR_FLAG		= 0x0a,
+	RC632_REG_COLL_POS		= 0x0b,
+	RC632_REG_TIMER_VALUE		= 0x0c,
+	RC632_REG_CRC_RESULT_LSB	= 0x0d,
+	RC632_REG_CRC_RESULT_MSB	= 0x0e,
+	RC632_REG_BIT_FRAMING		= 0x0f,
+
+	RC632_REG_PAGE2			= 0x10,
+	RC632_REG_TX_CONTROL		= 0x11,
+	RC632_REG_CW_CONDUCTANCE	= 0x12,
+	RC632_REG_MOD_CONDUCTANCE	= 0x13,
+	RC632_REG_CODER_CONTROL		= 0x14,
+	RC632_REG_MOD_WIDTH		= 0x15,
+	RC632_REG_MOD_WIDTH_SOF		= 0x16,
+	RC632_REG_TYPE_B_FRAMING	= 0x17,
+
+	RC632_REG_PAGE3			= 0x18,
+	RC632_REG_RX_CONTROL1		= 0x19,
+	RC632_REG_DECODER_CONTROL	= 0x1a,
+	RC632_REG_BIT_PHASE		= 0x1b,
+	RC632_REG_RX_THRESHOLD		= 0x1c,
+	RC632_REG_BPSK_DEM_CONTROL	= 0x1d,
+	RC632_REG_RX_CONTROL2		= 0x1e,
+	RC632_REG_CLOCK_Q_CONTROL	= 0x1f,
+
+	RC632_REG_PAGE4			= 0x20,
+	RC632_REG_RX_WAIT		= 0x21,
+	RC632_REG_CHANNEL_REDUNDANCY	= 0x22,
+	RC632_REG_CRC_PRESET_LSB	= 0x23,
+	RC632_REG_CRC_PRESET_MSB	= 0x24,
+	RC632_REG_TIME_SLOT_PERIOD	= 0x25,
+	RC632_REG_MFOUT_SELECT		= 0x26,
+	RC632_REG_PRESET_27		= 0x27,
+
+	RC632_REG_PAGE5			= 0x28,
+	RC632_REG_FIFO_LEVEL		= 0x29,
+	RC632_REG_TIMER_CLOCK		= 0x2a,
+	RC632_REG_TIMER_CONTROL		= 0x2b,
+	RC632_REG_TIMER_RELOAD		= 0x2c,
+	RC632_REG_IRQ_PIN_CONFIG	= 0x2d,
+	RC632_REG_PRESET_2E		= 0x2e,
+	RC632_REG_PRESET_2F		= 0x2f,
+
+	RC632_REG_PAGE6			= 0x30,
+
+	RC632_REG_PAGE7			= 0x38,
+	RC632_REG_TEST_ANA_SELECT	= 0x3a,
+	RC632_REG_TEST_DIGI_SELECT	= 0x3d,
+};
+
+enum rc632_reg_command {
+	RC632_CMD_IDLE			= 0x00,
+	RC632_CMD_WRITE_E2		= 0x01,
+	RC632_CMD_READ_E2		= 0x03,
+	RC632_CMD_LOAD_CONFIG		= 0x07,
+	RC632_CMD_LOAD_KEY_E2		= 0x0b,
+	RC632_CMD_AUTHENT1		= 0x0c,
+	RC632_CMD_CALC_CRC		= 0x12,
+	RC632_CMD_AUTHENT2		= 0x14,
+	RC632_CMD_RECEIVE		= 0x16,
+	RC632_CMD_LOAD_KEY		= 0x19,
+	RC632_CMD_TRANSMIT		= 0x1a,
+	RC632_CMD_TRANSCEIVE		= 0x1e,
+	RC632_CMD_STARTUP		= 0x3f,
+};
+
+enum rc632_reg_interrupt {
+	RC632_INT_LOALERT		= 0x01,
+	RC632_INT_HIALERT		= 0x02,
+	RC632_INT_IDLE			= 0x04,
+	RC632_INT_RX			= 0x08,
+	RC632_INT_TX			= 0x10,
+	RC632_INT_TIMER			= 0x20,
+	RC632_INT_SET			= 0x80,
+};
+
+enum rc632_reg_control {
+	RC632_CONTROL_CRYPTO1_ON	= 0x08,
+	RC632_CONTROL_POWERDOWN		= 0x10,
+};
+
+enum rc632_reg_error_flag {
+	RC632_ERR_FLAG_COL_ERR		= 0x01,
+	RC632_ERR_FLAG_PARITY_ERR	= 0x02,
+	RC632_ERR_FLAG_FRAMING_ERR	= 0x04,
+	RC632_ERR_FLAG_CRC_ERR		= 0x08,
+	RC632_ERR_FLAG_FIFO_OVERFLOW	= 0x10,
+	RC632_ERR_FLAG_ACCESS_ERR	= 0x20,
+	RC632_ERR_FLAG_KEY_ERR		= 0x40,
+};
+
+enum rc632_reg_tx_control {
+	RC632_TXCTRL_TX1_RF_EN		= 0x01,
+	RC632_TXCTRL_TX2_RF_EN		= 0x02,
+	RC632_TXCTRL_TX2_CW		= 0x04,
+	RC632_TXCTRL_TX2_INV		= 0x08,
+	RC632_TXCTRL_FORCE_100_ASK	= 0x10,
+
+	RC632_TXCTRL_MOD_SRC_LOW	= 0x00,
+	RC632_TXCTRL_MOD_SRC_HIGH	= 0x20,
+	RC632_TXCTRL_MOD_SRC_INT	= 0x40,
+	RC632_TXCTRL_MOD_SRC_MFIN	= 0x60,
+};
+
+enum rc632_reg_coder_control {
+	RC632_CDRCTRL_TXCD_NRZ		= 0x00,
+	RC632_CDRCTRL_TXCD_14443A	= 0x01,
+	RC632_CDRCTRL_TXCD_ICODE_STD	= 0x04,
+
+#define RC632_CDRCTRL_RATE_MASK		0x38
+	RC632_CDRCTRL_RATE_848K		= 0x00,
+	RC632_CDRCTRL_RATE_424K		= 0x08,
+	RC632_CDRCTRL_RATE_212K		= 0x10,
+	RC632_CDRCTRL_RATE_106K		= 0x18,
+	RC632_CDRCTRL_RATE_14443B	= 0x20,
+	RC632_CDRCTRL_RATE_15693	= 0x28,
+	RC632_CDRCTRL_RATE_ICODE_FAST	= 0x30,
+};
+
+enum rc632_erg_type_b_framing {
+	RC632_TBFRAMING_SOF_10L_2H	= 0x00,
+	RC632_TBFRAMING_SOF_10L_3H	= 0x01,
+	RC632_TBFRAMING_SOF_11L_2H	= 0x02,
+	RC632_TBFRAMING_SOF_11L_3H	= 0x03,
+
+	RC632_TBFRAMING_EOF_10		= 0x00,
+	RC632_TBFRAMING_EOF_11		= 0x20,
+
+	RC632_TBFRAMING_NO_TX_SOF	= 0x80,
+	RC632_TBFRAMING_NO_TX_EOF	= 0x40,
+};
+#define	RC632_TBFRAMING_SPACE_SHIFT	2
+#define RC632_TBFRAMING_SPACE_MASK	7
+
+enum rc632_reg_rx_control1 {
+	RC632_RXCTRL1_GAIN_20DB		= 0x00,
+	RC632_RXCTRL1_GAIN_24DB		= 0x01,
+	RC632_RXCTRL1_GAIN_31DB		= 0x02,
+	RC632_RXCTRL1_GAIN_35DB		= 0x03,
+
+	RC632_RXCTRL1_LP_OFF		= 0x04,
+	RC632_RXCTRL1_ISO15693		= 0x08,
+	RC632_RXCTRL1_ISO14443		= 0x10,
+
+#define RC632_RXCTRL1_SUBCP_MASK	0xe0
+	RC632_RXCTRL1_SUBCP_1		= 0x00,
+	RC632_RXCTRL1_SUBCP_2		= 0x20,
+	RC632_RXCTRL1_SUBCP_4		= 0x40,
+	RC632_RXCTRL1_SUBCP_8		= 0x60,
+	RC632_RXCTRL1_SUBCP_16		= 0x80,
+};
+
+enum rc632_reg_decoder_control {
+	RC632_DECCTRL_MANCHESTER	= 0x00,
+	RC632_DECCTRL_BPSK		= 0x01,
+
+	RC632_DECCTRL_RX_INVERT		= 0x04,
+
+	RC632_DECCTRL_RXFR_ICODE	= 0x00,
+	RC632_DECCTRL_RXFR_14443A	= 0x08,
+	RC632_DECCTRL_RXFR_15693	= 0x10,
+	RC632_DECCTRL_RXFR_14443B	= 0x18,
+
+	RC632_DECCTRL_ZEROAFTERCOL	= 0x20,
+
+	RC632_DECCTRL_RX_MULTIPLE	= 0x40,
+};
+
+enum rc632_reg_bpsk_dem_control {
+	RC632_BPSKD_TAUB_SHIFT		= 0x00,
+	RC632_BPSKD_TAUB_MASK		= 0x03,
+	
+	RC632_BPSKD_TAUD_SHIFT		= 0x02,
+	RC632_BPSKD_TAUD_MASK		= 0x03,
+
+	RC632_BPSKD_FILTER_AMP_DETECT	= 0x10,
+	RC632_BPSKD_NO_RX_EOF		= 0x20,
+	RC632_BPSKD_NO_RX_EGT		= 0x40,
+	RC632_BPSKD_NO_RX_SOF		= 0x80,
+};
+
+enum rc632_reg_rx_control2 {
+	RC632_RXCTRL2_DECSRC_LOW	= 0x00,
+	RC632_RXCTRL2_DECSRC_INT	= 0x01,
+	RC632_RXCTRL2_DECSRC_SUBC_MFIN	= 0x10,
+	RC632_RXCTRL2_DECSRC_BASE_MFIN	= 0x11,
+
+	RC632_RXCTRL2_AUTO_PD		= 0x40,
+	RC632_RXCTRL2_CLK_I		= 0x80,
+	RC632_RXCTRL2_CLK_Q		= 0x00,
+};
+
+enum rc632_reg_channel_redundancy {
+	RC632_CR_PARITY_ENABLE		= 0x01,
+	RC632_CR_PARITY_ODD		= 0x02,
+	RC632_CR_TX_CRC_ENABLE		= 0x04,
+	RC632_CR_RX_CRC_ENABLE		= 0x08,
+	RC632_CR_CRC8			= 0x10,
+	RC632_CR_CRC3309		= 0x20,
+};
+
+
+
+#endif
diff --git a/openpcd/firmware/include/lib_AT91SAM7S64.h b/openpcd/firmware/include/lib_AT91SAM7S64.h
index ec841a4..10d9322 100644
--- a/openpcd/firmware/include/lib_AT91SAM7S64.h
+++ b/openpcd/firmware/include/lib_AT91SAM7S64.h
@@ -40,6 +40,8 @@
 #ifndef lib_AT91SAM7S64_H
 #define lib_AT91SAM7S64_H
 
+#include <include/AT91SAM7S64.h>
+
 /* *****************************************************************************
                 SOFTWARE API FOR AIC
    ***************************************************************************** */
diff --git a/openpcd/firmware/include/openpcd.h b/openpcd/firmware/include/openpcd.h
new file mode 100644
index 0000000..dd68d52
--- /dev/null
+++ b/openpcd/firmware/include/openpcd.h
@@ -0,0 +1,9 @@
+#ifndef _OPENPCD_H
+#define _OPENPCD_H
+
+#include <include/AT91SAM7S64.h>
+
+#define OPENPCD_RC632_IRQ	AT91C_ID_IRQ1
+#define OPENPCD_RC632_RESET	AT91C_PIO_PA29
+
+#endif
diff --git a/openpcd/firmware/src/fifo.c b/openpcd/firmware/src/fifo.c
index 67a99e7..5bb0015 100644
--- a/openpcd/firmware/src/fifo.c
+++ b/openpcd/firmware/src/fifo.c
@@ -2,6 +2,9 @@
 
 #include "fifo.h"
 
+#include <errno.h>
+#include <string.h>
+
 #define FIFO_IRQ_LO	0x01
 #define FIFO_IRQ_HI	0x02
 #define FIFO_IRQ_OFLOW	0x04
@@ -33,7 +36,7 @@ void fifo_check_water(struct fifo *fifo)
 void fifo_check_raise_int(struct fifo *fifo)
 {
 	if (fifo->irq & fifo->irq_en)
-		fifo->cb(fifo, fifo->irq, fifo->cb_data);
+		fifo->callback(fifo, fifo->irq, fifo->cb_data);
 }
 
 
@@ -42,7 +45,7 @@ u_int16_t fifo_data_put(struct fifo *fifo, u_int16_t len, u_int8_t *data)
 	u_int16_t old_producer = fifo->producer;
 
 	if (len > fifo_available(fifo)) {
-		len = fifo_available(fifo)
+		len = fifo_available(fifo);
 		fifo->irq |= FIFO_IRQ_OFLOW;
 	}
 
@@ -89,7 +92,8 @@ u_int16_t fifo_data_get(struct fifo *fifo, u_int16_t len, u_int8_t *data)
 	return len;
 }
 
-int fifo_init(struct fifo *fifo, u_int16_t size, void *cb_data)
+int fifo_init(struct fifo *fifo, u_int16_t size, 
+	      void (*cb)(struct fifo *fifo, u_int8_t event, void *data), void *cb_data)
 {
 	if (size > sizeof(fifo->data))
 		return -EINVAL;
@@ -98,7 +102,7 @@ int fifo_init(struct fifo *fifo, u_int16_t size, void *cb_data)
 	fifo->size = size;
 	fifo->producer = fifo->consumer = 0;
 	fifo->watermark = 0;
-	fifo->cb = cb;
+	fifo->callback = cb;
 	fifo->cb_data = cb_data;
 
 	return 0;
diff --git a/openpcd/firmware/src/fifo.h b/openpcd/firmware/src/fifo.h
index 148625b..324dad6 100644
--- a/openpcd/firmware/src/fifo.h
+++ b/openpcd/firmware/src/fifo.h
@@ -19,7 +19,8 @@ struct fifo {
 };
 
 
-extern int fifo_init(struct fifo *fifo, u_int16_t size, void *cb_data);
+extern int fifo_init(struct fifo *fifo, u_int16_t size, 
+		     void (*callback)(struct fifo *fifo, u_int8_t event, void *data), void *cb_data);
 extern u_int16_t fifo_data_get(struct fifo *fifo, u_int16_t len, u_int8_t *data);
 extern u_int16_t fifo_data_put(struct fifo *fifo, u_int16_t len, u_int8_t *data);
 extern int fifo_available(struct fifo *fifo);
diff --git a/openpcd/firmware/src/main.c b/openpcd/firmware/src/main.c
index 342c258..5cf72fa 100644
--- a/openpcd/firmware/src/main.c
+++ b/openpcd/firmware/src/main.c
@@ -17,7 +17,7 @@
 //* 1.4 27/Apr/05 JPP   : Unset the USART_COM and suppress displaying data
 //*--------------------------------------------------------------------------------------
 
-//#include "board.h"
+#include <include/lib_AT91SAM7S64.h>
 #include "dbgu.h"
 #include "pcd_enumerate.h"
 
diff --git a/openpcd/firmware/src/pio_irq.h b/openpcd/firmware/src/pio_irq.h
index ecb1a2c..86021df 100644
--- a/openpcd/firmware/src/pio_irq.h
+++ b/openpcd/firmware/src/pio_irq.h
@@ -1,6 +1,8 @@
 #ifndef _PIO_IRQ_H
 #define _PIO_IRQ_H
 
+#include <include/AT91SAM7S64.h>
+
 typedef irq_handler_t (void)(u_int32_t pio);
 
 static irq_handler_t pio_handlers[NR_PIO];
diff --git a/openpcd/firmware/src/rc632.c b/openpcd/firmware/src/rc632.c
index 422815d..e09cd84 100644
--- a/openpcd/firmware/src/rc632.c
+++ b/openpcd/firmware/src/rc632.c
@@ -3,8 +3,16 @@
  *
  * */
 
+#include <include/lib_AT91SAM7S64.h>
+#include <include/cl_rc632.h>
+#include <include/openpcd.h>
+
+#include <string.h>
+
 #include "fifo.h"
-#include "pio_irq.h"
+//#include "pio_irq.h"
+
+static AT91PS_SPI pSPI = AT91C_BASE_SPI;
 
 static void spi_irq(void)
 {
@@ -24,24 +32,26 @@ struct rc632 {
 	u_int16_t flags;
 	struct fifo fifo;
 };
-
 #define RC632_F_FIFO_TX		0x0001
 
+static struct rc632 rc632;
+
 
 /* RC632 access primitives */
 
 void rc632_reg_write(u_int8_t addr, u_int8_t data)
 {
 	addr = (addr << 1) & 0x7e;
+	/* FIXME: transceive */
 }
 
-void rc632_fifo_write(u_int8_t len, u_int8_t *data)
+int rc632_fifo_write(u_int8_t len, u_int8_t *data)
 {
 	if (len > sizeof(spi_outbuf)-1)
 		len = sizeof(spi_outbuf)-1;
 
 	spi_outbuf[0] = FIFO_ADDR;
-	memcpy(spi_outbuf[1], data, len);
+	memcpy(&spi_outbuf[1], data, len);
 
 	/* FIXME: transceive (len+1) */
 
@@ -51,6 +61,8 @@ void rc632_fifo_write(u_int8_t len, u_int8_t *data)
 u_int8_t rc632_reg_read(u_int8_t addr)
 {
 	addr = (addr << 1) & 0x7e;
+	/* FIXME: transceive */
+	return 0;
 }
 
 u_int8_t rc632_fifo_read(u_int8_t max_len, u_int8_t *data)
@@ -82,42 +94,47 @@ static void rc632_irq(void)
 
 	if (cause & RC632_INT_LOALERT) {
 		/* FIFO is getting low, refill from virtual FIFO */
-		if (!fifo_available(fifo))
-			break;
+		if (!fifo_available(&rc632.fifo))
+			return;
+		/* FIXME */
 	}
 	if (cause & RC632_INT_HIALERT) {
 		/* FIFO is getting full, empty into virtual FIFO */
+		/* FIXME */
 	}
-	if (cause & RCR632_INT_TIMER) {
+	if (cause & RC632_INT_TIMER) {
 		/* Timer has expired, signal it to host */
+		/* FIXME */
 	}
 }
 
 void rc632_init(void)
 {
+	fifo_init(&rc632.fifo, 256, NULL, &rc632);
+
 	AT91F_SPI_CfgPMC();
 	AT91F_SPI_CfgPIO();	/* check whether we really need all this */
-	AT91F_SPI_Enable();
+	AT91F_SPI_Enable(pSPI);
 
-	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI, F,
+	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI, AT91C_AIC_PRIOR_LOWEST,
 			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &spi_irq);
 	AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SPI);
 	AT91F_SPI_EnableIt(pSPI, AT91C_SPI_MODF|AT91C_SPI_OVRES);
-	AT91F_SPI_CfgMode(AT91C_SPI_MSTR|AT91C_SPI_PS_FIXED);
+	AT91F_SPI_CfgMode(pSPI, AT91C_SPI_MSTR|AT91C_SPI_PS_FIXED);
 	/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = 10 (4.8MHz), 
 	 * DLYBS = 0, DLYBCT = 0 */
-	AT91F_SPI_CfgCs(pSPI, 0, AT91C_SPI_BITS8|AT91C_SPI_NCPHA|(10<<8));
-	AT91F_SPI_Reset();
+	AT91F_SPI_CfgCs(pSPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(10<<8));
+	AT91F_SPI_Reset(pSPI);
 
 	/* Register rc632_irq */
-	pio_irq_register(OPENPCD_RC632_IRQ, &rc632_irq);
-	pio_irq_enable(OPENPCD_RC632_IRQ);
+	//pio_irq_register(OPENPCD_RC632_IRQ, &rc632_irq);
+	//pio_irq_enable(OPENPCD_RC632_IRQ);
 	AT91F_PIO_CfgOutput(AT91C_BASE_PIOA, OPENPCD_RC632_RESET);
 };
 
 void rc632_exit(void)
 {
-	pio_irq_unregister(OPENPCD_RC632_IRQ);
+	//pio_irq_unregister(OPENPCD_RC632_IRQ);
 	AT91F_AIC_DisableIt(AT91C_BASE_AIC, AT91C_ID_SPI);
-	AT01F_SPI_Disable();
+	AT91F_SPI_Disable(pSPI);
 }