diff options
| author | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-09-09 17:20:13 +0000 |
|---|---|---|
| committer | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-09-09 17:20:13 +0000 |
| commit | 48fbcc6bff88cddfee7288489c96b93bb1436875 (patch) | |
| tree | df58ce3256b4d160674137e3443996339b1f1560 | |
| parent | 84f258ce3e60ce2876dccb2a1b56edea39b891c7 (diff) | |
- remove bogus comment
git-svn-id: https://svn.openpcd.org:2342/trunk@159 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
| -rw-r--r-- | openpcd/firmware/src/picc/tc_fdt.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/openpcd/firmware/src/picc/tc_fdt.c b/openpcd/firmware/src/picc/tc_fdt.c index cc7729a..37194ad 100644 --- a/openpcd/firmware/src/picc/tc_fdt.c +++ b/openpcd/firmware/src/picc/tc_fdt.c @@ -1,13 +1,9 @@ /* OpenPC TC (Timer / Clock) support code * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de> * - * This idea of this code is to feed the 13.56MHz carrier clock of RC632 - * into TCLK1, which is routed to XC1. Then configure TC0 to divide this - * clock by a configurable divider. - * * PICC Simulator Side: * In order to support responding to synchronous frames (REQA/WUPA/ANTICOL), - * we need a second Timer/Counter (TC1). This unit is reset by an external + * we need a second Timer/Counter (TC2). This unit is reset by an external * event (rising edge of modulation pause PCD->PICC) connected to TIOB2, and * counts up to a configurable number of carrier clock cycles (RA). Once the * RA value is reached, TIOA2 will see a rising edge. This rising edge will |