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author(no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2006-08-08 16:39:51 +0000
committer(no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2006-08-08 16:39:51 +0000
commite0487263bc2adb6bd4e3246a856d8d3adb957ad3 (patch)
tree5337b0663f5d8716c50aa003e0e7b96fbf4309da
parent52985be4417d97beb2bbd95bdd2dd53be516ceda (diff)
add TC code for software-configurable division of carrier clock
git-svn-id: https://svn.openpcd.org:2342/trunk@81 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
-rw-r--r--openpcd/firmware/Makefile2
-rw-r--r--openpcd/firmware/src/main_pwm.c31
-rw-r--r--openpcd/firmware/src/tc.c74
-rw-r--r--openpcd/firmware/src/tc.h24
4 files changed, 127 insertions, 4 deletions
diff --git a/openpcd/firmware/Makefile b/openpcd/firmware/Makefile
index 247dcd5..531342a 100644
--- a/openpcd/firmware/Makefile
+++ b/openpcd/firmware/Makefile
@@ -74,7 +74,7 @@ SRC =
# use file-extension c for "c-only"-files
SRCARM = lib/lib_AT91SAM7.c src/pcd_enumerate.c src/fifo.c src/dbgu.c \
src/led.c src/rc632.c src/rc632_highlevel.c src/req_ctx.c \
- src/trigger.c src/main.c src/syscalls.c src/pwm.c \
+ src/trigger.c src/main.c src/syscalls.c src/pwm.c src/tc.c \
src/$(TARGET).c src/start/Cstartup_SAM7.c
SRCARM += src/rfid_layer2_iso14443a.c
diff --git a/openpcd/firmware/src/main_pwm.c b/openpcd/firmware/src/main_pwm.c
index f39a55a..20659cb 100644
--- a/openpcd/firmware/src/main_pwm.c
+++ b/openpcd/firmware/src/main_pwm.c
@@ -52,6 +52,10 @@ static u_int8_t rsrel_table[] = {
37, 26, 27, 51, 38, 28, 29, 39, 30, 52, 31, 40, 41, 53, 42, 43,
54, 44, 45, 55, 46, 47, 56, 57, 58, 59, 60, 61, 62, 63 };
+
+static u_int16_t cdivs[] = { 128, 64, 32, 16 };
+static int cdiv_idx = 0;
+
static void help(void)
{
DEBUGPCR("o: decrease duty p: increase duty\r\n"
@@ -75,13 +79,18 @@ void _init_func(void)
/* switch PA17 (connected to MFIN on board) to input */
AT91F_PIO_CfgInput(AT91C_BASE_PIOA, AT91C_PIO_PA17);
- pwm_init();
- rc632_modulate_mfin();
+ DEBUGPCRF("Initializing carrier divider");
+ tc_cdiv_init();
+ DEBUGPCRF("Initializing PWM");
+ pwm_init();
pwm_freq_set(0, 105937);
pwm_start(0);
-
pwm_duty_set_percent(0, 22); /* 22% of 9.43uS = 2.07uS */
+ rc632_modulate_mfin();
+
+ DEBUGPCRF("Initializing SSC RX");
+ ssc_rx_init();
}
int _main_dbgu(char key)
@@ -182,6 +191,22 @@ int _main_dbgu(char key)
help();
return 0;
break;
+ case '<':
+ tc_cdiv_phase_inc();
+ break;
+ case '>':
+ tc_cdiv_phase_dec();
+ break;
+ case '{':
+ if (cdiv_idx > 0)
+ cdiv_idx--;
+ tc_cdiv_set_divider(cdivs[cdiv_idx]);
+ break;
+ case '}':
+ if (cdiv_idx < ARRAY_SIZE(cdivs)-1)
+ cdiv_idx++;
+ tc_cdiv_set_divider(cdivs[cdiv_idx]);
+ break;
default:
return -EINVAL;
}
diff --git a/openpcd/firmware/src/tc.c b/openpcd/firmware/src/tc.c
new file mode 100644
index 0000000..4ee28ba
--- /dev/null
+++ b/openpcd/firmware/src/tc.c
@@ -0,0 +1,74 @@
+/* OpenPC TC (Timer / Clock) support code
+ * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
+ *
+ * This idea of this code is to feed the 13.56MHz carrier clock of RC632
+ * into TCLK1, which is routed to XC1. Then configure TC0 to divide this
+ * clock by
+ */
+
+#include <lib_AT91SAM7.h>
+#include "openpcd.h"
+#include "dbgu.h"
+#include "tc.h"
+
+static AT91PS_TCB tcb = AT91C_BASE_TCB;
+
+/* set carrier divider to a specific */
+void tc_cdiv_set_divider(u_int16_t div)
+{
+ tcb->TCB_TC0.TC_RC = div;
+
+ /* set to 50% duty cycle */
+ tcb->TCB_TC0.TC_RA = 0;
+ tcb->TCB_TC0.TC_RB = div >> 1;
+}
+
+void tc_cdiv_phase_add(int16_t inc)
+{
+ tcb->TCB_TC0.TC_RA = (tcb->TCB_TC0.TC_RA + inc) % tcb->TCB_TC0.TC_RC;
+ tcb->TCB_TC0.TC_RB = (tcb->TCB_TC0.TC_RB + inc) % tcb->TCB_TC0.TC_RC;
+}
+
+void tc_cdiv_init(void)
+{
+ /* Cfg PIO28 as Periph B */
+ AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, OPENPCD_PIO_CARRIER|
+ OPENPCD_PIO_CARRIER_DIV);
+
+ AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
+ ((unsigned int) 1 << AT91C_ID_TC0));
+
+ /* Enable Clock for TC0 */
+ tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN;
+
+ /* Connect TCLK1 to XC1 */
+ tcb->TCB_BMR &= ~AT91C_TCB_TC1XC1S;
+ tcb->TCB_BMR |= AT91C_TCB_TC1XC1S_TCLK1;
+
+ tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
+ AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPC_SET |
+ AT91C_TC_BCPC_CLEAR | AT91C_TC_EEVT_XC0;
+
+ tc_cdiv_set_divider(128);
+
+ /* Reset to start timers */
+ tcb->TCB_BCR = 1;
+}
+
+void tc_cdiv_print(void)
+{
+ DEBUGP("TCB_BMR=0x%08x ", tcb->TCB_BMR);
+ DEBUGP("TC0_CV=0x%08x ", tcb->TCB_TC0.TC_CV);
+ DEBUGP("TC0_CMR=0x%08x ", tcb->TCB_TC0.TC_CMR);
+ DEBUGPCR("TC0_SR=0x%08x", tcb->TCB_TC0.TC_SR);
+
+ DEBUGPCR("TC0_RA=0x%04x, TC0_RB=0x%04x, TC0_RC=0x%04x",
+ tcb->TCB_TC0.TC_RA, tcb->TCB_TC0.TC_RB, tcb->TCB_TC0.TC_RC);
+}
+
+void tc_cdiv_fini(void)
+{
+ tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKDIS;
+ AT91F_PMC_DisablePeriphClock(AT91C_BASE_PMC,
+ ((unsigned int) 1 << AT91C_ID_TC0));
+}
diff --git a/openpcd/firmware/src/tc.h b/openpcd/firmware/src/tc.h
new file mode 100644
index 0000000..763992c
--- /dev/null
+++ b/openpcd/firmware/src/tc.h
@@ -0,0 +1,24 @@
+#ifndef _TC_H
+#define _TC_H
+
+#include <sys/types.h>
+
+extern void tc_cdiv_phase_add(int16_t inc);
+extern void tc_cdiv_set_divider(u_int16_t div);
+
+static inline void tc_cdiv_phase_inc(void)
+{
+ tc_cdiv_phase_add(1);
+}
+
+static inline void tc_cdiv_phase_dec(void)
+{
+ tc_cdiv_phase_add(-1);
+}
+
+
+extern void tc_cdiv_print(void);
+extern void tc_cdiv_init(void);
+extern void tc_cdiv_fini(void);
+
+#endif
personal git repositories of Harald Welte. Your mileage may vary