diff options
| author | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-03 04:55:57 +0000 |
|---|---|---|
| committer | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-03 04:55:57 +0000 |
| commit | e22f23efcbe54ab8aabfd54f8b55a5d01a15a487 (patch) | |
| tree | 015aa7b5dcf063d4fc594eb4fade40cd086ae924 /openpicc/application/tc_cdiv.c | |
| parent | 67d9be99569c49671b4cc2217824307202b92439 (diff) | |
* Reduce leaking of TX buffers
* Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which
stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would
have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct.
* Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly
git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc/application/tc_cdiv.c')
| -rw-r--r-- | openpicc/application/tc_cdiv.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/openpicc/application/tc_cdiv.c b/openpicc/application/tc_cdiv.c index 638586d..3bbfe77 100644 --- a/openpicc/application/tc_cdiv.c +++ b/openpicc/application/tc_cdiv.c @@ -38,6 +38,10 @@ void tc_cdiv_set_divider(u_int16_t div) /* set to 50% duty cycle */ tcb->TCB_TC0.TC_RA = 1; tcb->TCB_TC0.TC_RB = 1 + (div >> 1); + + /* Save current CV as phase, then reset to 0 (might otherwise be greater than RC) */ + tc_cdiv_phase_add(tcb->TCB_TC0.TC_RC-(tcb->TCB_TC0.TC_CV%tcb->TCB_TC0.TC_RC)); + tcb->TCB_TC0.TC_CCR = AT91C_TC_SWTRG; } void tc_cdiv_phase_add(int16_t inc) |