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| author | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-05 15:36:56 +0000 |
|---|---|---|
| committer | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-05 15:36:56 +0000 |
| commit | ba63352b4b915e46bc44fbd98c6e0e837477005d (patch) | |
| tree | 6d49eaab495d2fa9a8d8ebda9922b0ceeacac84f /openpicc/fdt_timing.dia | |
| parent | 1cdcc383d801f6468e2937475be3b98af231f4cf (diff) | |
Revamp SSC buffer handling, should severely reduce buffer leakage
Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise
Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug
git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc/fdt_timing.dia')
0 files changed, 0 insertions, 0 deletions