diff options
| author | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-12 04:44:38 +0000 |
|---|---|---|
| committer | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-12 04:44:38 +0000 |
| commit | e777e32afb32f8863d495eff68ea0a91b0793fac (patch) | |
| tree | a81dfdeb7211fc5ad4da5df06e1294f12b7ba724 /openpicc | |
| parent | 202b56a42c5e6a171ee43b469be48525d0e8e350 (diff) | |
Add complicated mechanism that should have brought clock cycle accurate measurement. Doesn't seem to work properly
git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc')
| -rw-r--r-- | openpicc/application/iso14443_layer3a.c | 1 | ||||
| -rw-r--r-- | openpicc/os/boot/boot.s | 40 |
2 files changed, 38 insertions, 3 deletions
diff --git a/openpicc/application/iso14443_layer3a.c b/openpicc/application/iso14443_layer3a.c index 35152db..4e077d5 100644 --- a/openpicc/application/iso14443_layer3a.c +++ b/openpicc/application/iso14443_layer3a.c @@ -94,6 +94,7 @@ void iso14443_transmit(ssc_dma_tx_buffer_t *buf, int fdt, int div) ssc_tx_fiq_fdt_cdiv = fdt -3*div -1; tc_fdt_set(ssc_tx_fiq_fdt_cdiv -MAX_TF_FIQ_ENTRY_DELAY -MAX_TF_FIQ_OVERHEAD); ssc_tx_fiq_fdt_ssc = fdt -div +1; + *AT91C_TC0_CCR = AT91C_TC_CLKDIS; ssc_tx_start(buf); } diff --git a/openpicc/os/boot/boot.s b/openpicc/os/boot/boot.s index c065a6d..0371b6e 100644 --- a/openpicc/os/boot/boot.s +++ b/openpicc/os/boot/boot.s @@ -51,7 +51,7 @@ .equ SSC_CR, 0x0 .equ SSC_RCMR, 0x10 .equ SSC_CR_TXEN, 0x100 -.equ AT91C_TC_SWTRG, (1 << 2) +.equ AT91C_TC_SWTRG, ((1 << 2)|1) .equ AT91C_TC_CLKEN, (1 << 0) .equ PIO_DATA, (1 << 27) .equ PIO_FRAME, (1 << 20) @@ -257,7 +257,7 @@ my_fiq_handler: * At 47.923200 MHz 7 processor cycles are 2 carrier cycles of the 13.56MHz carrier */ .equ SUB_TIME, 20 /* subtract 20 carrier cycles == 70 processor cycles */ - .equ ADD_TIME, (70-20) /* Add x processor cycles */ + .equ ADD_TIME, (70-30) /* Add x processor cycles */ mov r8, #SUB_TIME sub r11, r11, r8 @@ -275,7 +275,41 @@ my_fiq_handler: mov r11, r11, ASR #1 /* r11 = r11 / 2 */ mov r8, #ADD_TIME - add r11, r11, r8 /* r11 = r11 + ADD_TIME */ + adds r11, r11, r8 /* r11 = r11 + ADD_TIME */ + + bmi .wait_zero + +/* The following contraption is designed to compensate for the fact + that the loop below will only be able to count CPU cycles with a + precision of 4 cycles. Constraint: Since we want to keep the value + of r11 there's only one free register: r8.*/ + mov r8, #0x1 + tst r11, r8 + beq .wait_zero_or_two + bne .wait_one_or_three + +/* relative timing ------+ All code paths have the same number of CPU cycles, except + V for the relative timing given in these comments */ +.wait_zero_or_two: /* +0 */ + mov r8, #0x2 + tst r11, r8 + beq .wait_zero /* +0 */ + nop + bne .wait_two /* +2 */ + +.wait_one_or_three: /* +1 */ + mov r8, #0x2 + tst r11, r8 + beq .wait_one /* +0 */ + nop + bne .wait_three /* +2 */ + + nop /* Don't know if this nop is needed. Just add to make sure that nobody can assume that the "bne .wait_three" is no branch at all. */ + +.wait_three: +.wait_two: +.wait_one: +.wait_zero: mov r11, r11, ASR #2 /* r11 = r11 / 4 (4 is the number of cycles per loop run below) */ |