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-rw-r--r--firmware/include/openpcd.h22
-rw-r--r--firmware/include/openpicc_regs.h46
2 files changed, 62 insertions, 6 deletions
diff --git a/firmware/include/openpcd.h b/firmware/include/openpcd.h
index e6ccebe..9e2d45e 100644
--- a/firmware/include/openpcd.h
+++ b/firmware/include/openpcd.h
@@ -6,19 +6,29 @@
#include <sys/types.h>
struct openpcd_hdr {
- u_int8_t cmd; /* command. high nibble: class, low nibble: cmd */
+ u_int8_t cmd; /* command. high nibble: class,
+ * low nibble: cmd */
u_int8_t flags;
u_int8_t reg; /* register */
u_int8_t val; /* value (in case of write *) */
u_int8_t data[0];
} __attribute__ ((packed));
-#define OPENPC_FLAG_RESPOND 0x01 /* Response requested */
+#define OPCD_REV_LEN 16
+struct openpcd_compile_version {
+ char svnrev[OPCD_REV_LEN];
+ char by[OPCD_REV_LEN];
+ char date[OPCD_REV_LEN];
+} __attribute__ ((packed));
+
+#define OPENPCD_FLAG_RESPOND 0x01 /* Response requested */
+#define OPENPCD_FLAG_ERROR 0x80 /* An error occurred */
enum openpcd_cmd_class {
+ OPENPCD_CMD_CLS_GENERIC = 0x0,
/* PCD (reader) side */
OPENPCD_CMD_CLS_RC632 = 0x1,
- OPENPCD_CMD_CLS_LED = 0x2,
+ //OPENPCD_CMD_CLS_LED = 0x2,
OPENPCD_CMD_CLS_SSC = 0x3,
OPENPCD_CMD_CLS_PWM = 0x4,
OPENPCD_CMD_CLS_ADC = 0x5,
@@ -35,6 +45,9 @@ enum openpcd_cmd_class {
#define OPENPCD_CLS2CMD(x) (x << 4)
+#define OPENPCD_CMD_GET_VERSION (0x1|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_GENERIC))
+#define OPENPCD_CMD_SET_LED (0x2|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_GENERIC))
+
/* CMD_CLS_RC632 */
#define OPENPCD_CMD_WRITE_REG (0x1|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_RC632))
#define OPENPCD_CMD_WRITE_FIFO (0x2|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_RC632))
@@ -47,9 +60,6 @@ enum openpcd_cmd_class {
#define OPENPCD_CMD_DUMP_REGS (0x9|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_RC632))
#define OPENPCD_CMD_IRQ (0xa|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_RC632))
-/* CMD_CLS_LED */
-#define OPENPCD_CMD_SET_LED (0x1|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_LED))
-
/* CMD_CLS_SSC */
#define OPENPCD_CMD_SSC_READ (0x1|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_SSC))
#define OPENPCD_CMD_SSC_WRITE (0x2|OPENPCD_CLS2CMD(OPENPCD_CMD_CLS_SSC))
diff --git a/firmware/include/openpicc_regs.h b/firmware/include/openpicc_regs.h
new file mode 100644
index 0000000..2df0618
--- /dev/null
+++ b/firmware/include/openpicc_regs.h
@@ -0,0 +1,46 @@
+#ifndef _OPENPICC_STATE
+#define _OPENPICC_STATE
+
+/* according to ISO 14443-3(2000) 6.2 */
+enum opicc_14443a_state {
+ ISO14443A_ST_POWEROFF,
+ ISO14443A_ST_IDLE,
+ ISO14443A_ST_READY,
+ ISO14443A_ST_ACTIVE,
+ ISO14443A_ST_HALT,
+ ISO14443A_ST_READY2,
+ ISO14443A_ST_ACTIVE2,
+};
+
+enum opicc_reg_tx_control {
+ OPICC_REG_TX_BPSK = 0x01,
+ OPICC_REG_TX_MANCHESTER = 0x02,
+ OPICC_REG_TX_INTENSITY0 = 0x00,
+ OPICC_REG_TX_INTENSITY1 = 0x10,
+ OPICC_REG_TX_INTENSITY2 = 0x20,
+ OPICC_REG_TX_INTENSITY3 = 0x30,
+};
+
+enum opicc_reg {
+ OPICC_REG_14443A_UIDLEN,/* Length of UID in bytes */
+
+ OPICC_REG_14443A_FDT0, /* Frame delay time if last bit 0 */
+ OPICC_REG_14443A_FDT1, /* Frame delay time if last bit 1 */
+ OPICC_REG_14443A_STATE, /* see 'enum opicc_14443a_state' */
+
+ OPICC_REG_RX_CLK_DIV, /* Clock divider for Rx sample clock */
+ OPICC_REG_RX_CLK_PHASE, /* Phase shift of Rx sample clock */
+ OPICC_REG_RX_COMP_LEVEL,/* Comparator level of Demodulator */
+ OPICC_REG_RX_CONTROL,
+
+ OPICC_REG_TX_CLK_DIV, /* Clock divider for Tx sample clock */
+ OPICC_REG_TX_CONTROL, /* see 'enum opicc_reg_tx_Control */
+ _OPICC_NUM_REGS,
+};
+
+enum openpicc_14443a_sregs {
+ /* string 'registers' */
+ OPICC_REG_14443A_UID, /* The UID (4...10 bytes) */
+};
+
+#endif
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