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-rw-r--r--openpicc/os/core/ARM7_AT91SAM7S/portISR.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/openpicc/os/core/ARM7_AT91SAM7S/portISR.c b/openpicc/os/core/ARM7_AT91SAM7S/portISR.c
index 6f92c24..ec8d3d4 100644
--- a/openpicc/os/core/ARM7_AT91SAM7S/portISR.c
+++ b/openpicc/os/core/ARM7_AT91SAM7S/portISR.c
@@ -209,7 +209,9 @@ vPortEnterCritical (void)
"ORR R0, R0, #0x80 \n\t" /* Disable IRQ, don't disable FIQ. */
"MSR CPSR, R0 \n\t" /* Write back modified value. */
"LDMIA SP!, {R0}"); /* Pop R0. */
-
+#ifdef configDEBUG_CRITICAL_TIMING
+ *AT91C_PIOA_CODR = configDEBUG_CRITICAL_TIMING;
+#endif
/* Now interrupts are disabled ulCriticalNesting can be accessed
directly. Increment ulCriticalNesting to keep a count of how many times
portENTER_CRITICAL() has been called. */
@@ -228,6 +230,9 @@ vPortExitCritical (void)
re-enabled. */
if (ulCriticalNesting == portNO_CRITICAL_NESTING)
{
+#ifdef configDEBUG_CRITICAL_TIMING
+ *AT91C_PIOA_SODR = configDEBUG_CRITICAL_TIMING;
+#endif
/* Enable interrupts as per portEXIT_CRITICAL(). */
asm volatile ("STMDB SP!, {R0} \n\t" /* Push R0. */
"MRS R0, CPSR \n\t" /* Get CPSR. */
personal git repositories of Harald Welte. Your mileage may vary