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* Add SSC_DATA_GATE supporthenryk2007-12-204-3/+34
* New hardware versionhenryk2007-12-195-9/+55
* Play with transfer sizeshenryk2007-12-193-10/+68
* Optimizing (disabling debugging reduces time spent in decoder from 460us to 60ushenryk2007-12-171-20/+43
* That comment is not true anymorehenryk2007-12-161-6/+1
* Get SSC_MODE_14443A workinghenryk2007-12-163-9/+28
* Record size of SSC RX DMA buffers in transfers, much clearerhenryk2007-12-157-20/+89
* Standard state is still idlehenryk2007-12-151-2/+2
* Further the distinction between SSC and PDC transfersizehenryk2007-12-155-18/+24
* Prepare generic ISO 14443A reception mode (no short/standard distinction), pr...henryk2007-12-154-25/+51
* Implement unrolled loop, have not yet measured performancehenryk2007-12-151-59/+42
* Fix consistency checkhenryk2007-12-153-19/+21
* Sanitize and clarify the len handling in rx buffers.henryk2007-12-145-28/+44
* Add complicated mechanism that should have brought clock cycle accurate measu...henryk2007-12-122-3/+38
* Add new miller decoder (not working yet)henryk2007-12-129-35/+187
* Some more delayhenryk2007-12-111-3/+5
* Several modifications to enable spinning until the correct phase is reached i...henryk2007-12-119-34/+92
* Clean up SSC performance metric reportinghenryk2007-12-094-21/+47
* Prevent late frames by spinning in SSC CP0 IRQ till end of short frame receptionhenryk2007-12-095-9/+43
* Make it possible to send long frames for debugginghenryk2007-12-094-36/+82
* Change parity storage in frame structhenryk2007-12-092-3/+4
* Count and print late frameshenryk2007-12-094-3/+57
* inlined miller bit decode functionmeri2007-12-061-1/+1
* Fix stupid buffer leakage code in standard modehenryk2007-12-062-3/+5
* Obsolete commenthenryk2007-12-051-2/+0
* Add a kludge to make repetitive sends working. For some obscure reason the fi...henryk2007-12-052-0/+6
* Revamp SSC buffer handling, should severely reduce buffer leakagehenryk2007-12-055-154/+175
* remove old debugging #ifdef'shenryk2007-12-054-26/+10
* Change tc_cdiv_set_divider. The new code seems to work nearly perfect (jitter...henryk2007-12-041-2/+5
* Add (#ifdef'ed out) code to measure critical section timing with an LEDhenryk2007-12-042-1/+9
* Graphical explanation of what should/could happen when TC0 RC is re-set to a ...henryk2007-12-032-0/+0
* Disbale tracing again. Maybe that's giving less delay?henryk2007-12-031-1/+1
* ATQA needs to be transmitted with parityhenryk2007-12-031-1/+1
* * Reduce leaking of TX buffershenryk2007-12-033-3/+19
* Fix copy and paste error in prefill_bufferhenryk2007-12-031-1/+8
* Fix FIQ code for SSC TF emulationhenryk2007-12-031-8/+7
* Add dia file with timer design visualisationhenryk2007-12-022-2/+4
* Document the current state of the timers (e.g. what laforge did), partly as a...henryk2007-12-021-0/+59
* Fix power-on logic for the case that the card is already in the fieldhenryk2007-11-301-26/+25
* Fix SSC TX registers (especially the clock source selection), peripheral conf...henryk2007-11-294-7/+65
* Move to prefilling the transmit buffer for faster ATQA responsehenryk2007-11-292-33/+53
* Switch to hardcoded fiq handler implementation directly in the vector table (...henryk2007-11-292-105/+19
* Forgotten filehenryk2007-11-271-0/+5
* Print relevant SSC registershenryk2007-11-273-2/+18
* Restructure irq handling for setting tc_fdt (works now) and to get most iso s...henryk2007-11-265-73/+141
* Added automatic dependency generation to makefilehenryk2007-11-261-2/+11
* Remove unusedhenryk2007-11-261-67/+0
* Prepare transmission codehenryk2007-11-269-112/+265
* Add load modulation and encoding/decoding code from haraldhenryk2007-11-2411-3/+566
* hex and dec ...henryk2007-11-231-1/+1
personal git repositories of Harald Welte. Your mileage may vary