|  | Commit message (Collapse) | Author | Age | Files | Lines | 
|---|
| | 
| 
| 
| 
| 
| 
| | Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness)  in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction
git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| | git-svn-id: https://svn.openpcd.org:2342/trunk@354 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| | git-svn-id: https://svn.openpcd.org:2342/trunk@351 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| 
| | Currently working on fiq for pio data change to reset tc0 via swtrg
git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| 
| | Print version and compile date on help and config commands
git-svn-id: https://svn.openpcd.org:2342/trunk@332 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| | git-svn-id: https://svn.openpcd.org:2342/trunk@331 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| | or similar situations
git-svn-id: https://svn.openpcd.org:2342/trunk@330 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| 
| | Add adc code to read the field strength
git-svn-id: https://svn.openpcd.org:2342/trunk@325 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| 
| 
| | Almost all of these have not been checked yet, I just copied them over and hot-fixed compile time errors
F.e. all ssc usb code has been removed
git-svn-id: https://svn.openpcd.org:2342/trunk@323 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| 
| 
| 
| | (and a dummy dbgu.h)
git-svn-id: https://svn.openpcd.org:2342/trunk@322 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
| | 
| 
| 
| | git-svn-id: https://svn.openpcd.org:2342/trunk@312 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 | 
|  | git-svn-id: https://svn.openpcd.org:2342/trunk@311 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 |