openpcd - Firmware for the OpenPCD, OpenPICC and SIMtrace hardware

	Commit message (Collapse)	Author	Age	Files	Lines
*	Fix the clock gating for the new layer 2 code	henryk	2008-03-15	1	-0/+3
\| \| \| \| \| \| \|	Only perform the switch to continous when necessary since it has serious side effects in the current hardware (we really need TF ored into the clock gating) git-svn-id: https://svn.openpcd.org:2342/trunk@457 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Faked anticollision working now. During stress test (OpenPCD reqa firmware ↵	henryk	2008-03-14	1	-3/+11
\| \| \| \| \| \|	in anticol mode performing one cycle every 70ms) there were 52 late frames in 15992. git-svn-id: https://svn.openpcd.org:2342/trunk@454 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Add T/C based receiver code with integrated miller decoder	henryk	2008-03-14	1	-30/+41
\| \| \| \| \| \| \| \| \|	Integrate T/C receiver into iso14443 layer 2a Add state field to iso14443_frame, rename ssc buffer state constants Sniffer seems to work with the new code git-svn-id: https://svn.openpcd.org:2342/trunk@452 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Fix sending	henryk	2008-03-09	1	-0/+10
\| \| \| \| \| \| \| \| \| \| \|	Add Tx abort and SSC reset functionalities There is a bug workaround for a peculiarity in the SSC Tx: When it is set to START CONTINOUS while a transmission is in progress (started by START TF RISING EDGE, which is necessary for the correct timing) it will lose one (or two?) bits of sample data. The resetting of the start condition itself is necessary because the SSC will only transmit up to 64 bytes (32 bit times 16) per start condition Add performance counters for sent and received frames git-svn-id: https://svn.openpcd.org:2342/trunk@445 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	convert pio irq isr to a switching isr	henryk	2008-03-05	1	-1/+2
\| \| \| \|	git-svn-id: https://svn.openpcd.org:2342/trunk@444 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Port over the differential miller decoder from the sniffonly host tool	henryk	2008-03-05	1	-4/+6
\| \| \| \| \| \| \| \|	Move clock switch to its own header file Specify default (and for non-clock switching capable hardware: single) clock source in hardware definitions git-svn-id: https://svn.openpcd.org:2342/trunk@443 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	anticol working more often now	henryk	2008-03-04	1	-0/+6
\| \| \| \|	git-svn-id: https://svn.openpcd.org:2342/trunk@440 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Sending seems to be reliable now.	henryk	2008-03-03	1	-1/+5
\| \| \| \| \| \| \|	Once in a while (about 1 in 20) there's an error condition that's not being recovered from, need to investigate git-svn-id: https://svn.openpcd.org:2342/trunk@438 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Implement transmission	henryk	2008-03-03	1	-8/+84
\| \| \| \| \| \| \| \|	Implement a 'pretender' for PoC: Since Rx is not working properly we'll just pretend to have received something based on the approximate length. Clarify length calculations in machester encoder and remove obsolete test code git-svn-id: https://svn.openpcd.org:2342/trunk@437 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	New cleaned-up (and then messed up again) SSC code	henryk	2008-02-29	1	-51/+45
\| \| \| \| \| \| \|	Better layering separation git-svn-id: https://svn.openpcd.org:2342/trunk@434 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Commit a first version of an iso 14443 layer 2 and a passive sniffer. Works ↵	henryk	2008-02-09	1	-0/+172
	for short frames, and sometimes even for long frames. Pending some major cleanup git-svn-id: https://svn.openpcd.org:2342/trunk@408 6dc7ffe9-61d6-0310-9af1-9938baff3ed1