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path: root/openpicc/application/iso14443_layer3a.c
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* Add complicated mechanism that should have brought clock cycle accurate ↵henryk2007-12-121-0/+1
| | | | | | measurement. Doesn't seem to work properly git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add new miller decoder (not working yet)henryk2007-12-121-10/+17
| | | | | | | Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Several modifications to enable spinning until the correct phase is reached ↵henryk2007-12-111-8/+29
| | | | | | | | | in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv) Still too much jitter (some bug in this code?) git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Clean up SSC performance metric reportinghenryk2007-12-091-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@382 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Make it possible to send long frames for debugginghenryk2007-12-091-33/+65
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@380 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix stupid buffer leakage code in standard modehenryk2007-12-061-0/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@376 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a kludge to make repetitive sends working. For some obscure reason the ↵henryk2007-12-051-0/+4
| | | | | | | | | first transfer of subsequent transmissions (32 sample-bits, equalling 2 data-bits) gets lost. It does work if I just give the same TX buffer to the PDC twice (once after starting the TX PDC). git-svn-id: https://svn.openpcd.org:2342/trunk@374 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Revamp SSC buffer handling, should severely reduce buffer leakagehenryk2007-12-051-42/+25
| | | | | | | | Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* ATQA needs to be transmitted with parityhenryk2007-12-031-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@367 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix copy and paste error in prefill_bufferhenryk2007-12-031-1/+8
| | | | | | | (Add debug output in main loop) git-svn-id: https://svn.openpcd.org:2342/trunk@365 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix power-on logic for the case that the card is already in the fieldhenryk2007-11-301-26/+25
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@361 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Move to prefilling the transmit buffer for faster ATQA responsehenryk2007-11-291-32/+50
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@359 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Print relevant SSC registershenryk2007-11-271-0/+1
| | | | | | | Set correct tc_cdiv for sending (FIXME: need to reset before receiving) git-svn-id: https://svn.openpcd.org:2342/trunk@356 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Restructure irq handling for setting tc_fdt (works now) and to get most iso ↵henryk2007-11-261-6/+86
| | | | | | | | | specific stuff out of ssc_picc Add ssc tx code (doesn't work yet) git-svn-id: https://svn.openpcd.org:2342/trunk@355 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare transmission codehenryk2007-11-261-3/+52
| | | | | | | | Restructure/add some buffer code Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add load modulation and encoding/decoding code from haraldhenryk2007-11-241-3/+12
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@351 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo (pending cleanup of the debug and experimental code that I ↵henryk2007-11-231-0/+4
| | | | | | | | | | | added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Refactor frame print code out and use in iso14443_layer3ahenryk2007-11-221-3/+11
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@345 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-211-0/+143
Currently working on fiq for pio data change to reset tc0 via swtrg git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary