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* Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which
stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would
have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct.
* Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly
git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Restructure/add some buffer code
Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread
git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@350 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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added during the last week)
Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working
Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to
a possible data edge and therefore not reliable
git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Currently working on fiq for pio data change to reset tc0 via swtrg
git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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