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* Prepare generic ISO 14443A reception mode (no short/standard distinction), ↵henryk2007-12-151-0/+7
| | | | | | prerequisite for proper frame handling and anticol, doesn't work yet git-svn-id: https://svn.openpcd.org:2342/trunk@390 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add new miller decoder (not working yet)henryk2007-12-121-15/+15
| | | | | | | Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Some more delayhenryk2007-12-111-3/+5
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@384 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Several modifications to enable spinning until the correct phase is reached ↵henryk2007-12-111-6/+7
| | | | | | | | | in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv) Still too much jitter (some bug in this code?) git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Change parity storage in frame structhenryk2007-12-091-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@379 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Count and print late frameshenryk2007-12-091-2/+8
| | | | | | | | Make load modulation level changeable on the fly Better fdt calculation and ajustable fdt offset git-svn-id: https://svn.openpcd.org:2342/trunk@378 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* * Reduce leaking of TX buffershenryk2007-12-031-2/+4
| | | | | | | | | | * Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct. * Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare transmission codehenryk2007-11-261-1/+52
| | | | | | | | Restructure/add some buffer code Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* hex and dec ...henryk2007-11-231-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@350 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo (pending cleanup of the debug and experimental code that I ↵henryk2007-11-231-0/+27
| | | | | | | | | | | added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-211-0/+18
Currently working on fiq for pio data change to reset tc0 via swtrg git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary