| Commit message (Collapse) | Author | Age | Files | Lines |
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Move clock switch to its own header file
Specify default (and for non-clock switching capable hardware: single) clock source in hardware definitions
git-svn-id: https://svn.openpcd.org:2342/trunk@443 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Better layering separation
git-svn-id: https://svn.openpcd.org:2342/trunk@434 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@396 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Change miller decoder to take an RX DMA buffer in order to have access to the reception_mode member, much more versatile
git-svn-id: https://svn.openpcd.org:2342/trunk@393 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Add convenient access to the last data bit from the miller decoder for type a frames
git-svn-id: https://svn.openpcd.org:2342/trunk@391 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Fix miller decoder for the case of a buffer containing only zeroes
git-svn-id: https://svn.openpcd.org:2342/trunk@388 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Fix miller decoder
git-svn-id: https://svn.openpcd.org:2342/trunk@387 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction
git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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