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* Make it possible to send long frames for debugginghenryk2007-12-091-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@380 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Count and print late frameshenryk2007-12-091-0/+8
| | | | | | | | Make load modulation level changeable on the fly Better fdt calculation and ajustable fdt offset git-svn-id: https://svn.openpcd.org:2342/trunk@378 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix stupid buffer leakage code in standard modehenryk2007-12-061-3/+4
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@376 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Obsolete commenthenryk2007-12-051-2/+0
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@375 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a kludge to make repetitive sends working. For some obscure reason the ↵henryk2007-12-051-0/+2
| | | | | | | | | first transfer of subsequent transmissions (32 sample-bits, equalling 2 data-bits) gets lost. It does work if I just give the same TX buffer to the PDC twice (once after starting the TX PDC). git-svn-id: https://svn.openpcd.org:2342/trunk@374 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Revamp SSC buffer handling, should severely reduce buffer leakagehenryk2007-12-051-109/+144
| | | | | | | | Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* remove old debugging #ifdef'shenryk2007-12-051-13/+4
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@372 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* * Reduce leaking of TX buffershenryk2007-12-031-1/+11
| | | | | | | | | | * Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct. * Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix SSC TX registers (especially the clock source selection), peripheral ↵henryk2007-11-291-6/+39
| | | | | | | | | configuration in ssc_tx_init Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Print relevant SSC registershenryk2007-11-271-2/+2
| | | | | | | Set correct tc_cdiv for sending (FIXME: need to reset before receiving) git-svn-id: https://svn.openpcd.org:2342/trunk@356 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Restructure irq handling for setting tc_fdt (works now) and to get most iso ↵henryk2007-11-261-66/+36
| | | | | | | | | specific stuff out of ssc_picc Add ssc tx code (doesn't work yet) git-svn-id: https://svn.openpcd.org:2342/trunk@355 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Remove unusedhenryk2007-11-261-67/+0
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@353 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare transmission codehenryk2007-11-261-49/+46
| | | | | | | | Restructure/add some buffer code Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a work around to have each pio data change fiq followed by a regular IRQ ↵henryk2007-11-231-3/+0
| | | | | | in order to enable some code to be run synchronized with critical sections git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo (pending cleanup of the debug and experimental code that I ↵henryk2007-11-231-13/+10
| | | | | | | | | | | added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Remove obsolete codehenryk2007-11-221-28/+6
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@346 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-211-0/+1
| | | | | | | Currently working on fiq for pio data change to reset tc0 via swtrg git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Checking in status quo: Can currently receive and print frames in ssc ↵henryk2007-11-211-124/+191
| | | | | | | | | continuous mode (with new short and incomplete ssc irq handler: FIXME, either switch back to original handler (maybe fixing it if necessary) or handle the missing cases in the new handler). Lots of debug statements still in there git-svn-id: https://svn.openpcd.org:2342/trunk@335 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Move some definitions to header filehenryk2007-11-191-9/+0
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@333 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Rewrite irq handlers according to the new information in ↵henryk2007-11-141-3/+8
| | | | | | | | | http://www.freertos.org/portsam7xlwIP.html: /* Call the handler function. This must be a separate function unless you can guarantee that handling the interrupt will never use any stack space. */ git-svn-id: https://svn.openpcd.org:2342/trunk@327 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Slight progress, still: enabling tc_fdt crashes the processor after some bitshenryk2007-11-131-0/+3
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@326 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add code modules for tc_fdt, tc_cdiv_sync, tc_cdiv, ssc_picchenryk2007-11-111-0/+589
Almost all of these have not been checked yet, I just copied them over and hot-fixed compile time errors F.e. all ssc usb code has been removed git-svn-id: https://svn.openpcd.org:2342/trunk@323 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary