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* Change tc_cdiv_set_divider. The new code seems to work nearly perfect ↵henryk2007-12-041-2/+5
| | | | | | (jitter is now near 1 sample for the fdt of 1172) git-svn-id: https://svn.openpcd.org:2342/trunk@371 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* * Reduce leaking of TX buffershenryk2007-12-031-0/+4
| | | | | | | | | | * Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct. * Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Get tc_cdiv working (presumably, need to check on the oscilloscope)henryk2007-11-131-8/+8
| | | | | | | Add adc code to read the field strength git-svn-id: https://svn.openpcd.org:2342/trunk@325 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add code modules for tc_fdt, tc_cdiv_sync, tc_cdiv, ssc_picchenryk2007-11-111-0/+107
Almost all of these have not been checked yet, I just copied them over and hot-fixed compile time errors F.e. all ssc usb code has been removed git-svn-id: https://svn.openpcd.org:2342/trunk@323 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary