| Commit message (Collapse) | Author | Age | Files | Lines |
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git-svn-id: https://svn.openpcd.org:2342/trunk@384 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv)
Still too much jitter (some bug in this code?)
git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@382 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Fix tc_cdiv_set_divider. again.
Reverse the polarity! (of the ssc transmit clock)
git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@380 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@379 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Make load modulation level changeable on the fly
Better fdt calculation and ajustable fdt offset
git-svn-id: https://svn.openpcd.org:2342/trunk@378 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@377 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@376 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@375 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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first transfer of subsequent transmissions (32 sample-bits, equalling 2 data-bits) gets lost. It does work if I just give
the same TX buffer to the PDC twice (once after starting the TX PDC).
git-svn-id: https://svn.openpcd.org:2342/trunk@374 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise
Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug
git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@372 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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(jitter is now near 1 sample for the fdt of 1172)
git-svn-id: https://svn.openpcd.org:2342/trunk@371 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@367 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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* Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which
stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would
have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct.
* Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly
git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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(Add debug output in main loop)
git-svn-id: https://svn.openpcd.org:2342/trunk@365 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@361 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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configuration in ssc_tx_init
Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition
git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@359 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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(milosch's idea)
git-svn-id: https://svn.openpcd.org:2342/trunk@358 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@357 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Set correct tc_cdiv for sending (FIXME: need to reset before receiving)
git-svn-id: https://svn.openpcd.org:2342/trunk@356 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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specific stuff out of ssc_picc
Add ssc tx code (doesn't work yet)
git-svn-id: https://svn.openpcd.org:2342/trunk@355 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@353 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Restructure/add some buffer code
Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread
git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@351 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@350 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@349 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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in order to enable some code to be run synchronized with critical sections
git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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added during the last week)
Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working
Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to
a possible data edge and therefore not reliable
git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@346 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@345 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@344 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Currently working on fiq for pio data change to reset tc0 via swtrg
git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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continuous mode (with new short and incomplete ssc irq handler: FIXME, either switch back to original handler (maybe fixing it
if necessary) or handle the missing cases in the new handler). Lots of debug statements still in there
git-svn-id: https://svn.openpcd.org:2342/trunk@335 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@334 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@333 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Print version and compile date on help and config commands
git-svn-id: https://svn.openpcd.org:2342/trunk@332 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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or similar situations
git-svn-id: https://svn.openpcd.org:2342/trunk@330 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@329 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@328 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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http://www.freertos.org/portsam7xlwIP.html: /* Call the handler function. This must be a separate function unless you can guarantee that
handling the interrupt will never use any stack space. */
git-svn-id: https://svn.openpcd.org:2342/trunk@327 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@326 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Add adc code to read the field strength
git-svn-id: https://svn.openpcd.org:2342/trunk@325 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Make tc_cdiv_sync interrupt working
Add 'p' command to print some PIO inputs
Add 'z' command to enable/disable tc_cdiv_sync
git-svn-id: https://svn.openpcd.org:2342/trunk@324 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Almost all of these have not been checked yet, I just copied them over and hot-fixed compile time errors
F.e. all ssc usb code has been removed
git-svn-id: https://svn.openpcd.org:2342/trunk@323 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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(and a dummy dbgu.h)
git-svn-id: https://svn.openpcd.org:2342/trunk@322 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Add commands to increase and decrease comparator threshold
git-svn-id: https://svn.openpcd.org:2342/trunk@320 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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type commands
git-svn-id: https://svn.openpcd.org:2342/trunk@317 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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