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* Factor out time print code and enhance ithenryk2008-02-032-12/+29
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@404 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Change order on these two because otherwise unloading while IRQs are still ↵henryk2008-02-031-1/+1
| | | | | | enabled will lead to an IRQ storm git-svn-id: https://svn.openpcd.org:2342/trunk@403 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo. Partly or severely broken.henryk2008-02-025-14/+35
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@402 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Use finer grained #ifdef's for the new board's featureshenryk2007-12-213-5/+11
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@400 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add SSC_DATA_GATE supporthenryk2007-12-203-0/+33
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@399 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* New hardware versionhenryk2007-12-193-8/+37
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@398 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Play with transfer sizeshenryk2007-12-193-10/+68
| | | | | | | | Enhance timing by removing debugging code Pending rewrite of SSC RX IRQ code git-svn-id: https://svn.openpcd.org:2342/trunk@397 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Optimizing (disabling debugging reduces time spent in decoder from 460us to 60ushenryk2007-12-171-20/+43
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@396 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* That comment is not true anymorehenryk2007-12-161-6/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@395 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Get SSC_MODE_14443A workinghenryk2007-12-163-9/+28
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@394 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Record size of SSC RX DMA buffers in transfers, much clearerhenryk2007-12-157-20/+89
| | | | | | | Change miller decoder to take an RX DMA buffer in order to have access to the reception_mode member, much more versatile git-svn-id: https://svn.openpcd.org:2342/trunk@393 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Standard state is still idlehenryk2007-12-151-2/+2
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@392 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Further the distinction between SSC and PDC transfersizehenryk2007-12-155-18/+24
| | | | | | | Add convenient access to the last data bit from the miller decoder for type a frames git-svn-id: https://svn.openpcd.org:2342/trunk@391 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare generic ISO 14443A reception mode (no short/standard distinction), ↵henryk2007-12-154-25/+51
| | | | | | prerequisite for proper frame handling and anticol, doesn't work yet git-svn-id: https://svn.openpcd.org:2342/trunk@390 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix consistency checkhenryk2007-12-153-19/+21
| | | | | | | Fix miller decoder for the case of a buffer containing only zeroes git-svn-id: https://svn.openpcd.org:2342/trunk@388 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Sanitize and clarify the len handling in rx buffers.henryk2007-12-145-28/+44
| | | | | | | Fix miller decoder git-svn-id: https://svn.openpcd.org:2342/trunk@387 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add complicated mechanism that should have brought clock cycle accurate ↵henryk2007-12-121-0/+1
| | | | | | measurement. Doesn't seem to work properly git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add new miller decoder (not working yet)henryk2007-12-127-34/+156
| | | | | | | Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Some more delayhenryk2007-12-111-3/+5
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@384 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Several modifications to enable spinning until the correct phase is reached ↵henryk2007-12-115-18/+53
| | | | | | | | | in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv) Still too much jitter (some bug in this code?) git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Clean up SSC performance metric reportinghenryk2007-12-094-21/+47
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@382 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prevent late frames by spinning in SSC CP0 IRQ till end of short frame receptionhenryk2007-12-094-8/+34
| | | | | | | | Fix tc_cdiv_set_divider. again. Reverse the polarity! (of the ssc transmit clock) git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Make it possible to send long frames for debugginghenryk2007-12-094-36/+82
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@380 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Change parity storage in frame structhenryk2007-12-092-3/+4
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@379 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Count and print late frameshenryk2007-12-094-3/+57
| | | | | | | | Make load modulation level changeable on the fly Better fdt calculation and ajustable fdt offset git-svn-id: https://svn.openpcd.org:2342/trunk@378 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* inlined miller bit decode functionmeri2007-12-061-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@377 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix stupid buffer leakage code in standard modehenryk2007-12-062-3/+5
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@376 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Obsolete commenthenryk2007-12-051-2/+0
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@375 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a kludge to make repetitive sends working. For some obscure reason the ↵henryk2007-12-052-0/+6
| | | | | | | | | first transfer of subsequent transmissions (32 sample-bits, equalling 2 data-bits) gets lost. It does work if I just give the same TX buffer to the PDC twice (once after starting the TX PDC). git-svn-id: https://svn.openpcd.org:2342/trunk@374 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Revamp SSC buffer handling, should severely reduce buffer leakagehenryk2007-12-055-154/+175
| | | | | | | | Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* remove old debugging #ifdef'shenryk2007-12-053-26/+10
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@372 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Change tc_cdiv_set_divider. The new code seems to work nearly perfect ↵henryk2007-12-041-2/+5
| | | | | | (jitter is now near 1 sample for the fdt of 1172) git-svn-id: https://svn.openpcd.org:2342/trunk@371 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* ATQA needs to be transmitted with parityhenryk2007-12-031-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@367 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* * Reduce leaking of TX buffershenryk2007-12-033-3/+19
| | | | | | | | | | * Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct. * Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix copy and paste error in prefill_bufferhenryk2007-12-031-1/+8
| | | | | | | (Add debug output in main loop) git-svn-id: https://svn.openpcd.org:2342/trunk@365 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix power-on logic for the case that the card is already in the fieldhenryk2007-11-301-26/+25
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@361 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix SSC TX registers (especially the clock source selection), peripheral ↵henryk2007-11-292-7/+40
| | | | | | | | | configuration in ssc_tx_init Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Move to prefilling the transmit buffer for faster ATQA responsehenryk2007-11-292-33/+53
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@359 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Switch to hardcoded fiq handler implementation directly in the vector table ↵henryk2007-11-291-26/+5
| | | | | | (milosch's idea) git-svn-id: https://svn.openpcd.org:2342/trunk@358 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Forgotten filehenryk2007-11-271-0/+5
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@357 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Print relevant SSC registershenryk2007-11-273-2/+18
| | | | | | | Set correct tc_cdiv for sending (FIXME: need to reset before receiving) git-svn-id: https://svn.openpcd.org:2342/trunk@356 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Restructure irq handling for setting tc_fdt (works now) and to get most iso ↵henryk2007-11-264-72/+140
| | | | | | | | | specific stuff out of ssc_picc Add ssc tx code (doesn't work yet) git-svn-id: https://svn.openpcd.org:2342/trunk@355 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Remove unusedhenryk2007-11-261-67/+0
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@353 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare transmission codehenryk2007-11-268-111/+264
| | | | | | | | Restructure/add some buffer code Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add load modulation and encoding/decoding code from haraldhenryk2007-11-249-3/+558
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@351 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* hex and dec ...henryk2007-11-231-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@350 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add scale values to the field meterhenryk2007-11-231-2/+5
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@349 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a work around to have each pio data change fiq followed by a regular IRQ ↵henryk2007-11-233-8/+54
| | | | | | in order to enable some code to be run synchronized with critical sections git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo (pending cleanup of the debug and experimental code that I ↵henryk2007-11-237-16/+61
| | | | | | | | | | | added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Remove obsolete codehenryk2007-11-221-28/+6
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@346 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary