openpcd - Firmware for the OpenPCD, OpenPICC and SIMtrace hardware

	Commit message (Collapse)	Author	Age	Files	Lines
*	Add new miller decoder (not working yet)	henryk	2007-12-12	1	-1/+30
\| \| \| \| \| \| \|	Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Several modifications to enable spinning until the correct phase is reached ↵	henryk	2007-12-11	1	-10/+33
\| \| \| \| \| \| \| \| \|	in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv) Still too much jitter (some bug in this code?) git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Prevent late frames by spinning in SSC CP0 IRQ till end of short frame reception	henryk	2007-12-09	1	-1/+9
\| \| \| \| \| \| \| \|	Fix tc_cdiv_set_divider. again. Reverse the polarity! (of the ssc transmit clock) git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Fix FIQ code for SSC TF emulation	henryk	2007-12-03	1	-8/+7
\| \| \| \|	git-svn-id: https://svn.openpcd.org:2342/trunk@364 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Fix SSC TX registers (especially the clock source selection), peripheral ↵	henryk	2007-11-29	1	-0/+24
\| \| \| \| \| \| \| \| \|	configuration in ssc_tx_init Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Switch to hardcoded fiq handler implementation directly in the vector table ↵	henryk	2007-11-29	1	-79/+14
\| \| \| \| \| \|	(milosch's idea) git-svn-id: https://svn.openpcd.org:2342/trunk@358 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Add a work around to have each pio data change fiq followed by a regular IRQ ↵	henryk	2007-11-23	1	-10/+15
\| \| \| \| \| \|	in order to enable some code to be run synchronized with critical sections git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Commit status quo (pending cleanup of the debug and experimental code that I ↵	henryk	2007-11-23	1	-15/+63
\| \| \| \| \| \| \| \| \| \| \|	added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Add tragically failed (and commented out) attempt to remap ram to addr 0	henryk	2007-11-21	1	-0/+16
\| \| \| \|	git-svn-id: https://svn.openpcd.org:2342/trunk@341 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Commit status quo: Start adding iso 14443 layer 3a code	henryk	2007-11-21	1	-2/+91
\| \| \| \| \| \| \|	Currently working on fiq for pio data change to reset tc0 via swtrg git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
*	Initial import of FreeRTOS code for OpenPICC	henryk	2007-11-06	1	-0/+161
	git-svn-id: https://svn.openpcd.org:2342/trunk@311 6dc7ffe9-61d6-0310-9af1-9938baff3ed1