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* Copy over the relevant changes from the sniffonly branch pending integrationhenryk2008-03-051-108/+42
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@442 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo. Partly or severely broken.henryk2008-02-021-0/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@402 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* New hardware versionhenryk2007-12-191-1/+1
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@398 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Implement unrolled loop, have not yet measured performancehenryk2007-12-151-59/+42
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@389 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add complicated mechanism that should have brought clock cycle accurate ↵henryk2007-12-121-3/+37
| | | | | | measurement. Doesn't seem to work properly git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add new miller decoder (not working yet)henryk2007-12-121-1/+30
| | | | | | | Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Several modifications to enable spinning until the correct phase is reached ↵henryk2007-12-112-12/+35
| | | | | | | | | in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv) Still too much jitter (some bug in this code?) git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prevent late frames by spinning in SSC CP0 IRQ till end of short frame receptionhenryk2007-12-091-1/+9
| | | | | | | | Fix tc_cdiv_set_divider. again. Reverse the polarity! (of the ssc transmit clock) git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix FIQ code for SSC TF emulationhenryk2007-12-031-8/+7
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@364 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Fix SSC TX registers (especially the clock source selection), peripheral ↵henryk2007-11-291-0/+24
| | | | | | | | | configuration in ssc_tx_init Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Switch to hardcoded fiq handler implementation directly in the vector table ↵henryk2007-11-291-79/+14
| | | | | | (milosch's idea) git-svn-id: https://svn.openpcd.org:2342/trunk@358 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Prepare transmission codehenryk2007-11-261-1/+1
| | | | | | | | Restructure/add some buffer code Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add a work around to have each pio data change fiq followed by a regular IRQ ↵henryk2007-11-231-10/+15
| | | | | | in order to enable some code to be run synchronized with critical sections git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo (pending cleanup of the debug and experimental code that I ↵henryk2007-11-232-18/+67
| | | | | | | | | | | added during the last week) Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to a possible data edge and therefore not reliable git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Add tragically failed (and commented out) attempt to remap ram to addr 0henryk2007-11-211-0/+16
| | | | git-svn-id: https://svn.openpcd.org:2342/trunk@341 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-212-2/+97
| | | | | | | Currently working on fiq for pio data change to reset tc0 via swtrg git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Checking in status quo: Can currently receive and print frames in ssc ↵henryk2007-11-211-1/+2
| | | | | | | | | continuous mode (with new short and incomplete ssc irq handler: FIXME, either switch back to original handler (maybe fixing it if necessary) or handle the missing cases in the new handler). Lots of debug statements still in there git-svn-id: https://svn.openpcd.org:2342/trunk@335 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Revert 313 and 315 again, I'm too stupid to get DFU working, focus on the ↵henryk2007-11-113-706/+39
| | | | | | application code first git-svn-id: https://svn.openpcd.org:2342/trunk@316 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Start working at dfu by copying from main openpcd repository (with ↵henryk2007-11-073-39/+706
| | | | | | modifications), doesn't boot application yet git-svn-id: https://svn.openpcd.org:2342/trunk@315 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
* Initial import of FreeRTOS code for OpenPICChenryk2007-11-062-0/+228
git-svn-id: https://svn.openpcd.org:2342/trunk@311 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
personal git repositories of Harald Welte. Your mileage may vary