| Commit message (Collapse) | Author | Age | Files | Lines |
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Better layering separation
git-svn-id: https://svn.openpcd.org:2342/trunk@434 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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efficiently sent.
Should affect existing byte base code only marginally.
(Note: Not compliant with FreeRTOS' braindead coding style)
git-svn-id: https://svn.openpcd.org:2342/trunk@416 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@402 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@398 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@389 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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measurement. Doesn't seem to work properly
git-svn-id: https://svn.openpcd.org:2342/trunk@386 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction
git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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in tc_fdt (thereby taking the phase information from tc_fdt, resetting the phase in tc_cdiv)
Still too much jitter (some bug in this code?)
git-svn-id: https://svn.openpcd.org:2342/trunk@383 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Fix tc_cdiv_set_divider. again.
Reverse the polarity! (of the ssc transmit clock)
git-svn-id: https://svn.openpcd.org:2342/trunk@381 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@370 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@364 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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configuration in ssc_tx_init
Implement software (FIQ based) workaround for the problem that TF seemingly cannot be used as a start condition
git-svn-id: https://svn.openpcd.org:2342/trunk@360 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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(milosch's idea)
git-svn-id: https://svn.openpcd.org:2342/trunk@358 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Restructure/add some buffer code
Reset the watchdog timer (now at 1.5s), add a watchdog pinger thread
git-svn-id: https://svn.openpcd.org:2342/trunk@352 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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in order to enable some code to be run synchronized with critical sections
git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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added during the last week)
Change freertos code to not mask FIQ, this finally makes the FIQ working (with approx 700ns +/- 100ns latency; yeah!) and therefore reception starts working
Change to two times oversampling (keep four times oversampling code ifdef'd, extract all the magical values to a header file) because at four times oversampling every other sample is very close to
a possible data edge and therefore not reliable
git-svn-id: https://svn.openpcd.org:2342/trunk@347 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@341 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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Currently working on fiq for pio data change to reset tc0 via swtrg
git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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continuous mode (with new short and incomplete ssc irq handler: FIXME, either switch back to original handler (maybe fixing it
if necessary) or handle the missing cases in the new handler). Lots of debug statements still in there
git-svn-id: https://svn.openpcd.org:2342/trunk@335 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@318 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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application code first
git-svn-id: https://svn.openpcd.org:2342/trunk@316 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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modifications), doesn't boot application yet
git-svn-id: https://svn.openpcd.org:2342/trunk@315 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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git-svn-id: https://svn.openpcd.org:2342/trunk@311 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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