From 880465ce17b0ae3eda6efb1ae50352808213ab4e Mon Sep 17 00:00:00 2001
From: "(no author)" <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>
Date: Sun, 23 Jul 2006 14:34:36 +0000
Subject: - increase to 320kHz SPI clock rate - enable SPI overflow interrupts

git-svn-id: https://svn.openpcd.org:2342/trunk@21 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
---
 openpcd/firmware/src/rc632.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/openpcd/firmware/src/rc632.c b/openpcd/firmware/src/rc632.c
index 1f94dd0..e60e051 100644
--- a/openpcd/firmware/src/rc632.c
+++ b/openpcd/firmware/src/rc632.c
@@ -222,12 +222,12 @@ void rc632_init(void)
 	AT91F_AIC_ConfigureIt(AT91C_BASE_AIC, AT91C_ID_SPI, AT91C_AIC_PRIOR_HIGHEST,
 			      AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, &spi_irq);
 	AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SPI);
-	AT91F_SPI_EnableIt(pSPI, AT91C_SPI_MODF|AT91C_SPI_OVRES|AT91C_SPI_RDRF|AT91C_SPI_TDRE);
+	AT91F_SPI_EnableIt(pSPI, AT91C_SPI_MODF|AT91C_SPI_OVRES);
 	AT91F_SPI_CfgMode(pSPI, AT91C_SPI_MSTR|AT91C_SPI_PS_FIXED);
 	/* CPOL = 0, NCPHA = 1, CSAAT = 0, BITS = 0000, SCBR = 10 (4.8MHz), 
 	 * DLYBS = 0, DLYBCT = 0 */
 	//AT91F_SPI_CfgCs(pSPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(10<<8));
-	AT91F_SPI_CfgCs(pSPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(0xff<<8));
+	AT91F_SPI_CfgCs(pSPI, 0, AT91C_SPI_BITS_8|AT91C_SPI_NCPHA|(0x7f<<8));
 
 	//AT91F_SPI_Reset(pSPI);
 
-- 
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