From 97c8df09837638708eb716a5f2544f32e8ba8409 Mon Sep 17 00:00:00 2001 From: "(no author)" <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> Date: Sat, 9 Sep 2006 15:36:25 +0000 Subject: remove old comment git-svn-id: https://svn.openpcd.org:2342/trunk@155 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 --- openpcd/firmware/src/os/tc_cdiv.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/openpcd/firmware/src/os/tc_cdiv.c b/openpcd/firmware/src/os/tc_cdiv.c index b15f7b1..6c4024c 100644 --- a/openpcd/firmware/src/os/tc_cdiv.c +++ b/openpcd/firmware/src/os/tc_cdiv.c @@ -5,15 +5,6 @@ * into TCLK1, which is routed to XC1. Then configure TC0 to divide this * clock by a configurable divider. * - * PICC Simulator Side: - * In order to support responding to synchronous frames (REQA/WUPA/ANTICOL), - * we need a second Timer/Counter (TC1). This unit is reset by an external - * event (rising edge of modulation pause PCD->PICC) connected to TIOB2, and - * counts up to a configurable number of carrier clock cycles (RA). Once the - * RA value is reached, TIOA2 will see a rising edge. This rising edge will - * be interconnected to TF (Tx Frame) of the SSC to start transmitting our - * synchronous response. - * */ #include -- cgit v1.2.3