From de1d73984f09ecf2aa53636b1adebd3a459bbad9 Mon Sep 17 00:00:00 2001
From: "(no author)" <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>
Date: Sat, 9 Sep 2006 11:21:10 +0000
Subject: rename tc files

git-svn-id: https://svn.openpcd.org:2342/trunk@152 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
---
 openpcd/firmware/src/picc/tc_fdt.c | 51 ++++++++++++++++++++++++++++++++++++++
 openpcd/firmware/src/picc/tc_fdt.h |  9 +++++++
 2 files changed, 60 insertions(+)
 create mode 100644 openpcd/firmware/src/picc/tc_fdt.c
 create mode 100644 openpcd/firmware/src/picc/tc_fdt.h

diff --git a/openpcd/firmware/src/picc/tc_fdt.c b/openpcd/firmware/src/picc/tc_fdt.c
new file mode 100644
index 0000000..cc7729a
--- /dev/null
+++ b/openpcd/firmware/src/picc/tc_fdt.c
@@ -0,0 +1,51 @@
+/* OpenPC TC (Timer / Clock) support code
+ * (C) 2006 by Harald Welte <hwelte@hmw-consulting.de>
+ *
+ * This idea of this code is to feed the 13.56MHz carrier clock of RC632
+ * into TCLK1, which is routed to XC1.  Then configure TC0 to divide this
+ * clock by a configurable divider.
+ *
+ * PICC Simulator Side:
+ * In order to support responding to synchronous frames (REQA/WUPA/ANTICOL),
+ * we need a second Timer/Counter (TC1).  This unit is reset by an external
+ * event (rising edge of modulation pause PCD->PICC) connected to TIOB2, and
+ * counts up to a configurable number of carrier clock cycles (RA). Once the
+ * RA value is reached, TIOA2 will see a rising edge.  This rising edge will
+ * be interconnected to TF (Tx Frame) of the SSC to start transmitting our
+ * synchronous response.
+ *
+ */
+
+#include <lib_AT91SAM7.h>
+#include <AT91SAM7.h>
+#include <os/dbgu.h>
+
+#include "../openpcd.h"
+#include <os/tc_cdiv.h>
+#include <picc/tc_fdt.h>
+
+void tc_fdt_set(u_int16_t count)
+{
+	tcb->TCB_TC2.TC_RA = count;
+}
+
+void tc_fdt_init(void)
+{
+	AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, AT91C_PA15_TF,
+			    AT91C_PA26_TIOA2 | AT91C_PA27_TIOB2);
+	AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC,
+				    ((unsigned int) 1 << AT91C_ID_TC2));
+	/* Clock XC1, Wave Mode, No automatic reset on RC comp
+	 * TIOA2 in RA comp = set, TIOA2 on RC comp = clear,
+	 * TIOB2 as input, EEVT = TIOB2, Reset/Trigger on EEVT */
+	tcb->TCB_TC2.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE |
+			      AT91C_TC_WAVESEL_UP |
+			      AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR |
+			      AT91C_TC_BEEVT_NONE | AT91C_TC_BCPB_NONE |
+			      AT91C_TC_EEVT_TIOB | AT91C_TC_ETRGEDG_RISING |
+			      AT91C_TC_ENETRG ;
+
+	/* Reset to start timers */
+	tcb->TCB_BCR = 1;
+}
+
diff --git a/openpcd/firmware/src/picc/tc_fdt.h b/openpcd/firmware/src/picc/tc_fdt.h
new file mode 100644
index 0000000..b39b935
--- /dev/null
+++ b/openpcd/firmware/src/picc/tc_fdt.h
@@ -0,0 +1,9 @@
+#ifndef _TC_FDT_H
+#define _TC_FDT_H
+
+#include <sys/types.h>
+
+extern void tc_fdt_init(void);
+extern void tc_fdt_set(u_int16_t count);
+
+#endif
-- 
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