From 98f3bcf710fccafb0cc8a4abc43cfc92636ddb07 Mon Sep 17 00:00:00 2001
From: meri <meri@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>
Date: Tue, 10 Apr 2007 17:46:11 +0000
Subject: added watchdog time support and debouncing on power-cycle

git-svn-id: https://svn.openpcd.org:2342/trunk@297 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
---
 firmware/src/start/Cstartup_SAM7.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'firmware/src/start')

diff --git a/firmware/src/start/Cstartup_SAM7.c b/firmware/src/start/Cstartup_SAM7.c
index 66dbe20..4ab263f 100644
--- a/firmware/src/start/Cstartup_SAM7.c
+++ b/firmware/src/start/Cstartup_SAM7.c
@@ -32,16 +32,17 @@ extern void AT91F_Default_FIQ_handler (void);
 void
 AT91F_LowLevelInit (void)
 {
-  int i;
+  volatile int i;
+  
+  //* Debounce power supply
+  for(i=0;i<1024;i++);
+  
   AT91PS_PMC pPMC = AT91C_BASE_PMC;
   //* Set Flash Waite sate
   //  Single Cycle Access at Up to 30 MHz, or 40
   //  if MCK = 47923200 I have 50 Cycle for 1 usecond ( flied MC_FMR->FMCN
   AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN) & (48 << 16)) | AT91C_MC_FWS_1FWS;
 
-  //* Watchdog Disable
-  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
-
   //* Set MCK at 47 923 200
   // 1 Enabling the Main Oscillator:
   // SCK = 1/32768 = 30.51 uSecond
-- 
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