From 56fa0102a8be4ab63e23b88675fa38ef6d5d554c Mon Sep 17 00:00:00 2001
From: "(no author)" <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>
Date: Sun, 23 Jul 2006 13:01:34 +0000
Subject: add pll calculation helper

git-svn-id: https://svn.openpcd.org:2342/trunk@17 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
---
 openpcd/pll.txt | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 openpcd/pll.txt

(limited to 'openpcd/pll.txt')

diff --git a/openpcd/pll.txt b/openpcd/pll.txt
new file mode 100644
index 0000000..d086630
--- /dev/null
+++ b/openpcd/pll.txt
@@ -0,0 +1,7 @@
+MAINCLK = 18.432MHz
+PLLCLK(div=24,mul=125) = 96MHz
+MCLK(divisor 2) = 48MHz
+USB(divisor 2) = 48MHz
+MC_FWR(FWS) = 2 		# 1 flash waitstate
+
+SPCK(SCBR=10) = 4.8MHz		# 5MHz max clock RC632
-- 
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