From ba63352b4b915e46bc44fbd98c6e0e837477005d Mon Sep 17 00:00:00 2001 From: henryk Date: Wed, 5 Dec 2007 15:36:56 +0000 Subject: Revamp SSC buffer handling, should severely reduce buffer leakage Switch SSC IRQ handling from edge triggered to level triggered. Somehow I was losing the ENDTX interrupt otherwise Modified ISO14443 code for testing to enable repeated REQA->ATQA cycles. Somehow only the first ATQA is correct, subsequent ATQAs are missing the first two bits. Need to debug git-svn-id: https://svn.openpcd.org:2342/trunk@373 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 --- openpicc/application/led.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'openpicc/application/led.c') diff --git a/openpicc/application/led.c b/openpicc/application/led.c index 9b6861a..cab12b1 100644 --- a/openpicc/application/led.c +++ b/openpicc/application/led.c @@ -29,7 +29,7 @@ #include "led.h" /**********************************************************************/ -#define BLINK_TIME 10 +#define BLINK_TIME 5 void vLedSetRed(bool_t on) { -- cgit v1.2.3