From aa804cf4ef8ed3236ae0065952d1faef735b3824 Mon Sep 17 00:00:00 2001 From: henryk Date: Fri, 23 Nov 2007 17:32:14 +0000 Subject: Add a work around to have each pio data change fiq followed by a regular IRQ in order to enable some code to be run synchronized with critical sections git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1 --- openpicc/application/ssc_picc.c | 3 --- 1 file changed, 3 deletions(-) (limited to 'openpicc/application/ssc_picc.c') diff --git a/openpicc/application/ssc_picc.c b/openpicc/application/ssc_picc.c index acdf9ae..e9fdbfb 100644 --- a/openpicc/application/ssc_picc.c +++ b/openpicc/application/ssc_picc.c @@ -102,9 +102,6 @@ static const u_int16_t ssc_dmasize[] = { AT91C_SSC_TXBUFE | \ AT91C_SSC_TXSYN) -/* This stores the value that SSC_RCMR should be set to when a frame start is detected. - * Will be used in my_fiq_handler in os/boot/boot.s */ -u_int32_t ssc_rcmr_on_start = 0; void ssc_rx_mode_set(enum ssc_mode ssc_mode) { u_int8_t data_len=0, num_data=0, sync_len=0; -- cgit v1.2.3