From 616746c2e01a0425a9fc62d24153d88079f0daac Mon Sep 17 00:00:00 2001
From: henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>
Date: Wed, 21 Nov 2007 04:45:15 +0000
Subject: Commit status quo: Start adding iso 14443 layer 3a code Currently
working on fiq for pio data change to reset tc0 via swtrg
git-svn-id: https://svn.openpcd.org:2342/trunk@336 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
---
openpicc/os/boot/Cstartup_SAM7.c | 6 +++
openpicc/os/boot/boot.s | 93 +++++++++++++++++++++++++++++++++++++++-
2 files changed, 97 insertions(+), 2 deletions(-)
(limited to 'openpicc/os')
diff --git a/openpicc/os/boot/Cstartup_SAM7.c b/openpicc/os/boot/Cstartup_SAM7.c
index 72c9917..fdcafd3 100644
--- a/openpicc/os/boot/Cstartup_SAM7.c
+++ b/openpicc/os/boot/Cstartup_SAM7.c
@@ -26,6 +26,7 @@
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit (void)
{
+ char i=0;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set flash wait state
@@ -65,4 +66,9 @@ void AT91F_LowLevelInit (void)
pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK;
while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+ /* Copy IRQ vector table to RAM */
+ for(i=0; i<0x24; i++) *((char*)(0x00200000)+i) = *((char*)(0x00100000)+i);
+ /* Perform remap FIXME doesn't work*/
+ // AT91C_BASE_MC->MC_RCR = AT91C_MC_RCB;
}
diff --git a/openpicc/os/boot/boot.s b/openpicc/os/boot/boot.s
index 6bd5db2..cbd9be7 100644
--- a/openpicc/os/boot/boot.s
+++ b/openpicc/os/boot/boot.s
@@ -23,7 +23,7 @@
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
- .set FIQ_STACK_SIZE, 0x00000004
+ .set FIQ_STACK_SIZE, 0x00000400
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
@@ -39,6 +39,20 @@
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
+.equ AT91C_BASE_AIC, (0xFFFFF000)
+.equ AT91C_BASE_PIOA, 0xFFFFF400
+.equ AT91C_BASE_TC0, 0xFFFA0000
+.equ AT91C_TC_SWTRG, (1 << 2)
+.equ PIO_DATA, (1 << 27)
+.equ PIOA_SODR, 0x30
+.equ PIOA_CODR, 0x34
+.equ PIOA_PDSR, 0x3c
+.equ PIOA_IDR, 0x44
+.equ PIOA_ISR, 0x4c
+.equ TC_CCR, 0x00
+.equ AIC_EOICR, (304)
+/*.equ PIO_LED1, (1 << 25)*/
+.equ PIO_LED1, (1 << 12)
start:
_start:
@@ -55,6 +69,11 @@ _mainCRTStartup:
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
+ /* Preload registers for FIQ handler */
+ ldr r10, =AT91C_BASE_PIOA
+ ldr r12, =AT91C_BASE_TC0
+ ldr r8, =AT91C_BASE_AIC
+ mov r9, #AT91C_TC_SWTRG
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
@@ -147,7 +166,7 @@ endless_loop:
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */
- ldr pc, _fiq /* FIQ - _fiq */
+ ldr pc, [pc,#-0xF20] /* FIQ - read the AIC */
_undf: .word __undf /* undefined */
_swi: .word swi_handler /* SWI */
@@ -159,3 +178,73 @@ __undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */
+
+/* Following is from openpcd/firmware/src/start/Cstartup_app.S */
+#define LED_TRIGGER
+/*#define CALL_PIO_IRQ_DEMUX*/
+
+ .text
+ .arm
+ .section .fastrun, "ax"
+
+ .global fiq_handler
+ .func fiq_handler
+fiq_handler:
+ /* code that uses pre-initialized FIQ reg */
+ /* r8 AT91C_BASE_AIC (dfu init)
+ r9 AT91C_TC_SWTRG
+ r10 AT91C_BASE_PIOA
+ r11 tmp
+ r12 AT91C_BASE_TC0
+ r13 stack
+ r14 lr
+ */
+
+ ldr r8, [r10, #PIOA_ISR]
+ tst r8, #PIO_DATA /* check for PIO_DATA change */
+ ldrne r11, [r10, #PIOA_PDSR]
+ tstne r11, #PIO_DATA /* check for PIO_DATA == 1 */
+ strne r9, [r12, #TC_CCR] /* software trigger */
+#ifdef LED_TRIGGER
+ movne r11, #PIO_LED1
+ strne r11, [r10, #PIOA_CODR] /* enable LED */
+#endif
+
+#if 1
+ movne r11, #PIO_DATA
+ strne r11, [r10, #PIOA_IDR] /* disable further PIO_DATA FIQ */
+#endif
+
+ /*- Mark the End of Interrupt on the AIC */
+ ldr r11, =AT91C_BASE_AIC
+ str r11, [r11, #AIC_EOICR]
+
+#ifdef LED_TRIGGER
+ mov r11, #PIO_LED1
+ str r11, [r10, #PIOA_SODR] /* disable LED */
+#endif
+
+#ifdef CALL_PIO_IRQ_DEMUX
+ /* push r0, r1-r3, r12, r14 onto FIQ stack */
+ /*stmfd sp!, { r0-r3, r12, lr}
+ mov r0, r8*/
+
+ /* enable interrupts while handling demux */
+ /* enable interrupts while handling demux */
+ /* msr CPSR_c, #F_BIT | ARM_MODE_SVC */
+
+ /* Call C function, give PIOA_ISR as argument */
+ /*ldr r11, =__pio_irq_demux
+ mov r14, pc
+ bx r11*/
+
+ /* msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ */
+ /*ldmia sp!, { r0-r3, r12, lr }*/
+#endif
+
+ /*- Restore the Program Counter using the LR_fiq directly in the PC */
+ subs pc, lr, #4
+
+ .size fiq_handler, . - fiq_handler
+ .endfunc
+ .end
--
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