diff options
| author | Harald Welte <laforge@gnumonks.org> | 2011-07-04 20:52:54 +0200 |
|---|---|---|
| committer | Harald Welte <laforge@gnumonks.org> | 2011-07-04 20:52:54 +0200 |
| commit | 044ad7c3987460ede48ff27afd6bdb0ca05a0432 (patch) | |
| tree | 924818cdb0d39ca08aec540d18da7bd406eaae8c /boards/at91sam9g10-ek | |
import at91lib from at91lib_20100901_softpack_1_9_v_1_0_svn_v1501120100901_softpack_1_9_v_1_0_svn_v15011
it's sad to see that atmel doesn't publish their svn repo or has
a centralized location or even puts proper version/release info
into the library itself
Diffstat (limited to 'boards/at91sam9g10-ek')
26 files changed, 6531 insertions, 0 deletions
diff --git a/boards/at91sam9g10-ek/at91sam9g10/AT91SAM9G10.h b/boards/at91sam9g10-ek/at91sam9g10/AT91SAM9G10.h new file mode 100644 index 0000000..e198892 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/AT91SAM9G10.h @@ -0,0 +1,3668 @@ +// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2008, Atmel Corporation
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91SAM9G10.h
+// Object : AT91SAM9G10 definitions
+// Generated : AT91 SW Application Group 06/25/2009 (10:52:48)
+//
+// CVS Reference : /AT91SAM9G10.pl/1.2/Fri Jun 12 07:21:23 2009//
+// CVS Reference : /SYS_SAM9261.pl/1.5/Thu Nov 18 13:22:33 2004//
+// CVS Reference : /HMATRIX1_SAM9261.pl/1.2/Mon Nov 8 16:38:17 2004//
+// CVS Reference : /PMC_SAM9261.pl/1.4/Fri Sep 9 15:24:01 2005//
+// CVS Reference : /HSMC3_SAM9261.pl/1.1/Tue Nov 16 09:16:07 2004//
+// CVS Reference : /SHDWC_SAM9261.pl/1.1/Tue Mar 8 14:46:52 2005//
+// CVS Reference : /UDP_6ept_puon.pl/1.1/Wed Jan 21 10:53:24 2009//
+// CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
+// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
+// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
+// CVS Reference : /RSTC_6098A.pl/1.4/Fri Oct 17 13:27:55 2008//
+// CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
+// CVS Reference : /TC_6082A.pl/1.8/Fri Oct 17 13:27:58 2008//
+// CVS Reference : /MCI_6101F.pl/1.3/Fri Jan 23 09:15:32 2009//
+// CVS Reference : /TWI_6061B.pl/1.3/Fri Oct 17 13:27:59 2008//
+// CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
+// CVS Reference : /SSC_6078B.pl/1.3/Fri Oct 17 13:27:57 2008//
+// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
+// CVS Reference : /UHP_6127A.pl/1.1/Wed Jan 21 10:53:45 2009//
+// CVS Reference : /LCDC_6063A.pl/1.6/Tue Jan 20 16:29:59 2009//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91SAM9G10_H
+#define AT91SAM9G10_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+#define AT91_CAST(a) (a)
+#else
+#define AT91_CAST(a)
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
+ AT91_REG Reserved0[118]; //
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
+ AT91_REG SMC_CTRL0; // Control Register for CS 0
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
+ AT91_REG SMC_CTRL1; // Control Register for CS 1
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
+ AT91_REG SMC_CTRL2; // Control Register for CS 2
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
+ AT91_REG SMC_CTRL3; // Control Register for CS 3
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
+ AT91_REG SMC_CTRL4; // Control Register for CS 4
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
+ AT91_REG SMC_CTRL5; // Control Register for CS 5
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
+ AT91_REG SMC_CTRL6; // Control Register for CS 6
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
+ AT91_REG SMC_CTRL7; // Control Register for CS 7
+ AT91_REG Reserved1[96]; //
+ AT91_REG MATRIX_MCFG; // Master Configuration Register
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
+ AT91_REG Reserved2[3]; //
+ AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register
+ AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG MATRIX_VERSION; // Version Register
+ AT91_REG Reserved5[110]; //
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved6[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved7[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved8[45]; //
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved9[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved10[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved11[54]; //
+ AT91_REG PIOA_PER; // PIO Enable Register
+ AT91_REG PIOA_PDR; // PIO Disable Register
+ AT91_REG PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved12[1]; //
+ AT91_REG PIOA_OER; // Output Enable Register
+ AT91_REG PIOA_ODR; // Output Disable Registerr
+ AT91_REG PIOA_OSR; // Output Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG PIOA_IFER; // Input Filter Enable Register
+ AT91_REG PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG PIOA_SODR; // Set Output Data Register
+ AT91_REG PIOA_CODR; // Clear Output Data Register
+ AT91_REG PIOA_ODSR; // Output Data Status Register
+ AT91_REG PIOA_PDSR; // Pin Data Status Register
+ AT91_REG PIOA_IER; // Interrupt Enable Register
+ AT91_REG PIOA_IDR; // Interrupt Disable Register
+ AT91_REG PIOA_IMR; // Interrupt Mask Register
+ AT91_REG PIOA_ISR; // Interrupt Status Register
+ AT91_REG PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG PIOA_ASR; // Select A Register
+ AT91_REG PIOA_BSR; // Select B Register
+ AT91_REG PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved17[9]; //
+ AT91_REG PIOA_OWER; // Output Write Enable Register
+ AT91_REG PIOA_OWDR; // Output Write Disable Register
+ AT91_REG PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved18[85]; //
+ AT91_REG PIOB_PER; // PIO Enable Register
+ AT91_REG PIOB_PDR; // PIO Disable Register
+ AT91_REG PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved19[1]; //
+ AT91_REG PIOB_OER; // Output Enable Register
+ AT91_REG PIOB_ODR; // Output Disable Registerr
+ AT91_REG PIOB_OSR; // Output Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG PIOB_IFER; // Input Filter Enable Register
+ AT91_REG PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG PIOB_SODR; // Set Output Data Register
+ AT91_REG PIOB_CODR; // Clear Output Data Register
+ AT91_REG PIOB_ODSR; // Output Data Status Register
+ AT91_REG PIOB_PDSR; // Pin Data Status Register
+ AT91_REG PIOB_IER; // Interrupt Enable Register
+ AT91_REG PIOB_IDR; // Interrupt Disable Register
+ AT91_REG PIOB_IMR; // Interrupt Mask Register
+ AT91_REG PIOB_ISR; // Interrupt Status Register
+ AT91_REG PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved23[1]; //
+ AT91_REG PIOB_ASR; // Select A Register
+ AT91_REG PIOB_BSR; // Select B Register
+ AT91_REG PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved24[9]; //
+ AT91_REG PIOB_OWER; // Output Write Enable Register
+ AT91_REG PIOB_OWDR; // Output Write Disable Register
+ AT91_REG PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved25[85]; //
+ AT91_REG PIOC_PER; // PIO Enable Register
+ AT91_REG PIOC_PDR; // PIO Disable Register
+ AT91_REG PIOC_PSR; // PIO Status Register
+ AT91_REG Reserved26[1]; //
+ AT91_REG PIOC_OER; // Output Enable Register
+ AT91_REG PIOC_ODR; // Output Disable Registerr
+ AT91_REG PIOC_OSR; // Output Status Register
+ AT91_REG Reserved27[1]; //
+ AT91_REG PIOC_IFER; // Input Filter Enable Register
+ AT91_REG PIOC_IFDR; // Input Filter Disable Register
+ AT91_REG PIOC_IFSR; // Input Filter Status Register
+ AT91_REG Reserved28[1]; //
+ AT91_REG PIOC_SODR; // Set Output Data Register
+ AT91_REG PIOC_CODR; // Clear Output Data Register
+ AT91_REG PIOC_ODSR; // Output Data Status Register
+ AT91_REG PIOC_PDSR; // Pin Data Status Register
+ AT91_REG PIOC_IER; // Interrupt Enable Register
+ AT91_REG PIOC_IDR; // Interrupt Disable Register
+ AT91_REG PIOC_IMR; // Interrupt Mask Register
+ AT91_REG PIOC_ISR; // Interrupt Status Register
+ AT91_REG PIOC_MDER; // Multi-driver Enable Register
+ AT91_REG PIOC_MDDR; // Multi-driver Disable Register
+ AT91_REG PIOC_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved29[1]; //
+ AT91_REG PIOC_PPUDR; // Pull-up Disable Register
+ AT91_REG PIOC_PPUER; // Pull-up Enable Register
+ AT91_REG PIOC_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved30[1]; //
+ AT91_REG PIOC_ASR; // Select A Register
+ AT91_REG PIOC_BSR; // Select B Register
+ AT91_REG PIOC_ABSR; // AB Select Status Register
+ AT91_REG Reserved31[9]; //
+ AT91_REG PIOC_OWER; // Output Write Enable Register
+ AT91_REG PIOC_OWDR; // Output Write Disable Register
+ AT91_REG PIOC_OWSR; // Output Write Status Register
+ AT91_REG Reserved32[213]; //
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved33[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved34[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG PMC_PLLAR; // PLL A Register
+ AT91_REG PMC_PLLBR; // PLL B Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved35[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved36[36]; //
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved37[1]; //
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register
+ AT91_REG Reserved38[1]; //
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved39[1]; //
+ AT91_REG SYS_GPBR0; // General Purpose Register 0
+ AT91_REG SYS_GPBR1; // General Purpose Register 1
+ AT91_REG SYS_GPBR2; // General Purpose Register 2
+ AT91_REG SYS_GPBR3; // General Purpose Register 3
+ AT91_REG Reserved40[39]; //
+ AT91_REG RSTC_VER; // Version Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define SYS_GPBR0 (AT91_CAST(AT91_REG *) 0x00001350) // (SYS_GPBR0) General Purpose Register 0
+#define SYS_GPBR1 (AT91_CAST(AT91_REG *) 0x00001354) // (SYS_GPBR1) General Purpose Register 1
+#define SYS_GPBR2 (AT91_CAST(AT91_REG *) 0x00001358) // (SYS_GPBR2) General Purpose Register 2
+#define SYS_GPBR3 (AT91_CAST(AT91_REG *) 0x0000135C) // (SYS_GPBR3) General Purpose Register 3
+
+#endif
+// -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register --------
+// -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register --------
+// -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register --------
+// -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SDRAMC {
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
+} AT91S_SDRAMC, *AT91PS_SDRAMC;
+#else
+#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
+#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
+#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
+#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
+#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
+#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
+#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
+#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
+
+#endif
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
+#define AT91C_SDRAMC_MODE (0xF << 0) // (SDRAMC) Mode
+#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
+#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
+#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
+#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
+#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
+#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
+#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
+#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
+#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
+#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
+#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
+#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
+#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
+#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
+#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
+#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
+#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
+#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
+#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
+#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
+#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
+#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
+#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
+#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
+#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
+#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
+#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
+#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
+#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
+#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
+#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
+#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
+#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
+#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
+#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
+#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
+#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
+#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
+#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
+#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
+#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
+#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
+#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
+#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
+#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
+#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
+ AT91_REG SMC_CTRL0; // Control Register for CS 0
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
+ AT91_REG SMC_CTRL1; // Control Register for CS 1
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
+ AT91_REG SMC_CTRL2; // Control Register for CS 2
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
+ AT91_REG SMC_CTRL3; // Control Register for CS 3
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
+ AT91_REG SMC_CTRL4; // Control Register for CS 4
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
+ AT91_REG SMC_CTRL5; // Control Register for CS 5
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
+ AT91_REG SMC_CTRL6; // Control Register for CS 6
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
+ AT91_REG SMC_CTRL7; // Control Register for CS 7
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
+#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
+#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
+#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
+#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
+#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
+#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
+#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
+#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
+#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
+#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
+#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
+#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
+#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
+#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
+#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
+#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
+#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
+#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
+#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
+#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
+#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
+#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
+#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
+#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
+#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
+#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
+#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
+#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
+#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
+#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
+#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
+#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
+#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
+#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
+#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
+#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
+#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
+#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
+#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
+#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
+#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
+#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
+#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
+#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+ AT91_REG MATRIX_MCFG; // Master Configuration Register
+ AT91_REG MATRIX_SCFG0; // Slave Configuration Register 0
+ AT91_REG MATRIX_SCFG1; // Slave Configuration Register 1
+ AT91_REG MATRIX_SCFG2; // Slave Configuration Register 2
+ AT91_REG MATRIX_SCFG3; // Slave Configuration Register 3
+ AT91_REG MATRIX_SCFG4; // Slave Configuration Register 4
+ AT91_REG Reserved0[3]; //
+ AT91_REG MATRIX_TCMR; // Slave 0 Special Function Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG MATRIX_EBICSA; // Slave 3 Special Function Register
+ AT91_REG MATRIX_USBPCR; // Slave 4 Special Function Register
+ AT91_REG Reserved2[3]; //
+ AT91_REG MATRIX_VERSION; // Version Register
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG) Master Configuration Register
+#define MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_SCFG0) Slave Configuration Register 0
+#define MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0x00000008) // (MATRIX_SCFG1) Slave Configuration Register 1
+#define MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0x0000000C) // (MATRIX_SCFG2) Slave Configuration Register 2
+#define MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0x00000010) // (MATRIX_SCFG3) Slave Configuration Register 3
+#define MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0x00000014) // (MATRIX_SCFG4) Slave Configuration Register 4
+#define MATRIX_TCMR (AT91_CAST(AT91_REG *) 0x00000024) // (MATRIX_TCMR) Slave 0 Special Function Register
+#define MATRIX_EBICSA (AT91_CAST(AT91_REG *) 0x00000030) // (MATRIX_EBICSA) Slave 3 Special Function Register
+#define MATRIX_USBPCR (AT91_CAST(AT91_REG *) 0x00000034) // (MATRIX_USBPCR) Slave 4 Special Function Register
+#define MATRIX_VERSION (AT91_CAST(AT91_REG *) 0x00000044) // (MATRIX_VERSION) Version Register
+
+#endif
+// -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register --------
+#define AT91C_MATRIX_RCA926I (0x1 << 0) // (MATRIX) Remap Command for ARM926EJ-S Instruction Master
+#define AT91C_MATRIX_RCA926D (0x1 << 1) // (MATRIX) Remap Command for ARM926EJ-S Data Master
+// -------- MATRIX_SCFG0 : (MATRIX Offset: 0x4) Slave Configuration Register 0 --------
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR0 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR0_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR0_UHP (0x4 << 18) // (MATRIX) UHP Master is Default Master
+// -------- MATRIX_SCFG1 : (MATRIX Offset: 0x8) Slave Configuration Register 1 --------
+#define AT91C_MATRIX_FIXED_DEFMSTR1 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR1_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR1_UHP (0x4 << 18) // (MATRIX) UHP Master is Default Master
+// -------- MATRIX_SCFG2 : (MATRIX Offset: 0xc) Slave Configuration Register 2 --------
+#define AT91C_MATRIX_FIXED_DEFMSTR2 (0x1 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+// -------- MATRIX_SCFG3 : (MATRIX Offset: 0x10) Slave Configuration Register 3 --------
+#define AT91C_MATRIX_FIXED_DEFMSTR3 (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR3_LCDC (0x3 << 18) // (MATRIX) LCDC Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR3_UHP (0x4 << 18) // (MATRIX) UHP Master is Default Master
+// -------- MATRIX_SCFG4 : (MATRIX Offset: 0x14) Slave Configuration Register 4 --------
+#define AT91C_MATRIX_FIXED_DEFMSTR4 (0x3 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I (0x0 << 18) // (MATRIX) ARM926EJ-S Instruction Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D (0x1 << 18) // (MATRIX) ARM926EJ-S Data Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 (0x2 << 18) // (MATRIX) HPDC3 Master is Default Master
+// -------- MATRIX_TCMR : (MATRIX Offset: 0x24) TCM (Slave 0) Special Function Register --------
+#define AT91C_MATRIX_ITCM_SIZE (0xF << 0) // (MATRIX) Size of ITCM enabled memory block
+#define AT91C_MATRIX_ITCM_SIZE_0KB (0x0) // (MATRIX) 0 KB (No ITCM Memory)
+#define AT91C_MATRIX_ITCM_SIZE_16KB (0x5) // (MATRIX) 16 KB
+#define AT91C_MATRIX_ITCM_SIZE_32KB (0x6) // (MATRIX) 32 KB
+#define AT91C_MATRIX_ITCM_SIZE_64KB (0x7) // (MATRIX) 64 KB
+#define AT91C_MATRIX_DTCM_SIZE (0xF << 4) // (MATRIX) Size of DTCM enabled memory block
+#define AT91C_MATRIX_DTCM_SIZE_0KB (0x0 << 4) // (MATRIX) 0 KB (No DTCM Memory)
+#define AT91C_MATRIX_DTCM_SIZE_16KB (0x5 << 4) // (MATRIX) 16 KB
+#define AT91C_MATRIX_DTCM_SIZE_32KB (0x6 << 4) // (MATRIX) 32 KB
+#define AT91C_MATRIX_DTCM_SIZE_64KB (0x7 << 4) // (MATRIX) 64 KB
+// -------- MATRIX_EBICSA : (MATRIX Offset: 0x30) EBI (Slave 3) Special Function Register --------
+#define AT91C_MATRIX_CS1A (0x1 << 1) // (MATRIX) Chip Select 1 Assignment
+#define AT91C_MATRIX_CS1A_SMC (0x0 << 1) // (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
+#define AT91C_MATRIX_CS1A_SDRAMC (0x1 << 1) // (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
+#define AT91C_MATRIX_CS3A (0x1 << 3) // (MATRIX) Chip Select 3 Assignment
+#define AT91C_MATRIX_CS3A_SMC (0x0 << 3) // (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
+#define AT91C_MATRIX_CS3A_SM (0x1 << 3) // (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
+#define AT91C_MATRIX_CS4A (0x1 << 4) // (MATRIX) Chip Select 4 Assignment
+#define AT91C_MATRIX_CS4A_SMC (0x0 << 4) // (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
+#define AT91C_MATRIX_CS4A_CF (0x1 << 4) // (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
+#define AT91C_MATRIX_CS5A (0x1 << 5) // (MATRIX) Chip Select 5 Assignment
+#define AT91C_MATRIX_CS5A_SMC (0x0 << 5) // (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
+#define AT91C_MATRIX_CS5A_CF (0x1 << 5) // (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
+#define AT91C_MATRIX_DBPUC (0x1 << 8) // (MATRIX) Data Bus Pull-up Configuration
+// -------- MATRIX_USBPCR : (MATRIX Offset: 0x34) USB Pad Control Register --------
+#define AT91C_MATRIX_USBPCR_PUON (0x1 << 30) // (MATRIX) PullUp On
+#define AT91C_MATRIX_USBPCR_PUIDLE (0x1 << 31) // (MATRIX) PullUp Idle
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered
+#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
+
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG CKGR_PLLAR; // PLL A Register
+ AT91_REG CKGR_PLLBR; // PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
+#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
+#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
+
+#endif
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
+#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
+#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
+#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
+#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
+#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
+#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG PMC_PLLAR; // PLL A Register
+ AT91_REG PMC_PLLBR; // PLL B Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved2[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
+#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
+#define AT91C_PMC_HCK0 (0x1 << 16) // (PMC) AHB UHP Clock Output
+#define AT91C_PMC_HCK1 (0x1 << 17) // (PMC) AHB LCDC Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
+#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+#define AT91C_PMC_MDIV (0x3 << 8) // (PMC) Master Clock Division
+#define AT91C_PMC_MDIV_1 (0x0 << 8) // (PMC) The master clock and the processor clock are the same
+#define AT91C_PMC_MDIV_2 (0x1 << 8) // (PMC) The processor clock is twice as fast as the master clock
+#define AT91C_PMC_MDIV_3 (0x2 << 8) // (PMC) The processor clock is four times faster than the master clock
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved0[60]; //
+ AT91_REG RSTC_VER; // Version Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
+#define RSTC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (RSTC_VER) Version Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_ICERST (0x1 << 1) // (RSTC) ICE Interface Reset
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Enable
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
+#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
+#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
+#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) High Level.
+#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) Low Level.
+#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
+#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
+#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
+#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
+#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
+#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
+#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+ AT91_REG Reserved3[9]; //
+ AT91_REG TCB_ADDRSIZE; // TC ADDRSIZE REGISTER
+ AT91_REG TCB_IPNAME1; // TC IPNAME1 REGISTER
+ AT91_REG TCB_IPNAME2; // TC IPNAME2 REGISTER
+ AT91_REG TCB_FEATURES; // TC FEATURES REGISTER
+ AT91_REG TCB_VER; // Version Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
+#define TC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER
+#define TC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER
+#define TC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER
+#define TC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER
+#define TC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TC_VER) Version Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+#else
+#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
+#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
+#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
+#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
+#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
+#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
+#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
+#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
+#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
+#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
+#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
+#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
+
+#endif
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
+#define AT91C_UDP_PUON (0x1 << 9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Multimedia Card Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MCI {
+ AT91_REG MCI_CR; // MCI Control Register
+ AT91_REG MCI_MR; // MCI Mode Register
+ AT91_REG MCI_DTOR; // MCI Data Timeout Register
+ AT91_REG MCI_SDCR; // MCI SD/SDIO Card Register
+ AT91_REG MCI_ARGR; // MCI Argument Register
+ AT91_REG MCI_CMDR; // MCI Command Register
+ AT91_REG MCI_BLKR; // MCI Block Register
+ AT91_REG MCI_CSTOR; // MCI Completion Signal Timeout Register
+ AT91_REG MCI_RSPR[4]; // MCI Response Register
+ AT91_REG MCI_RDR; // MCI Receive Data Register
+ AT91_REG MCI_TDR; // MCI Transmit Data Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG MCI_SR; // MCI Status Register
+ AT91_REG MCI_IER; // MCI Interrupt Enable Register
+ AT91_REG MCI_IDR; // MCI Interrupt Disable Register
+ AT91_REG MCI_IMR; // MCI Interrupt Mask Register
+ AT91_REG MCI_DMA; // MCI DMA Configuration Register
+ AT91_REG MCI_CFG; // MCI Configuration Register
+ AT91_REG Reserved1[35]; //
+ AT91_REG MCI_WPCR; // MCI Write Protection Control Register
+ AT91_REG MCI_WPSR; // MCI Write Protection Status Register
+ AT91_REG MCI_ADDRSIZE; // MCI ADDRSIZE REGISTER
+ AT91_REG MCI_IPNAME1; // MCI IPNAME1 REGISTER
+ AT91_REG MCI_IPNAME2; // MCI IPNAME2 REGISTER
+ AT91_REG MCI_FEATURES; // MCI FEATURES REGISTER
+ AT91_REG MCI_VER; // MCI VERSION REGISTER
+ AT91_REG MCI_RPR; // Receive Pointer Register
+ AT91_REG MCI_RCR; // Receive Counter Register
+ AT91_REG MCI_TPR; // Transmit Pointer Register
+ AT91_REG MCI_TCR; // Transmit Counter Register
+ AT91_REG MCI_RNPR; // Receive Next Pointer Register
+ AT91_REG MCI_RNCR; // Receive Next Counter Register
+ AT91_REG MCI_TNPR; // Transmit Next Pointer Register
+ AT91_REG MCI_TNCR; // Transmit Next Counter Register
+ AT91_REG MCI_PTCR; // PDC Transfer Control Register
+ AT91_REG MCI_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved2[54]; //
+ AT91_REG MCI_FIFO; // MCI FIFO Aperture Register
+} AT91S_MCI, *AT91PS_MCI;
+#else
+#define MCI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (MCI_CR) MCI Control Register
+#define MCI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (MCI_MR) MCI Mode Register
+#define MCI_DTOR (AT91_CAST(AT91_REG *) 0x00000008) // (MCI_DTOR) MCI Data Timeout Register
+#define MCI_SDCR (AT91_CAST(AT91_REG *) 0x0000000C) // (MCI_SDCR) MCI SD/SDIO Card Register
+#define MCI_ARGR (AT91_CAST(AT91_REG *) 0x00000010) // (MCI_ARGR) MCI Argument Register
+#define MCI_CMDR (AT91_CAST(AT91_REG *) 0x00000014) // (MCI_CMDR) MCI Command Register
+#define MCI_BLKR (AT91_CAST(AT91_REG *) 0x00000018) // (MCI_BLKR) MCI Block Register
+#define MCI_CSTOR (AT91_CAST(AT91_REG *) 0x0000001C) // (MCI_CSTOR) MCI Completion Signal Timeout Register
+#define MCI_RSPR (AT91_CAST(AT91_REG *) 0x00000020) // (MCI_RSPR) MCI Response Register
+#define MCI_RDR (AT91_CAST(AT91_REG *) 0x00000030) // (MCI_RDR) MCI Receive Data Register
+#define MCI_TDR (AT91_CAST(AT91_REG *) 0x00000034) // (MCI_TDR) MCI Transmit Data Register
+#define MCI_SR (AT91_CAST(AT91_REG *) 0x00000040) // (MCI_SR) MCI Status Register
+#define MCI_IER (AT91_CAST(AT91_REG *) 0x00000044) // (MCI_IER) MCI Interrupt Enable Register
+#define MCI_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (MCI_IDR) MCI Interrupt Disable Register
+#define MCI_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (MCI_IMR) MCI Interrupt Mask Register
+#define MCI_DMA (AT91_CAST(AT91_REG *) 0x00000050) // (MCI_DMA) MCI DMA Configuration Register
+#define MCI_CFG (AT91_CAST(AT91_REG *) 0x00000054) // (MCI_CFG) MCI Configuration Register
+#define MCI_WPCR (AT91_CAST(AT91_REG *) 0x000000E4) // (MCI_WPCR) MCI Write Protection Control Register
+#define MCI_WPSR (AT91_CAST(AT91_REG *) 0x000000E8) // (MCI_WPSR) MCI Write Protection Status Register
+#define MCI_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (MCI_ADDRSIZE) MCI ADDRSIZE REGISTER
+#define MCI_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (MCI_IPNAME1) MCI IPNAME1 REGISTER
+#define MCI_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (MCI_IPNAME2) MCI IPNAME2 REGISTER
+#define MCI_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (MCI_FEATURES) MCI FEATURES REGISTER
+#define MCI_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (MCI_VER) MCI VERSION REGISTER
+#define MCI_FIFO (AT91_CAST(AT91_REG *) 0x00000200) // (MCI_FIFO) MCI FIFO Aperture Register
+
+#endif
+// -------- MCI_CR : (MCI Offset: 0x0) MCI Control Register --------
+#define AT91C_MCI_MCIEN (0x1 << 0) // (MCI) Multimedia Interface Enable
+#define AT91C_MCI_MCIEN_0 (0x0) // (MCI) No effect
+#define AT91C_MCI_MCIEN_1 (0x1) // (MCI) Enable the MultiMedia Interface if MCIDIS is 0
+#define AT91C_MCI_MCIDIS (0x1 << 1) // (MCI) Multimedia Interface Disable
+#define AT91C_MCI_MCIDIS_0 (0x0 << 1) // (MCI) No effect
+#define AT91C_MCI_MCIDIS_1 (0x1 << 1) // (MCI) Disable the MultiMedia Interface
+#define AT91C_MCI_PWSEN (0x1 << 2) // (MCI) Power Save Mode Enable
+#define AT91C_MCI_PWSEN_0 (0x0 << 2) // (MCI) No effect
+#define AT91C_MCI_PWSEN_1 (0x1 << 2) // (MCI) Enable the Power-saving mode if PWSDIS is 0.
+#define AT91C_MCI_PWSDIS (0x1 << 3) // (MCI) Power Save Mode Disable
+#define AT91C_MCI_PWSDIS_0 (0x0 << 3) // (MCI) No effect
+#define AT91C_MCI_PWSDIS_1 (0x1 << 3) // (MCI) Disable the Power-saving mode.
+#define AT91C_MCI_IOWAITEN (0x1 << 4) // (MCI) SDIO Read Wait Enable
+#define AT91C_MCI_IOWAITEN_0 (0x0 << 4) // (MCI) No effect
+#define AT91C_MCI_IOWAITEN_1 (0x1 << 4) // (MCI) Enables the SDIO Read Wait Operation.
+#define AT91C_MCI_IOWAITDIS (0x1 << 5) // (MCI) SDIO Read Wait Disable
+#define AT91C_MCI_IOWAITDIS_0 (0x0 << 5) // (MCI) No effect
+#define AT91C_MCI_IOWAITDIS_1 (0x1 << 5) // (MCI) Disables the SDIO Read Wait Operation.
+#define AT91C_MCI_SWRST (0x1 << 7) // (MCI) MCI Software reset
+#define AT91C_MCI_SWRST_0 (0x0 << 7) // (MCI) No effect
+#define AT91C_MCI_SWRST_1 (0x1 << 7) // (MCI) Resets the MCI
+// -------- MCI_MR : (MCI Offset: 0x4) MCI Mode Register --------
+#define AT91C_MCI_CLKDIV (0xFF << 0) // (MCI) Clock Divider
+#define AT91C_MCI_PWSDIV (0x7 << 8) // (MCI) Power Saving Divider
+#define AT91C_MCI_RDPROOF (0x1 << 11) // (MCI) Read Proof Enable
+#define AT91C_MCI_RDPROOF_DISABLE (0x0 << 11) // (MCI) Disables Read Proof
+#define AT91C_MCI_RDPROOF_ENABLE (0x1 << 11) // (MCI) Enables Read Proof
+#define AT91C_MCI_WRPROOF (0x1 << 12) // (MCI) Write Proof Enable
+#define AT91C_MCI_WRPROOF_DISABLE (0x0 << 12) // (MCI) Disables Write Proof
+#define AT91C_MCI_WRPROOF_ENABLE (0x1 << 12) // (MCI) Enables Write Proof
+#define AT91C_MCI_PDCFBYTE (0x1 << 13) // (MCI) PDC Force Byte Transfer
+#define AT91C_MCI_PDCFBYTE_DISABLE (0x0 << 13) // (MCI) Disables PDC Force Byte Transfer
+#define AT91C_MCI_PDCFBYTE_ENABLE (0x1 << 13) // (MCI) Enables PDC Force Byte Transfer
+#define AT91C_MCI_PDCPADV (0x1 << 14) // (MCI) PDC Padding Value
+#define AT91C_MCI_PDCMODE (0x1 << 15) // (MCI) PDC Oriented Mode
+#define AT91C_MCI_PDCMODE_DISABLE (0x0 << 15) // (MCI) Disables PDC Transfer
+#define AT91C_MCI_PDCMODE_ENABLE (0x1 << 15) // (MCI) Enables PDC Transfer
+#define AT91C_MCI_BLKLEN (0xFFFF << 16) // (MCI) Data Block Length
+// -------- MCI_DTOR : (MCI Offset: 0x8) MCI Data Timeout Register --------
+#define AT91C_MCI_DTOCYC (0xF << 0) // (MCI) Data Timeout Cycle Number
+#define AT91C_MCI_DTOMUL (0x7 << 4) // (MCI) Data Timeout Multiplier
+#define AT91C_MCI_DTOMUL_1 (0x0 << 4) // (MCI) DTOCYC x 1
+#define AT91C_MCI_DTOMUL_16 (0x1 << 4) // (MCI) DTOCYC x 16
+#define AT91C_MCI_DTOMUL_128 (0x2 << 4) // (MCI) DTOCYC x 128
+#define AT91C_MCI_DTOMUL_256 (0x3 << 4) // (MCI) DTOCYC x 256
+#define AT91C_MCI_DTOMUL_1024 (0x4 << 4) // (MCI) DTOCYC x 1024
+#define AT91C_MCI_DTOMUL_4096 (0x5 << 4) // (MCI) DTOCYC x 4096
+#define AT91C_MCI_DTOMUL_65536 (0x6 << 4) // (MCI) DTOCYC x 65536
+#define AT91C_MCI_DTOMUL_1048576 (0x7 << 4) // (MCI) DTOCYC x 1048576
+// -------- MCI_SDCR : (MCI Offset: 0xc) MCI SD Card Register --------
+#define AT91C_MCI_SCDSEL (0x3 << 0) // (MCI) SD Card/SDIO Selector
+#define AT91C_MCI_SCDSEL_SLOTA (0x0) // (MCI) Slot A selected
+#define AT91C_MCI_SCDSEL_SLOTB (0x1) // (MCI) Slot B selected
+#define AT91C_MCI_SCDSEL_SLOTC (0x2) // (MCI) Slot C selected
+#define AT91C_MCI_SCDSEL_SLOTD (0x3) // (MCI) Slot D selected
+#define AT91C_MCI_SCDBUS (0x3 << 6) // (MCI) SDCard/SDIO Bus Width
+#define AT91C_MCI_SCDBUS_1BIT (0x0 << 6) // (MCI) 1-bit data bus
+#define AT91C_MCI_SCDBUS_4BITS (0x2 << 6) // (MCI) 4-bits data bus
+#define AT91C_MCI_SCDBUS_8BITS (0x3 << 6) // (MCI) 8-bits data bus
+// -------- MCI_CMDR : (MCI Offset: 0x14) MCI Command Register --------
+#define AT91C_MCI_CMDNB (0x3F << 0) // (MCI) Command Number
+#define AT91C_MCI_RSPTYP (0x3 << 6) // (MCI) Response Type
+#define AT91C_MCI_RSPTYP_NO (0x0 << 6) // (MCI) No response
+#define AT91C_MCI_RSPTYP_48 (0x1 << 6) // (MCI) 48-bit response
+#define AT91C_MCI_RSPTYP_136 (0x2 << 6) // (MCI) 136-bit response
+#define AT91C_MCI_RSPTYP_R1B (0x3 << 6) // (MCI) R1b response
+#define AT91C_MCI_SPCMD (0x7 << 8) // (MCI) Special CMD
+#define AT91C_MCI_SPCMD_NONE (0x0 << 8) // (MCI) Not a special CMD
+#define AT91C_MCI_SPCMD_INIT (0x1 << 8) // (MCI) Initialization CMD
+#define AT91C_MCI_SPCMD_SYNC (0x2 << 8) // (MCI) Synchronized CMD
+#define AT91C_MCI_SPCMD_CE_ATA (0x3 << 8) // (MCI) CE-ATA Completion Signal disable CMD
+#define AT91C_MCI_SPCMD_IT_CMD (0x4 << 8) // (MCI) Interrupt command
+#define AT91C_MCI_SPCMD_IT_REP (0x5 << 8) // (MCI) Interrupt response
+#define AT91C_MCI_OPDCMD (0x1 << 11) // (MCI) Open Drain Command
+#define AT91C_MCI_OPDCMD_PUSHPULL (0x0 << 11) // (MCI) Push/pull command
+#define AT91C_MCI_OPDCMD_OPENDRAIN (0x1 << 11) // (MCI) Open drain command
+#define AT91C_MCI_MAXLAT (0x1 << 12) // (MCI) Maximum Latency for Command to respond
+#define AT91C_MCI_MAXLAT_5 (0x0 << 12) // (MCI) 5 cycles maximum latency
+#define AT91C_MCI_MAXLAT_64 (0x1 << 12) // (MCI) 64 cycles maximum latency
+#define AT91C_MCI_TRCMD (0x3 << 16) // (MCI) Transfer CMD
+#define AT91C_MCI_TRCMD_NO (0x0 << 16) // (MCI) No transfer
+#define AT91C_MCI_TRCMD_START (0x1 << 16) // (MCI) Start transfer
+#define AT91C_MCI_TRCMD_STOP (0x2 << 16) // (MCI) Stop transfer
+#define AT91C_MCI_TRDIR (0x1 << 18) // (MCI) Transfer Direction
+#define AT91C_MCI_TRDIR_WRITE (0x0 << 18) // (MCI) Write
+#define AT91C_MCI_TRDIR_READ (0x1 << 18) // (MCI) Read
+#define AT91C_MCI_TRTYP (0x7 << 19) // (MCI) Transfer Type
+#define AT91C_MCI_TRTYP_BLOCK (0x0 << 19) // (MCI) MMC/SDCard Single Block Transfer type
+#define AT91C_MCI_TRTYP_MULTIPLE (0x1 << 19) // (MCI) MMC/SDCard Multiple Block transfer type
+#define AT91C_MCI_TRTYP_STREAM (0x2 << 19) // (MCI) MMC Stream transfer type
+#define AT91C_MCI_TRTYP_SDIO_BYTE (0x4 << 19) // (MCI) SDIO Byte transfer type
+#define AT91C_MCI_TRTYP_SDIO_BLOCK (0x5 << 19) // (MCI) SDIO Block transfer type
+#define AT91C_MCI_IOSPCMD (0x3 << 24) // (MCI) SDIO Special Command
+#define AT91C_MCI_IOSPCMD_NONE (0x0 << 24) // (MCI) NOT a special command
+#define AT91C_MCI_IOSPCMD_SUSPEND (0x1 << 24) // (MCI) SDIO Suspend Command
+#define AT91C_MCI_IOSPCMD_RESUME (0x2 << 24) // (MCI) SDIO Resume Command
+#define AT91C_MCI_ATACS (0x1 << 26) // (MCI) ATA with command completion signal
+#define AT91C_MCI_ATACS_NORMAL (0x0 << 26) // (MCI) normal operation mode
+#define AT91C_MCI_ATACS_COMPLETION (0x1 << 26) // (MCI) completion signal is expected within MCI_CSTOR
+// -------- MCI_BLKR : (MCI Offset: 0x18) MCI Block Register --------
+#define AT91C_MCI_BCNT (0xFFFF << 0) // (MCI) MMC/SDIO Block Count / SDIO Byte Count
+// -------- MCI_CSTOR : (MCI Offset: 0x1c) MCI Completion Signal Timeout Register --------
+#define AT91C_MCI_CSTOCYC (0xF << 0) // (MCI) Completion Signal Timeout Cycle Number
+#define AT91C_MCI_CSTOMUL (0x7 << 4) // (MCI) Completion Signal Timeout Multiplier
+#define AT91C_MCI_CSTOMUL_1 (0x0 << 4) // (MCI) CSTOCYC x 1
+#define AT91C_MCI_CSTOMUL_16 (0x1 << 4) // (MCI) CSTOCYC x 16
+#define AT91C_MCI_CSTOMUL_128 (0x2 << 4) // (MCI) CSTOCYC x 128
+#define AT91C_MCI_CSTOMUL_256 (0x3 << 4) // (MCI) CSTOCYC x 256
+#define AT91C_MCI_CSTOMUL_1024 (0x4 << 4) // (MCI) CSTOCYC x 1024
+#define AT91C_MCI_CSTOMUL_4096 (0x5 << 4) // (MCI) CSTOCYC x 4096
+#define AT91C_MCI_CSTOMUL_65536 (0x6 << 4) // (MCI) CSTOCYC x 65536
+#define AT91C_MCI_CSTOMUL_1048576 (0x7 << 4) // (MCI) CSTOCYC x 1048576
+// -------- MCI_SR : (MCI Offset: 0x40) MCI Status Register --------
+#define AT91C_MCI_CMDRDY (0x1 << 0) // (MCI) Command Ready flag
+#define AT91C_MCI_RXRDY (0x1 << 1) // (MCI) RX Ready flag
+#define AT91C_MCI_TXRDY (0x1 << 2) // (MCI) TX Ready flag
+#define AT91C_MCI_BLKE (0x1 << 3) // (MCI) Data Block Transfer Ended flag
+#define AT91C_MCI_DTIP (0x1 << 4) // (MCI) Data Transfer in Progress flag
+#define AT91C_MCI_NOTBUSY (0x1 << 5) // (MCI) Data Line Not Busy flag
+#define AT91C_MCI_ENDRX (0x1 << 6) // (MCI) End of RX Buffer flag
+#define AT91C_MCI_ENDTX (0x1 << 7) // (MCI) End of TX Buffer flag
+#define AT91C_MCI_SDIOIRQA (0x1 << 8) // (MCI) SDIO Interrupt for Slot A
+#define AT91C_MCI_SDIOIRQB (0x1 << 9) // (MCI) SDIO Interrupt for Slot B
+#define AT91C_MCI_SDIOIRQC (0x1 << 10) // (MCI) SDIO Interrupt for Slot C
+#define AT91C_MCI_SDIOIRQD (0x1 << 11) // (MCI) SDIO Interrupt for Slot D
+#define AT91C_MCI_SDIOWAIT (0x1 << 12) // (MCI) SDIO Read Wait operation flag
+#define AT91C_MCI_CSRCV (0x1 << 13) // (MCI) CE-ATA Completion Signal flag
+#define AT91C_MCI_RXBUFF (0x1 << 14) // (MCI) RX Buffer Full flag
+#define AT91C_MCI_TXBUFE (0x1 << 15) // (MCI) TX Buffer Empty flag
+#define AT91C_MCI_RINDE (0x1 << 16) // (MCI) Response Index Error flag
+#define AT91C_MCI_RDIRE (0x1 << 17) // (MCI) Response Direction Error flag
+#define AT91C_MCI_RCRCE (0x1 << 18) // (MCI) Response CRC Error flag
+#define AT91C_MCI_RENDE (0x1 << 19) // (MCI) Response End Bit Error flag
+#define AT91C_MCI_RTOE (0x1 << 20) // (MCI) Response Time-out Error flag
+#define AT91C_MCI_DCRCE (0x1 << 21) // (MCI) data CRC Error flag
+#define AT91C_MCI_DTOE (0x1 << 22) // (MCI) Data timeout Error flag
+#define AT91C_MCI_CSTOE (0x1 << 23) // (MCI) Completion Signal timeout Error flag
+#define AT91C_MCI_BLKOVRE (0x1 << 24) // (MCI) DMA Block Overrun Error flag
+#define AT91C_MCI_DMADONE (0x1 << 25) // (MCI) DMA Transfer Done flag
+#define AT91C_MCI_FIFOEMPTY (0x1 << 26) // (MCI) FIFO Empty flag
+#define AT91C_MCI_XFRDONE (0x1 << 27) // (MCI) Transfer Done flag
+#define AT91C_MCI_OVRE (0x1 << 30) // (MCI) Overrun flag
+#define AT91C_MCI_UNRE (0x1 << 31) // (MCI) Underrun flag
+// -------- MCI_IER : (MCI Offset: 0x44) MCI Interrupt Enable Register --------
+// -------- MCI_IDR : (MCI Offset: 0x48) MCI Interrupt Disable Register --------
+// -------- MCI_IMR : (MCI Offset: 0x4c) MCI Interrupt Mask Register --------
+// -------- MCI_DMA : (MCI Offset: 0x50) MCI DMA Configuration Register --------
+#define AT91C_MCI_OFFSET (0x3 << 0) // (MCI) DMA Write Buffer Offset
+#define AT91C_MCI_CHKSIZE (0x7 << 4) // (MCI) DMA Channel Read/Write Chunk Size
+#define AT91C_MCI_CHKSIZE_1 (0x0 << 4) // (MCI) Number of data transferred is 1
+#define AT91C_MCI_CHKSIZE_4 (0x1 << 4) // (MCI) Number of data transferred is 4
+#define AT91C_MCI_CHKSIZE_8 (0x2 << 4) // (MCI) Number of data transferred is 8
+#define AT91C_MCI_CHKSIZE_16 (0x3 << 4) // (MCI) Number of data transferred is 16
+#define AT91C_MCI_CHKSIZE_32 (0x4 << 4) // (MCI) Number of data transferred is 32
+#define AT91C_MCI_DMAEN (0x1 << 8) // (MCI) DMA Hardware Handshaking Enable
+#define AT91C_MCI_DMAEN_DISABLE (0x0 << 8) // (MCI) DMA interface is disabled
+#define AT91C_MCI_DMAEN_ENABLE (0x1 << 8) // (MCI) DMA interface is enabled
+// -------- MCI_CFG : (MCI Offset: 0x54) MCI Configuration Register --------
+#define AT91C_MCI_FIFOMODE (0x1 << 0) // (MCI) MCI Internal FIFO Control Mode
+#define AT91C_MCI_FIFOMODE_AMOUNTDATA (0x0) // (MCI) A write transfer starts when a sufficient amount of datas is written into the FIFO
+#define AT91C_MCI_FIFOMODE_ONEDATA (0x1) // (MCI) A write transfer starts as soon as one data is written into the FIFO
+#define AT91C_MCI_FERRCTRL (0x1 << 4) // (MCI) Flow Error Flag Reset Control Mode
+#define AT91C_MCI_FERRCTRL_RWCMD (0x0 << 4) // (MCI) When an underflow/overflow condition flag is set, a new Write/Read command is needed to reset the flag
+#define AT91C_MCI_FERRCTRL_READSR (0x1 << 4) // (MCI) When an underflow/overflow condition flag is set, a read status resets the flag
+#define AT91C_MCI_HSMODE (0x1 << 8) // (MCI) High Speed Mode
+#define AT91C_MCI_HSMODE_DISABLE (0x0 << 8) // (MCI) Default Bus Timing Mode
+#define AT91C_MCI_HSMODE_ENABLE (0x1 << 8) // (MCI) High Speed Mode
+#define AT91C_MCI_LSYNC (0x1 << 12) // (MCI) Synchronize on last block
+#define AT91C_MCI_LSYNC_CURRENT (0x0 << 12) // (MCI) Pending command sent at end of current data block
+#define AT91C_MCI_LSYNC_INFINITE (0x1 << 12) // (MCI) Pending command sent at end of block transfer when transfer length is not infinite
+// -------- MCI_WPCR : (MCI Offset: 0xe4) Write Protection Control Register --------
+#define AT91C_MCI_WP_EN (0x1 << 0) // (MCI) Write Protection Enable
+#define AT91C_MCI_WP_EN_DISABLE (0x0) // (MCI) Write Operation is disabled (if WP_KEY corresponds)
+#define AT91C_MCI_WP_EN_ENABLE (0x1) // (MCI) Write Operation is enabled (if WP_KEY corresponds)
+#define AT91C_MCI_WP_KEY (0xFFFFFF << 8) // (MCI) Write Protection Key
+// -------- MCI_WPSR : (MCI Offset: 0xe8) Write Protection Status Register --------
+#define AT91C_MCI_WP_VS (0xF << 0) // (MCI) Write Protection Violation Status
+#define AT91C_MCI_WP_VS_NO_VIOLATION (0x0) // (MCI) No Write Protection Violation detected since last read
+#define AT91C_MCI_WP_VS_ON_WRITE (0x1) // (MCI) Write Protection Violation detected since last read
+#define AT91C_MCI_WP_VS_ON_RESET (0x2) // (MCI) Software Reset Violation detected since last read
+#define AT91C_MCI_WP_VS_ON_BOTH (0x3) // (MCI) Write Protection and Software Reset Violation detected since last read
+#define AT91C_MCI_WP_VSRC (0xF << 8) // (MCI) Write Protection Violation Source
+#define AT91C_MCI_WP_VSRC_NO_VIOLATION (0x0 << 8) // (MCI) No Write Protection Violation detected since last read
+#define AT91C_MCI_WP_VSRC_MCI_MR (0x1 << 8) // (MCI) Write Protection Violation detected on MCI_MR since last read
+#define AT91C_MCI_WP_VSRC_MCI_DTOR (0x2 << 8) // (MCI) Write Protection Violation detected on MCI_DTOR since last read
+#define AT91C_MCI_WP_VSRC_MCI_SDCR (0x3 << 8) // (MCI) Write Protection Violation detected on MCI_SDCR since last read
+#define AT91C_MCI_WP_VSRC_MCI_CSTOR (0x4 << 8) // (MCI) Write Protection Violation detected on MCI_CSTOR since last read
+#define AT91C_MCI_WP_VSRC_MCI_DMA (0x5 << 8) // (MCI) Write Protection Violation detected on MCI_DMA since last read
+#define AT91C_MCI_WP_VSRC_MCI_CFG (0x6 << 8) // (MCI) Write Protection Violation detected on MCI_CFG since last read
+#define AT91C_MCI_WP_VSRC_MCI_DEL (0x7 << 8) // (MCI) Write Protection Violation detected on MCI_DEL since last read
+// -------- MCI_VER : (MCI Offset: 0xfc) VERSION Register --------
+#define AT91C_MCI_VER (0xF << 0) // (MCI) VERSION Register
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Two-wire Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TWI {
+ AT91_REG TWI_CR; // Control Register
+ AT91_REG TWI_MMR; // Master Mode Register
+ AT91_REG TWI_SMR; // Slave Mode Register
+ AT91_REG TWI_IADR; // Internal Address Register
+ AT91_REG TWI_CWGR; // Clock Waveform Generator Register
+ AT91_REG Reserved0[3]; //
+ AT91_REG TWI_SR; // Status Register
+ AT91_REG TWI_IER; // Interrupt Enable Register
+ AT91_REG TWI_IDR; // Interrupt Disable Register
+ AT91_REG TWI_IMR; // Interrupt Mask Register
+ AT91_REG TWI_RHR; // Receive Holding Register
+ AT91_REG TWI_THR; // Transmit Holding Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG TWI_ADDRSIZE; // TWI ADDRSIZE REGISTER
+ AT91_REG TWI_IPNAME1; // TWI IPNAME1 REGISTER
+ AT91_REG TWI_IPNAME2; // TWI IPNAME2 REGISTER
+ AT91_REG TWI_FEATURES; // TWI FEATURES REGISTER
+ AT91_REG TWI_VER; // Version Register
+ AT91_REG TWI_RPR; // Receive Pointer Register
+ AT91_REG TWI_RCR; // Receive Counter Register
+ AT91_REG TWI_TPR; // Transmit Pointer Register
+ AT91_REG TWI_TCR; // Transmit Counter Register
+ AT91_REG TWI_RNPR; // Receive Next Pointer Register
+ AT91_REG TWI_RNCR; // Receive Next Counter Register
+ AT91_REG TWI_TNPR; // Transmit Next Pointer Register
+ AT91_REG TWI_TNCR; // Transmit Next Counter Register
+ AT91_REG TWI_PTCR; // PDC Transfer Control Register
+ AT91_REG TWI_PTSR; // PDC Transfer Status Register
+} AT91S_TWI, *AT91PS_TWI;
+#else
+#define TWI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (TWI_CR) Control Register
+#define TWI_MMR (AT91_CAST(AT91_REG *) 0x00000004) // (TWI_MMR) Master Mode Register
+#define TWI_SMR (AT91_CAST(AT91_REG *) 0x00000008) // (TWI_SMR) Slave Mode Register
+#define TWI_IADR (AT91_CAST(AT91_REG *) 0x0000000C) // (TWI_IADR) Internal Address Register
+#define TWI_CWGR (AT91_CAST(AT91_REG *) 0x00000010) // (TWI_CWGR) Clock Waveform Generator Register
+#define TWI_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TWI_SR) Status Register
+#define TWI_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TWI_IER) Interrupt Enable Register
+#define TWI_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TWI_IDR) Interrupt Disable Register
+#define TWI_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TWI_IMR) Interrupt Mask Register
+#define TWI_RHR (AT91_CAST(AT91_REG *) 0x00000030) // (TWI_RHR) Receive Holding Register
+#define TWI_THR (AT91_CAST(AT91_REG *) 0x00000034) // (TWI_THR) Transmit Holding Register
+#define TWI_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TWI_ADDRSIZE) TWI ADDRSIZE REGISTER
+#define TWI_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TWI_IPNAME1) TWI IPNAME1 REGISTER
+#define TWI_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TWI_IPNAME2) TWI IPNAME2 REGISTER
+#define TWI_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TWI_FEATURES) TWI FEATURES REGISTER
+#define TWI_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TWI_VER) Version Register
+
+#endif
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
+#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN (0x1 << 4) // (TWI) TWI Slave mode Enabled
+#define AT91C_TWI_SVDIS (0x1 << 5) // (TWI) TWI Slave mode Disabled
+#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
+#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size
+#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address
+#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address
+#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address
+#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register --------
+#define AT91C_TWI_SADR (0x7F << 16) // (TWI) Slave Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
+#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
+#define AT91C_TWI_TXCOMP_SLAVE (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_TXCOMP_MASTER (0x1 << 0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY_MASTER (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_TXRDY_SLAVE (0x1 << 2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD (0x1 << 3) // (TWI) Slave READ (used only in Slave mode)
+#define AT91C_TWI_SVACC (0x1 << 4) // (TWI) Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_GACC (0x1 << 5) // (TWI) General Call ACcess (used only in Slave mode)
+#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error (used only in Master and Multi-master mode)
+#define AT91C_TWI_NACK_SLAVE (0x1 << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_NACK_MASTER (0x1 << 8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST_MULTI_MASTER (0x1 << 9) // (TWI) Arbitration Lost (used only in Multimaster mode)
+#define AT91C_TWI_SCLWS (0x1 << 10) // (TWI) Clock Wait State (used only in Slave mode)
+#define AT91C_TWI_EOSACC (0x1 << 11) // (TWI) End Of Slave ACCess (used only in Slave mode)
+#define AT91C_TWI_ENDRX (0x1 << 12) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_ENDTX (0x1 << 13) // (TWI) End of Receiver Transfer
+#define AT91C_TWI_RXBUFF (0x1 << 14) // (TWI) RXBUFF Interrupt
+#define AT91C_TWI_TXBUFE (0x1 << 15) // (TWI) TXBUFE Interrupt
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG Reserved2[44]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
+#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
+#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
+#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SSC {
+ AT91_REG SSC_CR; // Control Register
+ AT91_REG SSC_CMR; // Clock Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG SSC_RCMR; // Receive Clock ModeRegister
+ AT91_REG SSC_RFMR; // Receive Frame Mode Register
+ AT91_REG SSC_TCMR; // Transmit Clock Mode Register
+ AT91_REG SSC_TFMR; // Transmit Frame Mode Register
+ AT91_REG SSC_RHR; // Receive Holding Register
+ AT91_REG SSC_THR; // Transmit Holding Register
+ AT91_REG Reserved1[2]; //
+ AT91_REG SSC_RSHR; // Receive Sync Holding Register
+ AT91_REG SSC_TSHR; // Transmit Sync Holding Register
+ AT91_REG Reserved2[2]; //
+ AT91_REG SSC_SR; // Status Register
+ AT91_REG SSC_IER; // Interrupt Enable Register
+ AT91_REG SSC_IDR; // Interrupt Disable Register
+ AT91_REG SSC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved3[39]; //
+ AT91_REG SSC_ADDRSIZE; // SSC ADDRSIZE REGISTER
+ AT91_REG SSC_IPNAME1; // SSC IPNAME1 REGISTER
+ AT91_REG SSC_IPNAME2; // SSC IPNAME2 REGISTER
+ AT91_REG SSC_FEATURES; // SSC FEATURES REGISTER
+ AT91_REG SSC_VER; // Version Register
+ AT91_REG SSC_RPR; // Receive Pointer Register
+ AT91_REG SSC_RCR; // Receive Counter Register
+ AT91_REG SSC_TPR; // Transmit Pointer Register
+ AT91_REG SSC_TCR; // Transmit Counter Register
+ AT91_REG SSC_RNPR; // Receive Next Pointer Register
+ AT91_REG SSC_RNCR; // Receive Next Counter Register
+ AT91_REG SSC_TNPR; // Transmit Next Pointer Register
+ AT91_REG SSC_TNCR; // Transmit Next Counter Register
+ AT91_REG SSC_PTCR; // PDC Transfer Control Register
+ AT91_REG SSC_PTSR; // PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+#else
+#define SSC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SSC_CR) Control Register
+#define SSC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (SSC_CMR) Clock Mode Register
+#define SSC_RCMR (AT91_CAST(AT91_REG *) 0x00000010) // (SSC_RCMR) Receive Clock ModeRegister
+#define SSC_RFMR (AT91_CAST(AT91_REG *) 0x00000014) // (SSC_RFMR) Receive Frame Mode Register
+#define SSC_TCMR (AT91_CAST(AT91_REG *) 0x00000018) // (SSC_TCMR) Transmit Clock Mode Register
+#define SSC_TFMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SSC_TFMR) Transmit Frame Mode Register
+#define SSC_RHR (AT91_CAST(AT91_REG *) 0x00000020) // (SSC_RHR) Receive Holding Register
+#define SSC_THR (AT91_CAST(AT91_REG *) 0x00000024) // (SSC_THR) Transmit Holding Register
+#define SSC_RSHR (AT91_CAST(AT91_REG *) 0x00000030) // (SSC_RSHR) Receive Sync Holding Register
+#define SSC_TSHR (AT91_CAST(AT91_REG *) 0x00000034) // (SSC_TSHR) Transmit Sync Holding Register
+#define SSC_SR (AT91_CAST(AT91_REG *) 0x00000040) // (SSC_SR) Status Register
+#define SSC_IER (AT91_CAST(AT91_REG *) 0x00000044) // (SSC_IER) Interrupt Enable Register
+#define SSC_IDR (AT91_CAST(AT91_REG *) 0x00000048) // (SSC_IDR) Interrupt Disable Register
+#define SSC_IMR (AT91_CAST(AT91_REG *) 0x0000004C) // (SSC_IMR) Interrupt Mask Register
+#define SSC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (SSC_ADDRSIZE) SSC ADDRSIZE REGISTER
+#define SSC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (SSC_IPNAME1) SSC IPNAME1 REGISTER
+#define SSC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (SSC_IPNAME2) SSC IPNAME2 REGISTER
+#define SSC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (SSC_FEATURES) SSC FEATURES REGISTER
+#define SSC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (SSC_VER) Version Register
+
+#endif
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
+#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
+#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection
+#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock
+#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal
+#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG (0x3 << 6) // (SSC) Receive/Transmit Clock Gating Selection
+#define AT91C_SSC_CKG_NONE (0x0 << 6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define AT91C_SSC_CKG_LOW (0x1 << 6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define AT91C_SSC_CKG_HIGH (0x2 << 6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection
+#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start
+#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input
+#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input
+#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input
+#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input
+#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input
+#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input
+#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0
+#define AT91C_SSC_STOP (0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
+#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length
+#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
+#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
+#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0 (0x1 << 8) // (SSC) Compare 0
+#define AT91C_SSC_CP1 (0x1 << 9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
+#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
+#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Host Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UHP {
+ AT91_REG UHP_HcRevision; // Revision
+ AT91_REG UHP_HcControl; // Operating modes for the Host Controller
+ AT91_REG UHP_HcCommandStatus; // Command & status Register
+ AT91_REG UHP_HcInterruptStatus; // Interrupt Status Register
+ AT91_REG UHP_HcInterruptEnable; // Interrupt Enable Register
+ AT91_REG UHP_HcInterruptDisable; // Interrupt Disable Register
+ AT91_REG UHP_HcHCCA; // Pointer to the Host Controller Communication Area
+ AT91_REG UHP_HcPeriodCurrentED; // Current Isochronous or Interrupt Endpoint Descriptor
+ AT91_REG UHP_HcControlHeadED; // First Endpoint Descriptor of the Control list
+ AT91_REG UHP_HcControlCurrentED; // Endpoint Control and Status Register
+ AT91_REG UHP_HcBulkHeadED; // First endpoint register of the Bulk list
+ AT91_REG UHP_HcBulkCurrentED; // Current endpoint of the Bulk list
+ AT91_REG UHP_HcBulkDoneHead; // Last completed transfer descriptor
+ AT91_REG UHP_HcFmInterval; // Bit time between 2 consecutive SOFs
+ AT91_REG UHP_HcFmRemaining; // Bit time remaining in the current Frame
+ AT91_REG UHP_HcFmNumber; // Frame number
+ AT91_REG UHP_HcPeriodicStart; // Periodic Start
+ AT91_REG UHP_HcLSThreshold; // LS Threshold
+ AT91_REG UHP_HcRhDescriptorA; // Root Hub characteristics A
+ AT91_REG UHP_HcRhDescriptorB; // Root Hub characteristics B
+ AT91_REG UHP_HcRhStatus; // Root Hub Status register
+ AT91_REG UHP_HcRhPortStatus[2]; // Root Hub Port Status Register
+} AT91S_UHP, *AT91PS_UHP;
+#else
+#define HcRevision (AT91_CAST(AT91_REG *) 0x00000000) // (HcRevision) Revision
+#define HcControl (AT91_CAST(AT91_REG *) 0x00000004) // (HcControl) Operating modes for the Host Controller
+#define HcCommandStatus (AT91_CAST(AT91_REG *) 0x00000008) // (HcCommandStatus) Command & status Register
+#define HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0000000C) // (HcInterruptStatus) Interrupt Status Register
+#define HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00000010) // (HcInterruptEnable) Interrupt Enable Register
+#define HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00000014) // (HcInterruptDisable) Interrupt Disable Register
+#define HcHCCA (AT91_CAST(AT91_REG *) 0x00000018) // (HcHCCA) Pointer to the Host Controller Communication Area
+#define HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0000001C) // (HcPeriodCurrentED) Current Isochronous or Interrupt Endpoint Descriptor
+#define HcControlHeadED (AT91_CAST(AT91_REG *) 0x00000020) // (HcControlHeadED) First Endpoint Descriptor of the Control list
+#define HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00000024) // (HcControlCurrentED) Endpoint Control and Status Register
+#define HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00000028) // (HcBulkHeadED) First endpoint register of the Bulk list
+#define HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0000002C) // (HcBulkCurrentED) Current endpoint of the Bulk list
+#define HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00000030) // (HcBulkDoneHead) Last completed transfer descriptor
+#define HcFmInterval (AT91_CAST(AT91_REG *) 0x00000034) // (HcFmInterval) Bit time between 2 consecutive SOFs
+#define HcFmRemaining (AT91_CAST(AT91_REG *) 0x00000038) // (HcFmRemaining) Bit time remaining in the current Frame
+#define HcFmNumber (AT91_CAST(AT91_REG *) 0x0000003C) // (HcFmNumber) Frame number
+#define HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00000040) // (HcPeriodicStart) Periodic Start
+#define HcLSThreshold (AT91_CAST(AT91_REG *) 0x00000044) // (HcLSThreshold) LS Threshold
+#define HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00000048) // (HcRhDescriptorA) Root Hub characteristics A
+#define HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0000004C) // (HcRhDescriptorB) Root Hub characteristics B
+#define HcRhStatus (AT91_CAST(AT91_REG *) 0x00000050) // (HcRhStatus) Root Hub Status register
+#define HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00000054) // (HcRhPortStatus) Root Hub Port Status Register
+
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR LCD Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_LCDC {
+ AT91_REG LCDC_BA1; // DMA Base Address Register 1
+ AT91_REG LCDC_BA2; // DMA Base Address Register 2
+ AT91_REG LCDC_FRMP1; // DMA Frame Pointer Register 1
+ AT91_REG LCDC_FRMP2; // DMA Frame Pointer Register 2
+ AT91_REG LCDC_FRMA1; // DMA Frame Address Register 1
+ AT91_REG LCDC_FRMA2; // DMA Frame Address Register 2
+ AT91_REG LCDC_FRMCFG; // DMA Frame Configuration Register
+ AT91_REG LCDC_DMACON; // DMA Control Register
+ AT91_REG LCDC_DMA2DCFG; // DMA 2D addressing configuration
+ AT91_REG Reserved0[503]; //
+ AT91_REG LCDC_LCDCON1; // LCD Control 1 Register
+ AT91_REG LCDC_LCDCON2; // LCD Control 2 Register
+ AT91_REG LCDC_TIM1; // LCD Timing Config 1 Register
+ AT91_REG LCDC_TIM2; // LCD Timing Config 2 Register
+ AT91_REG LCDC_LCDFRCFG; // LCD Frame Config Register
+ AT91_REG LCDC_FIFO; // LCD FIFO Register
+ AT91_REG LCDC_MVAL; // LCD Mode Toggle Rate Value Register
+ AT91_REG LCDC_DP1_2; // Dithering Pattern DP1_2 Register
+ AT91_REG LCDC_DP4_7; // Dithering Pattern DP4_7 Register
+ AT91_REG LCDC_DP3_5; // Dithering Pattern DP3_5 Register
+ AT91_REG LCDC_DP2_3; // Dithering Pattern DP2_3 Register
+ AT91_REG LCDC_DP5_7; // Dithering Pattern DP5_7 Register
+ AT91_REG LCDC_DP3_4; // Dithering Pattern DP3_4 Register
+ AT91_REG LCDC_DP4_5; // Dithering Pattern DP4_5 Register
+ AT91_REG LCDC_DP6_7; // Dithering Pattern DP6_7 Register
+ AT91_REG LCDC_PWRCON; // Power Control Register
+ AT91_REG LCDC_CTRSTCON; // Contrast Control Register
+ AT91_REG LCDC_CTRSTVAL; // Contrast Value Register
+ AT91_REG LCDC_IER; // Interrupt Enable Register
+ AT91_REG LCDC_IDR; // Interrupt Disable Register
+ AT91_REG LCDC_IMR; // Interrupt Mask Register
+ AT91_REG LCDC_ISR; // Interrupt Enable Register
+ AT91_REG LCDC_ICR; // Interrupt Clear Register
+ AT91_REG LCDC_GPR; // General Purpose Register
+ AT91_REG LCDC_ITR; // Interrupts Test Register
+ AT91_REG LCDC_IRR; // Interrupts Raw Status Register
+ AT91_REG Reserved1[230]; //
+ AT91_REG LCDC_LUT_ENTRY[256]; // LUT Entries Register
+} AT91S_LCDC, *AT91PS_LCDC;
+#else
+#define LCDC_BA1 (AT91_CAST(AT91_REG *) 0x00000000) // (LCDC_BA1) DMA Base Address Register 1
+#define LCDC_BA2 (AT91_CAST(AT91_REG *) 0x00000004) // (LCDC_BA2) DMA Base Address Register 2
+#define LCDC_FRMP1 (AT91_CAST(AT91_REG *) 0x00000008) // (LCDC_FRMP1) DMA Frame Pointer Register 1
+#define LCDC_FRMP2 (AT91_CAST(AT91_REG *) 0x0000000C) // (LCDC_FRMP2) DMA Frame Pointer Register 2
+#define LCDC_FRMA1 (AT91_CAST(AT91_REG *) 0x00000010) // (LCDC_FRMA1) DMA Frame Address Register 1
+#define LCDC_FRMA2 (AT91_CAST(AT91_REG *) 0x00000014) // (LCDC_FRMA2) DMA Frame Address Register 2
+#define LCDC_FRMCFG (AT91_CAST(AT91_REG *) 0x00000018) // (LCDC_FRMCFG) DMA Frame Configuration Register
+#define LCDC_DMACON (AT91_CAST(AT91_REG *) 0x0000001C) // (LCDC_DMACON) DMA Control Register
+#define LCDC_DMA2DCFG (AT91_CAST(AT91_REG *) 0x00000020) // (LCDC_DMA2DCFG) DMA 2D addressing configuration
+#define LCDC_LCDCON1 (AT91_CAST(AT91_REG *) 0x00000800) // (LCDC_LCDCON1) LCD Control 1 Register
+#define LCDC_LCDCON2 (AT91_CAST(AT91_REG *) 0x00000804) // (LCDC_LCDCON2) LCD Control 2 Register
+#define LCDC_TIM1 (AT91_CAST(AT91_REG *) 0x00000808) // (LCDC_TIM1) LCD Timing Config 1 Register
+#define LCDC_TIM2 (AT91_CAST(AT91_REG *) 0x0000080C) // (LCDC_TIM2) LCD Timing Config 2 Register
+#define LCDC_LCDFRCFG (AT91_CAST(AT91_REG *) 0x00000810) // (LCDC_LCDFRCFG) LCD Frame Config Register
+#define LCDC_FIFO (AT91_CAST(AT91_REG *) 0x00000814) // (LCDC_FIFO) LCD FIFO Register
+#define LCDC_MVAL (AT91_CAST(AT91_REG *) 0x00000818) // (LCDC_MVAL) LCD Mode Toggle Rate Value Register
+#define LCDC_DP1_2 (AT91_CAST(AT91_REG *) 0x0000081C) // (LCDC_DP1_2) Dithering Pattern DP1_2 Register
+#define LCDC_DP4_7 (AT91_CAST(AT91_REG *) 0x00000820) // (LCDC_DP4_7) Dithering Pattern DP4_7 Register
+#define LCDC_DP3_5 (AT91_CAST(AT91_REG *) 0x00000824) // (LCDC_DP3_5) Dithering Pattern DP3_5 Register
+#define LCDC_DP2_3 (AT91_CAST(AT91_REG *) 0x00000828) // (LCDC_DP2_3) Dithering Pattern DP2_3 Register
+#define LCDC_DP5_7 (AT91_CAST(AT91_REG *) 0x0000082C) // (LCDC_DP5_7) Dithering Pattern DP5_7 Register
+#define LCDC_DP3_4 (AT91_CAST(AT91_REG *) 0x00000830) // (LCDC_DP3_4) Dithering Pattern DP3_4 Register
+#define LCDC_DP4_5 (AT91_CAST(AT91_REG *) 0x00000834) // (LCDC_DP4_5) Dithering Pattern DP4_5 Register
+#define LCDC_DP6_7 (AT91_CAST(AT91_REG *) 0x00000838) // (LCDC_DP6_7) Dithering Pattern DP6_7 Register
+#define LCDC_PWRCON (AT91_CAST(AT91_REG *) 0x0000083C) // (LCDC_PWRCON) Power Control Register
+#define LCDC_CTRSTCON (AT91_CAST(AT91_REG *) 0x00000840) // (LCDC_CTRSTCON) Contrast Control Register
+#define LCDC_CTRSTVAL (AT91_CAST(AT91_REG *) 0x00000844) // (LCDC_CTRSTVAL) Contrast Value Register
+#define LCDC_IER (AT91_CAST(AT91_REG *) 0x00000848) // (LCDC_IER) Interrupt Enable Register
+#define LCDC_IDR (AT91_CAST(AT91_REG *) 0x0000084C) // (LCDC_IDR) Interrupt Disable Register
+#define LCDC_IMR (AT91_CAST(AT91_REG *) 0x00000850) // (LCDC_IMR) Interrupt Mask Register
+#define LCDC_ISR (AT91_CAST(AT91_REG *) 0x00000854) // (LCDC_ISR) Interrupt Enable Register
+#define LCDC_ICR (AT91_CAST(AT91_REG *) 0x00000858) // (LCDC_ICR) Interrupt Clear Register
+#define LCDC_GPR (AT91_CAST(AT91_REG *) 0x0000085C) // (LCDC_GPR) General Purpose Register
+#define LCDC_ITR (AT91_CAST(AT91_REG *) 0x00000860) // (LCDC_ITR) Interrupts Test Register
+#define LCDC_IRR (AT91_CAST(AT91_REG *) 0x00000864) // (LCDC_IRR) Interrupts Raw Status Register
+#define LCDC_LUT_ENTRY (AT91_CAST(AT91_REG *) 0x00000C00) // (LCDC_LUT_ENTRY) LUT Entries Register
+
+#endif
+// -------- LCDC_FRMP1 : (LCDC Offset: 0x8) DMA Frame Pointer 1 Register --------
+#define AT91C_LCDC_FRMPT1 (0x3FFFFF << 0) // (LCDC) Frame Pointer Address 1
+// -------- LCDC_FRMP2 : (LCDC Offset: 0xc) DMA Frame Pointer 2 Register --------
+#define AT91C_LCDC_FRMPT2 (0x1FFFFF << 0) // (LCDC) Frame Pointer Address 2
+// -------- LCDC_FRMCFG : (LCDC Offset: 0x18) DMA Frame Config Register --------
+#define AT91C_LCDC_FRSIZE (0x7FFFFF << 0) // (LCDC) FRAME SIZE
+#define AT91C_LCDC_BLENGTH (0x7F << 24) // (LCDC) BURST LENGTH
+// -------- LCDC_DMACON : (LCDC Offset: 0x1c) DMA Control Register --------
+#define AT91C_LCDC_DMAEN (0x1 << 0) // (LCDC) DAM Enable
+#define AT91C_LCDC_DMARST (0x1 << 1) // (LCDC) DMA Reset (WO)
+#define AT91C_LCDC_DMABUSY (0x1 << 2) // (LCDC) DMA Reset (WO)
+#define AT91C_LCDC_DMAUPDT (0x1 << 3) // (LCDC) DMA Configuration Update
+#define AT91C_LCDC_DMA2DEN (0x1 << 4) // (LCDC) 2D Addressing Enable
+// -------- LCDC_DMA2DCFG : (LCDC Offset: 0x20) DMA 2D addressing configuration Register --------
+#define AT91C_LCDC_ADDRINC (0xFFFF << 0) // (LCDC) Number of 32b words that the DMA must jump when going to the next line
+#define AT91C_LCDC_PIXELOFF (0x1F << 24) // (LCDC) Offset (in bits) of the first pixel of the screen in the memory word which contain it
+// -------- LCDC_LCDCON1 : (LCDC Offset: 0x800) LCD Control 1 Register --------
+#define AT91C_LCDC_BYPASS (0x1 << 0) // (LCDC) Bypass lcd_pccklk divider
+#define AT91C_LCDC_CLKVAL (0x1FF << 12) // (LCDC) 9-bit Divider for pixel clock frequency
+#define AT91C_LCDC_LINCNT (0x7FF << 21) // (LCDC) Line Counter (RO)
+// -------- LCDC_LCDCON2 : (LCDC Offset: 0x804) LCD Control 2 Register --------
+#define AT91C_LCDC_DISTYPE (0x3 << 0) // (LCDC) Display Type
+#define AT91C_LCDC_DISTYPE_STNMONO (0x0) // (LCDC) STN Mono
+#define AT91C_LCDC_DISTYPE_STNCOLOR (0x1) // (LCDC) STN Color
+#define AT91C_LCDC_DISTYPE_TFT (0x2) // (LCDC) TFT
+#define AT91C_LCDC_SCANMOD (0x1 << 2) // (LCDC) Scan Mode
+#define AT91C_LCDC_SCANMOD_SINGLESCAN (0x0 << 2) // (LCDC) Single Scan
+#define AT91C_LCDC_SCANMOD_DUALSCAN (0x1 << 2) // (LCDC) Dual Scan
+#define AT91C_LCDC_IFWIDTH (0x3 << 3) // (LCDC) Interface Width
+#define AT91C_LCDC_IFWIDTH_FOURBITSWIDTH (0x0 << 3) // (LCDC) 4 Bits
+#define AT91C_LCDC_IFWIDTH_EIGTHBITSWIDTH (0x1 << 3) // (LCDC) 8 Bits
+#define AT91C_LCDC_IFWIDTH_SIXTEENBITSWIDTH (0x2 << 3) // (LCDC) 16 Bits
+#define AT91C_LCDC_PIXELSIZE (0x7 << 5) // (LCDC) Bits per pixel
+#define AT91C_LCDC_PIXELSIZE_ONEBITSPERPIXEL (0x0 << 5) // (LCDC) 1 Bits
+#define AT91C_LCDC_PIXELSIZE_TWOBITSPERPIXEL (0x1 << 5) // (LCDC) 2 Bits
+#define AT91C_LCDC_PIXELSIZE_FOURBITSPERPIXEL (0x2 << 5) // (LCDC) 4 Bits
+#define AT91C_LCDC_PIXELSIZE_EIGTHBITSPERPIXEL (0x3 << 5) // (LCDC) 8 Bits
+#define AT91C_LCDC_PIXELSIZE_SIXTEENBITSPERPIXEL (0x4 << 5) // (LCDC) 16 Bits
+#define AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL (0x5 << 5) // (LCDC) 24 Bits
+#define AT91C_LCDC_INVVD (0x1 << 8) // (LCDC) lcd datas polarity
+#define AT91C_LCDC_INVVD_NORMALPOL (0x0 << 8) // (LCDC) Normal Polarity
+#define AT91C_LCDC_INVVD_INVERTEDPOL (0x1 << 8) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVFRAME (0x1 << 9) // (LCDC) lcd vsync polarity
+#define AT91C_LCDC_INVFRAME_NORMALPOL (0x0 << 9) // (LCDC) Normal Polarity
+#define AT91C_LCDC_INVFRAME_INVERTEDPOL (0x1 << 9) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVLINE (0x1 << 10) // (LCDC) lcd hsync polarity
+#define AT91C_LCDC_INVLINE_NORMALPOL (0x0 << 10) // (LCDC) Normal Polarity
+#define AT91C_LCDC_INVLINE_INVERTEDPOL (0x1 << 10) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVCLK (0x1 << 11) // (LCDC) lcd pclk polarity
+#define AT91C_LCDC_INVCLK_NORMALPOL (0x0 << 11) // (LCDC) Normal Polarity
+#define AT91C_LCDC_INVCLK_INVERTEDPOL (0x1 << 11) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_INVDVAL (0x1 << 12) // (LCDC) lcd dval polarity
+#define AT91C_LCDC_INVDVAL_NORMALPOL (0x0 << 12) // (LCDC) Normal Polarity
+#define AT91C_LCDC_INVDVAL_INVERTEDPOL (0x1 << 12) // (LCDC) Inverted Polarity
+#define AT91C_LCDC_CLKMOD (0x1 << 15) // (LCDC) lcd pclk Mode
+#define AT91C_LCDC_CLKMOD_ACTIVEONLYDISP (0x0 << 15) // (LCDC) Active during display period
+#define AT91C_LCDC_CLKMOD_ALWAYSACTIVE (0x1 << 15) // (LCDC) Always Active
+#define AT91C_LCDC_MEMOR (0x3 << 30) // (LCDC) Memory Ordering Format
+#define AT91C_LCDC_MEMOR_BIGIND (0x0 << 30) // (LCDC) Big Endian
+#define AT91C_LCDC_MEMOR_LITTLEIND (0x2 << 30) // (LCDC) Little Endian
+// -------- LCDC_TIM1 : (LCDC Offset: 0x808) LCDC Timing Config 1 Register --------
+#define AT91C_LCDC_VFP (0xFF << 0) // (LCDC) Vertical Front Porch
+#define AT91C_LCDC_VBP (0xFF << 8) // (LCDC) Vertical Back Porch
+#define AT91C_LCDC_VPW (0x3F << 16) // (LCDC) Vertical Synchronization Pulse Width
+#define AT91C_LCDC_VHDLY (0xF << 24) // (LCDC) Vertical to Horizontal Delay
+// -------- LCDC_TIM2 : (LCDC Offset: 0x80c) LCDC Timing Config 2 Register --------
+#define AT91C_LCDC_HBP (0xFF << 0) // (LCDC) Horizontal Back Porch
+#define AT91C_LCDC_HPW (0x3F << 8) // (LCDC) Horizontal Synchronization Pulse Width
+#define AT91C_LCDC_HFP (0x7FF << 21) // (LCDC) Horizontal Front Porch
+// -------- LCDC_LCDFRCFG : (LCDC Offset: 0x810) LCD Frame Config Register --------
+#define AT91C_LCDC_LINEVAL (0x7FF << 0) // (LCDC) Vertical Size of LCD Module
+#define AT91C_LCDC_HOZVAL (0x7FF << 21) // (LCDC) Horizontal Size of LCD Module
+// -------- LCDC_FIFO : (LCDC Offset: 0x814) LCD FIFO Register --------
+#define AT91C_LCDC_FIFOTH (0xFFFF << 0) // (LCDC) FIFO Threshold
+// -------- LCDC_MVAL : (LCDC Offset: 0x818) LCD Mode Toggle Rate Value Register --------
+#define AT91C_LCDC_MVALUE (0xFF << 0) // (LCDC) Toggle Rate Value
+#define AT91C_LCDC_MMODE (0x1 << 31) // (LCDC) Toggle Rate Sel
+#define AT91C_LCDC_MMODE_EACHFRAME (0x0 << 31) // (LCDC) Each Frame
+#define AT91C_LCDC_MMODE_MVALDEFINED (0x1 << 31) // (LCDC) Defined by MVAL
+// -------- LCDC_DP1_2 : (LCDC Offset: 0x81c) Dithering Pattern 1/2 --------
+#define AT91C_LCDC_DP1_2_FIELD (0xFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP4_7 : (LCDC Offset: 0x820) Dithering Pattern 4/7 --------
+#define AT91C_LCDC_DP4_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP3_5 : (LCDC Offset: 0x824) Dithering Pattern 3/5 --------
+#define AT91C_LCDC_DP3_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP2_3 : (LCDC Offset: 0x828) Dithering Pattern 2/3 --------
+#define AT91C_LCDC_DP2_3_FIELD (0xFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP5_7 : (LCDC Offset: 0x82c) Dithering Pattern 5/7 --------
+#define AT91C_LCDC_DP5_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP3_4 : (LCDC Offset: 0x830) Dithering Pattern 3/4 --------
+#define AT91C_LCDC_DP3_4_FIELD (0xFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP4_5 : (LCDC Offset: 0x834) Dithering Pattern 4/5 --------
+#define AT91C_LCDC_DP4_5_FIELD (0xFFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_DP6_7 : (LCDC Offset: 0x838) Dithering Pattern 6/7 --------
+#define AT91C_LCDC_DP6_7_FIELD (0xFFFFFFF << 0) // (LCDC) Ratio
+// -------- LCDC_PWRCON : (LCDC Offset: 0x83c) LCDC Power Control Register --------
+#define AT91C_LCDC_PWR (0x1 << 0) // (LCDC) LCD Module Power Control
+#define AT91C_LCDC_GUARDT (0x7F << 1) // (LCDC) Delay in Frame Period
+#define AT91C_LCDC_BUSY (0x1 << 31) // (LCDC) Read Only : 1 indicates that LCDC is busy
+#define AT91C_LCDC_BUSY_LCDNOTBUSY (0x0 << 31) // (LCDC) LCD is Not Busy
+#define AT91C_LCDC_BUSY_LCDBUSY (0x1 << 31) // (LCDC) LCD is Busy
+// -------- LCDC_CTRSTCON : (LCDC Offset: 0x840) LCDC Contrast Control Register --------
+#define AT91C_LCDC_PS (0x3 << 0) // (LCDC) LCD Contrast Counter Prescaler
+#define AT91C_LCDC_PS_NOTDIVIDED (0x0) // (LCDC) Counter Freq is System Freq.
+#define AT91C_LCDC_PS_DIVIDEDBYTWO (0x1) // (LCDC) Counter Freq is System Freq divided by 2.
+#define AT91C_LCDC_PS_DIVIDEDBYFOUR (0x2) // (LCDC) Counter Freq is System Freq divided by 4.
+#define AT91C_LCDC_PS_DIVIDEDBYEIGHT (0x3) // (LCDC) Counter Freq is System Freq divided by 8.
+#define AT91C_LCDC_POL (0x1 << 2) // (LCDC) Polarity of output Pulse
+#define AT91C_LCDC_POL_NEGATIVEPULSE (0x0 << 2) // (LCDC) Negative Pulse
+#define AT91C_LCDC_POL_POSITIVEPULSE (0x1 << 2) // (LCDC) Positive Pulse
+#define AT91C_LCDC_ENA (0x1 << 3) // (LCDC) PWM generator Control
+#define AT91C_LCDC_ENA_PWMGEMDISABLED (0x0 << 3) // (LCDC) PWM Generator Disabled
+#define AT91C_LCDC_ENA_PWMGEMENABLED (0x1 << 3) // (LCDC) PWM Generator Disabled
+// -------- LCDC_CTRSTVAL : (LCDC Offset: 0x844) Contrast Value Register --------
+#define AT91C_LCDC_CVAL (0xFF << 0) // (LCDC) PWM Compare Value
+// -------- LCDC_IER : (LCDC Offset: 0x848) LCDC Interrupt Enable Register --------
+#define AT91C_LCDC_LNI (0x1 << 0) // (LCDC) Line Interrupt
+#define AT91C_LCDC_LSTLNI (0x1 << 1) // (LCDC) Last Line Interrupt
+#define AT91C_LCDC_EOFI (0x1 << 2) // (LCDC) End Of Frame Interrupt
+#define AT91C_LCDC_UFLWI (0x1 << 4) // (LCDC) FIFO Underflow Interrupt
+#define AT91C_LCDC_OWRI (0x1 << 5) // (LCDC) Over Write Interrupt
+#define AT91C_LCDC_MERI (0x1 << 6) // (LCDC) Memory Error Interrupt
+// -------- LCDC_IDR : (LCDC Offset: 0x84c) LCDC Interrupt Disable Register --------
+// -------- LCDC_IMR : (LCDC Offset: 0x850) LCDC Interrupt Mask Register --------
+// -------- LCDC_ISR : (LCDC Offset: 0x854) LCDC Interrupt Status Register --------
+// -------- LCDC_ICR : (LCDC Offset: 0x858) LCDC Interrupt Clear Register --------
+// -------- LCDC_GPR : (LCDC Offset: 0x85c) LCDC General Purpose Register --------
+#define AT91C_LCDC_GPRBUS (0xFF << 0) // (LCDC) 8 bits available
+// -------- LCDC_ITR : (LCDC Offset: 0x860) Interrupts Test Register --------
+// -------- LCDC_IRR : (LCDC Offset: 0x864) Interrupts Raw Status Register --------
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91SAM9G10
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ==========
+#define AT91C_SYS_GPBR1 (AT91_CAST(AT91_REG *) 0xFFFFFD54) // (SYS) General Purpose Register 1
+#define AT91C_SYS_GPBR3 (AT91_CAST(AT91_REG *) 0xFFFFFD5C) // (SYS) General Purpose Register 3
+#define AT91C_SYS_GPBR2 (AT91_CAST(AT91_REG *) 0xFFFFFD58) // (SYS) General Purpose Register 2
+#define AT91C_SYS_GPBR0 (AT91_CAST(AT91_REG *) 0xFFFFFD50) // (SYS) General Purpose Register 0
+// ========== Register definition for SDRAMC peripheral ==========
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
+// ========== Register definition for SMC peripheral ==========
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3
+// ========== Register definition for MATRIX peripheral ==========
+#define AT91C_MATRIX_USBPCR (AT91_CAST(AT91_REG *) 0xFFFFEE34) // (MATRIX) Slave 4 Special Function Register
+#define AT91C_MATRIX_MCFG (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register
+#define AT91C_MATRIX_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEE30) // (MATRIX) Slave 3 Special Function Register
+#define AT91C_MATRIX_SCFG2 (AT91_CAST(AT91_REG *) 0xFFFFEE0C) // (MATRIX) Slave Configuration Register 2
+#define AT91C_MATRIX_VERSION (AT91_CAST(AT91_REG *) 0xFFFFEE44) // (MATRIX) Version Register
+#define AT91C_MATRIX_SCFG3 (AT91_CAST(AT91_REG *) 0xFFFFEE10) // (MATRIX) Slave Configuration Register 3
+#define AT91C_MATRIX_TCMR (AT91_CAST(AT91_REG *) 0xFFFFEE24) // (MATRIX) Slave 0 Special Function Register
+#define AT91C_MATRIX_SCFG1 (AT91_CAST(AT91_REG *) 0xFFFFEE08) // (MATRIX) Slave Configuration Register 1
+#define AT91C_MATRIX_SCFG4 (AT91_CAST(AT91_REG *) 0xFFFFEE14) // (MATRIX) Slave Configuration Register 4
+#define AT91C_MATRIX_SCFG0 (AT91_CAST(AT91_REG *) 0xFFFFEE04) // (MATRIX) Slave Configuration Register 0
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for PIOC peripheral ==========
+#define AT91C_PIOC_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF8A4) // (PIOC) Output Write Disable Register
+#define AT91C_PIOC_SODR (AT91_CAST(AT91_REG *) 0xFFFFF830) // (PIOC) Set Output Data Register
+#define AT91C_PIOC_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF864) // (PIOC) Pull-up Enable Register
+#define AT91C_PIOC_CODR (AT91_CAST(AT91_REG *) 0xFFFFF834) // (PIOC) Clear Output Data Register
+#define AT91C_PIOC_PSR (AT91_CAST(AT91_REG *) 0xFFFFF808) // (PIOC) PIO Status Register
+#define AT91C_PIOC_PDR (AT91_CAST(AT91_REG *) 0xFFFFF804) // (PIOC) PIO Disable Register
+#define AT91C_PIOC_ODR (AT91_CAST(AT91_REG *) 0xFFFFF814) // (PIOC) Output Disable Registerr
+#define AT91C_PIOC_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF868) // (PIOC) Pull-up Status Register
+#define AT91C_PIOC_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF878) // (PIOC) AB Select Status Register
+#define AT91C_PIOC_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF828) // (PIOC) Input Filter Status Register
+#define AT91C_PIOC_OER (AT91_CAST(AT91_REG *) 0xFFFFF810) // (PIOC) Output Enable Register
+#define AT91C_PIOC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF848) // (PIOC) Interrupt Mask Register
+#define AT91C_PIOC_ASR (AT91_CAST(AT91_REG *) 0xFFFFF870) // (PIOC) Select A Register
+#define AT91C_PIOC_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF854) // (PIOC) Multi-driver Disable Register
+#define AT91C_PIOC_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF8A8) // (PIOC) Output Write Status Register
+#define AT91C_PIOC_PER (AT91_CAST(AT91_REG *) 0xFFFFF800) // (PIOC) PIO Enable Register
+#define AT91C_PIOC_IDR (AT91_CAST(AT91_REG *) 0xFFFFF844) // (PIOC) Interrupt Disable Register
+#define AT91C_PIOC_MDER (AT91_CAST(AT91_REG *) 0xFFFFF850) // (PIOC) Multi-driver Enable Register
+#define AT91C_PIOC_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF83C) // (PIOC) Pin Data Status Register
+#define AT91C_PIOC_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF858) // (PIOC) Multi-driver Status Register
+#define AT91C_PIOC_OWER (AT91_CAST(AT91_REG *) 0xFFFFF8A0) // (PIOC) Output Write Enable Register
+#define AT91C_PIOC_BSR (AT91_CAST(AT91_REG *) 0xFFFFF874) // (PIOC) Select B Register
+#define AT91C_PIOC_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF860) // (PIOC) Pull-up Disable Register
+#define AT91C_PIOC_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF824) // (PIOC) Input Filter Disable Register
+#define AT91C_PIOC_IER (AT91_CAST(AT91_REG *) 0xFFFFF840) // (PIOC) Interrupt Enable Register
+#define AT91C_PIOC_OSR (AT91_CAST(AT91_REG *) 0xFFFFF818) // (PIOC) Output Status Register
+#define AT91C_PIOC_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF838) // (PIOC) Output Data Status Register
+#define AT91C_PIOC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF84C) // (PIOC) Interrupt Status Register
+#define AT91C_PIOC_IFER (AT91_CAST(AT91_REG *) 0xFFFFF820) // (PIOC) Input Filter Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
+#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_VER (AT91_CAST(AT91_REG *) 0xFFFFFDFC) // (RSTC) Version Register
+#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ==========
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB0 peripheral ==========
+#define AT91C_TCB0_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFA00EC) // (TCB0) TC ADDRSIZE REGISTER
+#define AT91C_TCB0_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB0) TC Block Mode Register
+#define AT91C_TCB0_VER (AT91_CAST(AT91_REG *) 0xFFFA00FC) // (TCB0) Version Register
+#define AT91C_TCB0_FEATURES (AT91_CAST(AT91_REG *) 0xFFFA00F8) // (TCB0) TC FEATURES REGISTER
+#define AT91C_TCB0_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFA00F0) // (TCB0) TC IPNAME1 REGISTER
+#define AT91C_TCB0_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB0) TC Block Control Register
+#define AT91C_TCB0_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFA00F4) // (TCB0) TC IPNAME2 REGISTER
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register
+#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register
+#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register
+// ========== Register definition for PDC_MCI peripheral ==========
+#define AT91C_MCI_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_MCI) Receive Next Counter Register
+#define AT91C_MCI_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_MCI) Transmit Counter Register
+#define AT91C_MCI_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_MCI) Receive Counter Register
+#define AT91C_MCI_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_MCI) Transmit Next Pointer Register
+#define AT91C_MCI_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_MCI) Receive Next Pointer Register
+#define AT91C_MCI_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_MCI) Receive Pointer Register
+#define AT91C_MCI_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_MCI) Transmit Next Counter Register
+#define AT91C_MCI_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_MCI) Transmit Pointer Register
+#define AT91C_MCI_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_MCI) PDC Transfer Status Register
+#define AT91C_MCI_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_MCI) PDC Transfer Control Register
+// ========== Register definition for MCI peripheral ==========
+#define AT91C_MCI_RDR (AT91_CAST(AT91_REG *) 0xFFFA8030) // (MCI) MCI Receive Data Register
+#define AT91C_MCI_CMDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (MCI) MCI Command Register
+#define AT91C_MCI_IDR (AT91_CAST(AT91_REG *) 0xFFFA8048) // (MCI) MCI Interrupt Disable Register
+#define AT91C_MCI_TDR (AT91_CAST(AT91_REG *) 0xFFFA8034) // (MCI) MCI Transmit Data Register
+#define AT91C_MCI_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFA80F4) // (MCI) MCI IPNAME2 REGISTER
+#define AT91C_MCI_WPCR (AT91_CAST(AT91_REG *) 0xFFFA80E4) // (MCI) MCI Write Protection Control Register
+#define AT91C_MCI_CFG (AT91_CAST(AT91_REG *) 0xFFFA8054) // (MCI) MCI Configuration Register
+#define AT91C_MCI_DMA (AT91_CAST(AT91_REG *) 0xFFFA8050) // (MCI) MCI DMA Configuration Register
+#define AT91C_MCI_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (MCI) MCI Mode Register
+#define AT91C_MCI_ARGR (AT91_CAST(AT91_REG *) 0xFFFA8010) // (MCI) MCI Argument Register
+#define AT91C_MCI_SDCR (AT91_CAST(AT91_REG *) 0xFFFA800C) // (MCI) MCI SD/SDIO Card Register
+#define AT91C_MCI_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFA80F0) // (MCI) MCI IPNAME1 REGISTER
+#define AT91C_MCI_DTOR (AT91_CAST(AT91_REG *) 0xFFFA8008) // (MCI) MCI Data Timeout Register
+#define AT91C_MCI_FEATURES (AT91_CAST(AT91_REG *) 0xFFFA80F8) // (MCI) MCI FEATURES REGISTER
+#define AT91C_MCI_BLKR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (MCI) MCI Block Register
+#define AT91C_MCI_IER (AT91_CAST(AT91_REG *) 0xFFFA8044) // (MCI) MCI Interrupt Enable Register
+#define AT91C_MCI_FIFO (AT91_CAST(AT91_REG *) 0xFFFA8200) // (MCI) MCI FIFO Aperture Register
+#define AT91C_MCI_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (MCI) MCI Control Register
+#define AT91C_MCI_IMR (AT91_CAST(AT91_REG *) 0xFFFA804C) // (MCI) MCI Interrupt Mask Register
+#define AT91C_MCI_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFA80EC) // (MCI) MCI ADDRSIZE REGISTER
+#define AT91C_MCI_WPSR (AT91_CAST(AT91_REG *) 0xFFFA80E8) // (MCI) MCI Write Protection Status Register
+#define AT91C_MCI_CSTOR (AT91_CAST(AT91_REG *) 0xFFFA801C) // (MCI) MCI Completion Signal Timeout Register
+#define AT91C_MCI_SR (AT91_CAST(AT91_REG *) 0xFFFA8040) // (MCI) MCI Status Register
+#define AT91C_MCI_RSPR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (MCI) MCI Response Register
+// ========== Register definition for TWI peripheral ==========
+#define AT91C_TWI_CWGR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_IER (AT91_CAST(AT91_REG *) 0xFFFAC024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_MMR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (TWI) Master Mode Register
+#define AT91C_TWI_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFAC0F0) // (TWI) TWI IPNAME1 REGISTER
+#define AT91C_TWI_IMR (AT91_CAST(AT91_REG *) 0xFFFAC02C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_FEATURES (AT91_CAST(AT91_REG *) 0xFFFAC0F8) // (TWI) TWI FEATURES REGISTER
+#define AT91C_TWI_THR (AT91_CAST(AT91_REG *) 0xFFFAC034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR (AT91_CAST(AT91_REG *) 0xFFFAC028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SMR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (TWI) Slave Mode Register
+#define AT91C_TWI_IADR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (TWI) Internal Address Register
+#define AT91C_TWI_RHR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (TWI) Receive Holding Register
+#define AT91C_TWI_SR (AT91_CAST(AT91_REG *) 0xFFFAC020) // (TWI) Status Register
+#define AT91C_TWI_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (TWI) Control Register
+#define AT91C_TWI_VER (AT91_CAST(AT91_REG *) 0xFFFAC0FC) // (TWI) Version Register
+#define AT91C_TWI_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFAC0F4) // (TWI) TWI IPNAME2 REGISTER
+#define AT91C_TWI_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFAC0EC) // (TWI) TWI ADDRSIZE REGISTER
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register
+#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register
+#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register
+#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register
+#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register
+#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register
+#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register
+#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register
+#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register
+// ========== Register definition for PDC_US2 peripheral ==========
+#define AT91C_US2_TNCR (AT91_CAST(AT91_REG *) 0xFFFB811C) // (PDC_US2) Transmit Next Counter Register
+#define AT91C_US2_RNCR (AT91_CAST(AT91_REG *) 0xFFFB8114) // (PDC_US2) Receive Next Counter Register
+#define AT91C_US2_TNPR (AT91_CAST(AT91_REG *) 0xFFFB8118) // (PDC_US2) Transmit Next Pointer Register
+#define AT91C_US2_PTCR (AT91_CAST(AT91_REG *) 0xFFFB8120) // (PDC_US2) PDC Transfer Control Register
+#define AT91C_US2_TCR (AT91_CAST(AT91_REG *) 0xFFFB810C) // (PDC_US2) Transmit Counter Register
+#define AT91C_US2_RPR (AT91_CAST(AT91_REG *) 0xFFFB8100) // (PDC_US2) Receive Pointer Register
+#define AT91C_US2_TPR (AT91_CAST(AT91_REG *) 0xFFFB8108) // (PDC_US2) Transmit Pointer Register
+#define AT91C_US2_RCR (AT91_CAST(AT91_REG *) 0xFFFB8104) // (PDC_US2) Receive Counter Register
+#define AT91C_US2_PTSR (AT91_CAST(AT91_REG *) 0xFFFB8124) // (PDC_US2) PDC Transfer Status Register
+#define AT91C_US2_RNPR (AT91_CAST(AT91_REG *) 0xFFFB8110) // (PDC_US2) Receive Next Pointer Register
+// ========== Register definition for US2 peripheral ==========
+#define AT91C_US2_RTOR (AT91_CAST(AT91_REG *) 0xFFFB8024) // (US2) Receiver Time-out Register
+#define AT91C_US2_CSR (AT91_CAST(AT91_REG *) 0xFFFB8014) // (US2) Channel Status Register
+#define AT91C_US2_CR (AT91_CAST(AT91_REG *) 0xFFFB8000) // (US2) Control Register
+#define AT91C_US2_BRGR (AT91_CAST(AT91_REG *) 0xFFFB8020) // (US2) Baud Rate Generator Register
+#define AT91C_US2_NER (AT91_CAST(AT91_REG *) 0xFFFB8044) // (US2) Nb Errors Register
+#define AT91C_US2_FIDI (AT91_CAST(AT91_REG *) 0xFFFB8040) // (US2) FI_DI_Ratio Register
+#define AT91C_US2_TTGR (AT91_CAST(AT91_REG *) 0xFFFB8028) // (US2) Transmitter Time-guard Register
+#define AT91C_US2_RHR (AT91_CAST(AT91_REG *) 0xFFFB8018) // (US2) Receiver Holding Register
+#define AT91C_US2_IDR (AT91_CAST(AT91_REG *) 0xFFFB800C) // (US2) Interrupt Disable Register
+#define AT91C_US2_THR (AT91_CAST(AT91_REG *) 0xFFFB801C) // (US2) Transmitter Holding Register
+#define AT91C_US2_MR (AT91_CAST(AT91_REG *) 0xFFFB8004) // (US2) Mode Register
+#define AT91C_US2_IMR (AT91_CAST(AT91_REG *) 0xFFFB8010) // (US2) Interrupt Mask Register
+#define AT91C_US2_IF (AT91_CAST(AT91_REG *) 0xFFFB804C) // (US2) IRDA_FILTER Register
+#define AT91C_US2_IER (AT91_CAST(AT91_REG *) 0xFFFB8008) // (US2) Interrupt Enable Register
+// ========== Register definition for PDC_SSC0 peripheral ==========
+#define AT91C_SSC0_TNPR (AT91_CAST(AT91_REG *) 0xFFFBC118) // (PDC_SSC0) Transmit Next Pointer Register
+#define AT91C_SSC0_TCR (AT91_CAST(AT91_REG *) 0xFFFBC10C) // (PDC_SSC0) Transmit Counter Register
+#define AT91C_SSC0_RNCR (AT91_CAST(AT91_REG *) 0xFFFBC114) // (PDC_SSC0) Receive Next Counter Register
+#define AT91C_SSC0_RPR (AT91_CAST(AT91_REG *) 0xFFFBC100) // (PDC_SSC0) Receive Pointer Register
+#define AT91C_SSC0_TPR (AT91_CAST(AT91_REG *) 0xFFFBC108) // (PDC_SSC0) Transmit Pointer Register
+#define AT91C_SSC0_RCR (AT91_CAST(AT91_REG *) 0xFFFBC104) // (PDC_SSC0) Receive Counter Register
+#define AT91C_SSC0_RNPR (AT91_CAST(AT91_REG *) 0xFFFBC110) // (PDC_SSC0) Receive Next Pointer Register
+#define AT91C_SSC0_PTCR (AT91_CAST(AT91_REG *) 0xFFFBC120) // (PDC_SSC0) PDC Transfer Control Register
+#define AT91C_SSC0_TNCR (AT91_CAST(AT91_REG *) 0xFFFBC11C) // (PDC_SSC0) Transmit Next Counter Register
+#define AT91C_SSC0_PTSR (AT91_CAST(AT91_REG *) 0xFFFBC124) // (PDC_SSC0) PDC Transfer Status Register
+// ========== Register definition for SSC0 peripheral ==========
+#define AT91C_SSC0_CR (AT91_CAST(AT91_REG *) 0xFFFBC000) // (SSC0) Control Register
+#define AT91C_SSC0_CMR (AT91_CAST(AT91_REG *) 0xFFFBC004) // (SSC0) Clock Mode Register
+#define AT91C_SSC0_IER (AT91_CAST(AT91_REG *) 0xFFFBC044) // (SSC0) Interrupt Enable Register
+#define AT91C_SSC0_FEATURES (AT91_CAST(AT91_REG *) 0xFFFBC0F8) // (SSC0) SSC FEATURES REGISTER
+#define AT91C_SSC0_RSHR (AT91_CAST(AT91_REG *) 0xFFFBC030) // (SSC0) Receive Sync Holding Register
+#define AT91C_SSC0_THR (AT91_CAST(AT91_REG *) 0xFFFBC024) // (SSC0) Transmit Holding Register
+#define AT91C_SSC0_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFBC0EC) // (SSC0) SSC ADDRSIZE REGISTER
+#define AT91C_SSC0_TSHR (AT91_CAST(AT91_REG *) 0xFFFBC034) // (SSC0) Transmit Sync Holding Register
+#define AT91C_SSC0_RFMR (AT91_CAST(AT91_REG *) 0xFFFBC014) // (SSC0) Receive Frame Mode Register
+#define AT91C_SSC0_IMR (AT91_CAST(AT91_REG *) 0xFFFBC04C) // (SSC0) Interrupt Mask Register
+#define AT91C_SSC0_TFMR (AT91_CAST(AT91_REG *) 0xFFFBC01C) // (SSC0) Transmit Frame Mode Register
+#define AT91C_SSC0_RHR (AT91_CAST(AT91_REG *) 0xFFFBC020) // (SSC0) Receive Holding Register
+#define AT91C_SSC0_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFBC0F0) // (SSC0) SSC IPNAME1 REGISTER
+#define AT91C_SSC0_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFBC0F4) // (SSC0) SSC IPNAME2 REGISTER
+#define AT91C_SSC0_RCMR (AT91_CAST(AT91_REG *) 0xFFFBC010) // (SSC0) Receive Clock ModeRegister
+#define AT91C_SSC0_SR (AT91_CAST(AT91_REG *) 0xFFFBC040) // (SSC0) Status Register
+#define AT91C_SSC0_TCMR (AT91_CAST(AT91_REG *) 0xFFFBC018) // (SSC0) Transmit Clock Mode Register
+#define AT91C_SSC0_VER (AT91_CAST(AT91_REG *) 0xFFFBC0FC) // (SSC0) Version Register
+#define AT91C_SSC0_IDR (AT91_CAST(AT91_REG *) 0xFFFBC048) // (SSC0) Interrupt Disable Register
+// ========== Register definition for PDC_SSC1 peripheral ==========
+#define AT91C_SSC1_TNPR (AT91_CAST(AT91_REG *) 0xFFFC0118) // (PDC_SSC1) Transmit Next Pointer Register
+#define AT91C_SSC1_RNPR (AT91_CAST(AT91_REG *) 0xFFFC0110) // (PDC_SSC1) Receive Next Pointer Register
+#define AT91C_SSC1_TCR (AT91_CAST(AT91_REG *) 0xFFFC010C) // (PDC_SSC1) Transmit Counter Register
+#define AT91C_SSC1_PTCR (AT91_CAST(AT91_REG *) 0xFFFC0120) // (PDC_SSC1) PDC Transfer Control Register
+#define AT91C_SSC1_PTSR (AT91_CAST(AT91_REG *) 0xFFFC0124) // (PDC_SSC1) PDC Transfer Status Register
+#define AT91C_SSC1_TNCR (AT91_CAST(AT91_REG *) 0xFFFC011C) // (PDC_SSC1) Transmit Next Counter Register
+#define AT91C_SSC1_TPR (AT91_CAST(AT91_REG *) 0xFFFC0108) // (PDC_SSC1) Transmit Pointer Register
+#define AT91C_SSC1_RCR (AT91_CAST(AT91_REG *) 0xFFFC0104) // (PDC_SSC1) Receive Counter Register
+#define AT91C_SSC1_RPR (AT91_CAST(AT91_REG *) 0xFFFC0100) // (PDC_SSC1) Receive Pointer Register
+#define AT91C_SSC1_RNCR (AT91_CAST(AT91_REG *) 0xFFFC0114) // (PDC_SSC1) Receive Next Counter Register
+// ========== Register definition for SSC1 peripheral ==========
+#define AT91C_SSC1_IDR (AT91_CAST(AT91_REG *) 0xFFFC0048) // (SSC1) Interrupt Disable Register
+#define AT91C_SSC1_RCMR (AT91_CAST(AT91_REG *) 0xFFFC0010) // (SSC1) Receive Clock ModeRegister
+#define AT91C_SSC1_SR (AT91_CAST(AT91_REG *) 0xFFFC0040) // (SSC1) Status Register
+#define AT91C_SSC1_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFC00EC) // (SSC1) SSC ADDRSIZE REGISTER
+#define AT91C_SSC1_TSHR (AT91_CAST(AT91_REG *) 0xFFFC0034) // (SSC1) Transmit Sync Holding Register
+#define AT91C_SSC1_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFC00F4) // (SSC1) SSC IPNAME2 REGISTER
+#define AT91C_SSC1_THR (AT91_CAST(AT91_REG *) 0xFFFC0024) // (SSC1) Transmit Holding Register
+#define AT91C_SSC1_RFMR (AT91_CAST(AT91_REG *) 0xFFFC0014) // (SSC1) Receive Frame Mode Register
+#define AT91C_SSC1_VER (AT91_CAST(AT91_REG *) 0xFFFC00FC) // (SSC1) Version Register
+#define AT91C_SSC1_RHR (AT91_CAST(AT91_REG *) 0xFFFC0020) // (SSC1) Receive Holding Register
+#define AT91C_SSC1_CR (AT91_CAST(AT91_REG *) 0xFFFC0000) // (SSC1) Control Register
+#define AT91C_SSC1_IER (AT91_CAST(AT91_REG *) 0xFFFC0044) // (SSC1) Interrupt Enable Register
+#define AT91C_SSC1_CMR (AT91_CAST(AT91_REG *) 0xFFFC0004) // (SSC1) Clock Mode Register
+#define AT91C_SSC1_RSHR (AT91_CAST(AT91_REG *) 0xFFFC0030) // (SSC1) Receive Sync Holding Register
+#define AT91C_SSC1_TCMR (AT91_CAST(AT91_REG *) 0xFFFC0018) // (SSC1) Transmit Clock Mode Register
+#define AT91C_SSC1_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFC00F0) // (SSC1) SSC IPNAME1 REGISTER
+#define AT91C_SSC1_FEATURES (AT91_CAST(AT91_REG *) 0xFFFC00F8) // (SSC1) SSC FEATURES REGISTER
+#define AT91C_SSC1_TFMR (AT91_CAST(AT91_REG *) 0xFFFC001C) // (SSC1) Transmit Frame Mode Register
+#define AT91C_SSC1_IMR (AT91_CAST(AT91_REG *) 0xFFFC004C) // (SSC1) Interrupt Mask Register
+// ========== Register definition for PDC_SSC2 peripheral ==========
+#define AT91C_SSC2_RNCR (AT91_CAST(AT91_REG *) 0xFFFC4114) // (PDC_SSC2) Receive Next Counter Register
+#define AT91C_SSC2_PTCR (AT91_CAST(AT91_REG *) 0xFFFC4120) // (PDC_SSC2) PDC Transfer Control Register
+#define AT91C_SSC2_TCR (AT91_CAST(AT91_REG *) 0xFFFC410C) // (PDC_SSC2) Transmit Counter Register
+#define AT91C_SSC2_PTSR (AT91_CAST(AT91_REG *) 0xFFFC4124) // (PDC_SSC2) PDC Transfer Status Register
+#define AT91C_SSC2_TNPR (AT91_CAST(AT91_REG *) 0xFFFC4118) // (PDC_SSC2) Transmit Next Pointer Register
+#define AT91C_SSC2_RCR (AT91_CAST(AT91_REG *) 0xFFFC4104) // (PDC_SSC2) Receive Counter Register
+#define AT91C_SSC2_RNPR (AT91_CAST(AT91_REG *) 0xFFFC4110) // (PDC_SSC2) Receive Next Pointer Register
+#define AT91C_SSC2_RPR (AT91_CAST(AT91_REG *) 0xFFFC4100) // (PDC_SSC2) Receive Pointer Register
+#define AT91C_SSC2_TNCR (AT91_CAST(AT91_REG *) 0xFFFC411C) // (PDC_SSC2) Transmit Next Counter Register
+#define AT91C_SSC2_TPR (AT91_CAST(AT91_REG *) 0xFFFC4108) // (PDC_SSC2) Transmit Pointer Register
+// ========== Register definition for SSC2 peripheral ==========
+#define AT91C_SSC2_FEATURES (AT91_CAST(AT91_REG *) 0xFFFC40F8) // (SSC2) SSC FEATURES REGISTER
+#define AT91C_SSC2_IER (AT91_CAST(AT91_REG *) 0xFFFC4044) // (SSC2) Interrupt Enable Register
+#define AT91C_SSC2_TFMR (AT91_CAST(AT91_REG *) 0xFFFC401C) // (SSC2) Transmit Frame Mode Register
+#define AT91C_SSC2_RSHR (AT91_CAST(AT91_REG *) 0xFFFC4030) // (SSC2) Receive Sync Holding Register
+#define AT91C_SSC2_VER (AT91_CAST(AT91_REG *) 0xFFFC40FC) // (SSC2) Version Register
+#define AT91C_SSC2_CR (AT91_CAST(AT91_REG *) 0xFFFC4000) // (SSC2) Control Register
+#define AT91C_SSC2_SR (AT91_CAST(AT91_REG *) 0xFFFC4040) // (SSC2) Status Register
+#define AT91C_SSC2_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFC40EC) // (SSC2) SSC ADDRSIZE REGISTER
+#define AT91C_SSC2_IMR (AT91_CAST(AT91_REG *) 0xFFFC404C) // (SSC2) Interrupt Mask Register
+#define AT91C_SSC2_THR (AT91_CAST(AT91_REG *) 0xFFFC4024) // (SSC2) Transmit Holding Register
+#define AT91C_SSC2_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFC40F0) // (SSC2) SSC IPNAME1 REGISTER
+#define AT91C_SSC2_RFMR (AT91_CAST(AT91_REG *) 0xFFFC4014) // (SSC2) Receive Frame Mode Register
+#define AT91C_SSC2_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFC40F4) // (SSC2) SSC IPNAME2 REGISTER
+#define AT91C_SSC2_IDR (AT91_CAST(AT91_REG *) 0xFFFC4048) // (SSC2) Interrupt Disable Register
+#define AT91C_SSC2_RHR (AT91_CAST(AT91_REG *) 0xFFFC4020) // (SSC2) Receive Holding Register
+#define AT91C_SSC2_TCMR (AT91_CAST(AT91_REG *) 0xFFFC4018) // (SSC2) Transmit Clock Mode Register
+#define AT91C_SSC2_RCMR (AT91_CAST(AT91_REG *) 0xFFFC4010) // (SSC2) Receive Clock ModeRegister
+#define AT91C_SSC2_CMR (AT91_CAST(AT91_REG *) 0xFFFC4004) // (SSC2) Clock Mode Register
+#define AT91C_SSC2_TSHR (AT91_CAST(AT91_REG *) 0xFFFC4034) // (SSC2) Transmit Sync Holding Register
+// ========== Register definition for PDC_SPI0 peripheral ==========
+#define AT91C_SPI0_PTCR (AT91_CAST(AT91_REG *) 0xFFFC8120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TCR (AT91_CAST(AT91_REG *) 0xFFFC810C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RPR (AT91_CAST(AT91_REG *) 0xFFFC8100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TPR (AT91_CAST(AT91_REG *) 0xFFFC8108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_PTSR (AT91_CAST(AT91_REG *) 0xFFFC8124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNCR (AT91_CAST(AT91_REG *) 0xFFFC8114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR (AT91_CAST(AT91_REG *) 0xFFFC8118) // (PDC_SPI0) Transmit Next Pointer Register
+#define AT91C_SPI0_RCR (AT91_CAST(AT91_REG *) 0xFFFC8104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_RNPR (AT91_CAST(AT91_REG *) 0xFFFC8110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_TNCR (AT91_CAST(AT91_REG *) 0xFFFC811C) // (PDC_SPI0) Transmit Next Counter Register
+// ========== Register definition for SPI0 peripheral ==========
+#define AT91C_SPI0_IDR (AT91_CAST(AT91_REG *) 0xFFFC8018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_TDR (AT91_CAST(AT91_REG *) 0xFFFC800C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_SR (AT91_CAST(AT91_REG *) 0xFFFC8010) // (SPI0) Status Register
+#define AT91C_SPI0_CR (AT91_CAST(AT91_REG *) 0xFFFC8000) // (SPI0) Control Register
+#define AT91C_SPI0_CSR (AT91_CAST(AT91_REG *) 0xFFFC8030) // (SPI0) Chip Select Register
+#define AT91C_SPI0_RDR (AT91_CAST(AT91_REG *) 0xFFFC8008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_MR (AT91_CAST(AT91_REG *) 0xFFFC8004) // (SPI0) Mode Register
+#define AT91C_SPI0_IER (AT91_CAST(AT91_REG *) 0xFFFC8014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_IMR (AT91_CAST(AT91_REG *) 0xFFFC801C) // (SPI0) Interrupt Mask Register
+// ========== Register definition for PDC_SPI1 peripheral ==========
+#define AT91C_SPI1_PTCR (AT91_CAST(AT91_REG *) 0xFFFCC120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RNPR (AT91_CAST(AT91_REG *) 0xFFFCC110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RCR (AT91_CAST(AT91_REG *) 0xFFFCC104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_TPR (AT91_CAST(AT91_REG *) 0xFFFCC108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_PTSR (AT91_CAST(AT91_REG *) 0xFFFCC124) // (PDC_SPI1) PDC Transfer Status Register
+#define AT91C_SPI1_TNCR (AT91_CAST(AT91_REG *) 0xFFFCC11C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_RPR (AT91_CAST(AT91_REG *) 0xFFFCC100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TCR (AT91_CAST(AT91_REG *) 0xFFFCC10C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RNCR (AT91_CAST(AT91_REG *) 0xFFFCC114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_TNPR (AT91_CAST(AT91_REG *) 0xFFFCC118) // (PDC_SPI1) Transmit Next Pointer Register
+// ========== Register definition for SPI1 peripheral ==========
+#define AT91C_SPI1_IER (AT91_CAST(AT91_REG *) 0xFFFCC014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_RDR (AT91_CAST(AT91_REG *) 0xFFFCC008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_SR (AT91_CAST(AT91_REG *) 0xFFFCC010) // (SPI1) Status Register
+#define AT91C_SPI1_IMR (AT91_CAST(AT91_REG *) 0xFFFCC01C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_TDR (AT91_CAST(AT91_REG *) 0xFFFCC00C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_IDR (AT91_CAST(AT91_REG *) 0xFFFCC018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_CSR (AT91_CAST(AT91_REG *) 0xFFFCC030) // (SPI1) Chip Select Register
+#define AT91C_SPI1_CR (AT91_CAST(AT91_REG *) 0xFFFCC000) // (SPI1) Control Register
+#define AT91C_SPI1_MR (AT91_CAST(AT91_REG *) 0xFFFCC004) // (SPI1) Mode Register
+// ========== Register definition for UHP peripheral ==========
+#define AT91C_UHP_HcInterruptStatus (AT91_CAST(AT91_REG *) 0x0050000C) // (UHP) Interrupt Status Register
+#define AT91C_UHP_HcCommandStatus (AT91_CAST(AT91_REG *) 0x00500008) // (UHP) Command & status Register
+#define AT91C_UHP_HcRhStatus (AT91_CAST(AT91_REG *) 0x00500050) // (UHP) Root Hub Status register
+#define AT91C_UHP_HcInterruptDisable (AT91_CAST(AT91_REG *) 0x00500014) // (UHP) Interrupt Disable Register
+#define AT91C_UHP_HcPeriodicStart (AT91_CAST(AT91_REG *) 0x00500040) // (UHP) Periodic Start
+#define AT91C_UHP_HcControlCurrentED (AT91_CAST(AT91_REG *) 0x00500024) // (UHP) Endpoint Control and Status Register
+#define AT91C_UHP_HcPeriodCurrentED (AT91_CAST(AT91_REG *) 0x0050001C) // (UHP) Current Isochronous or Interrupt Endpoint Descriptor
+#define AT91C_UHP_HcBulkHeadED (AT91_CAST(AT91_REG *) 0x00500028) // (UHP) First endpoint register of the Bulk list
+#define AT91C_UHP_HcRevision (AT91_CAST(AT91_REG *) 0x00500000) // (UHP) Revision
+#define AT91C_UHP_HcBulkCurrentED (AT91_CAST(AT91_REG *) 0x0050002C) // (UHP) Current endpoint of the Bulk list
+#define AT91C_UHP_HcRhDescriptorB (AT91_CAST(AT91_REG *) 0x0050004C) // (UHP) Root Hub characteristics B
+#define AT91C_UHP_HcControlHeadED (AT91_CAST(AT91_REG *) 0x00500020) // (UHP) First Endpoint Descriptor of the Control list
+#define AT91C_UHP_HcFmRemaining (AT91_CAST(AT91_REG *) 0x00500038) // (UHP) Bit time remaining in the current Frame
+#define AT91C_UHP_HcHCCA (AT91_CAST(AT91_REG *) 0x00500018) // (UHP) Pointer to the Host Controller Communication Area
+#define AT91C_UHP_HcLSThreshold (AT91_CAST(AT91_REG *) 0x00500044) // (UHP) LS Threshold
+#define AT91C_UHP_HcRhPortStatus (AT91_CAST(AT91_REG *) 0x00500054) // (UHP) Root Hub Port Status Register
+#define AT91C_UHP_HcInterruptEnable (AT91_CAST(AT91_REG *) 0x00500010) // (UHP) Interrupt Enable Register
+#define AT91C_UHP_HcFmNumber (AT91_CAST(AT91_REG *) 0x0050003C) // (UHP) Frame number
+#define AT91C_UHP_HcFmInterval (AT91_CAST(AT91_REG *) 0x00500034) // (UHP) Bit time between 2 consecutive SOFs
+#define AT91C_UHP_HcControl (AT91_CAST(AT91_REG *) 0x00500004) // (UHP) Operating modes for the Host Controller
+#define AT91C_UHP_HcBulkDoneHead (AT91_CAST(AT91_REG *) 0x00500030) // (UHP) Last completed transfer descriptor
+#define AT91C_UHP_HcRhDescriptorA (AT91_CAST(AT91_REG *) 0x00500048) // (UHP) Root Hub characteristics A
+// ========== Register definition for LCDC peripheral ==========
+#define AT91C_LCDC_DP4_7 (AT91_CAST(AT91_REG *) 0x00600820) // (LCDC) Dithering Pattern DP4_7 Register
+#define AT91C_LCDC_PWRCON (AT91_CAST(AT91_REG *) 0x0060083C) // (LCDC) Power Control Register
+#define AT91C_LCDC_LUT_ENTRY (AT91_CAST(AT91_REG *) 0x00600C00) // (LCDC) LUT Entries Register
+#define AT91C_LCDC_TIM1 (AT91_CAST(AT91_REG *) 0x00600808) // (LCDC) LCD Timing Config 1 Register
+#define AT91C_LCDC_CTRSTVAL (AT91_CAST(AT91_REG *) 0x00600844) // (LCDC) Contrast Value Register
+#define AT91C_LCDC_ISR (AT91_CAST(AT91_REG *) 0x00600854) // (LCDC) Interrupt Enable Register
+#define AT91C_LCDC_IDR (AT91_CAST(AT91_REG *) 0x0060084C) // (LCDC) Interrupt Disable Register
+#define AT91C_LCDC_DP2_3 (AT91_CAST(AT91_REG *) 0x00600828) // (LCDC) Dithering Pattern DP2_3 Register
+#define AT91C_LCDC_DP1_2 (AT91_CAST(AT91_REG *) 0x0060081C) // (LCDC) Dithering Pattern DP1_2 Register
+#define AT91C_LCDC_FRMP1 (AT91_CAST(AT91_REG *) 0x00600008) // (LCDC) DMA Frame Pointer Register 1
+#define AT91C_LCDC_LCDCON2 (AT91_CAST(AT91_REG *) 0x00600804) // (LCDC) LCD Control 2 Register
+#define AT91C_LCDC_DP4_5 (AT91_CAST(AT91_REG *) 0x00600834) // (LCDC) Dithering Pattern DP4_5 Register
+#define AT91C_LCDC_IRR (AT91_CAST(AT91_REG *) 0x00600864) // (LCDC) Interrupts Raw Status Register
+#define AT91C_LCDC_IER (AT91_CAST(AT91_REG *) 0x00600848) // (LCDC) Interrupt Enable Register
+#define AT91C_LCDC_MVAL (AT91_CAST(AT91_REG *) 0x00600818) // (LCDC) LCD Mode Toggle Rate Value Register
+#define AT91C_LCDC_BA2 (AT91_CAST(AT91_REG *) 0x00600004) // (LCDC) DMA Base Address Register 2
+#define AT91C_LCDC_DMA2DCFG (AT91_CAST(AT91_REG *) 0x00600020) // (LCDC) DMA 2D addressing configuration
+#define AT91C_LCDC_ICR (AT91_CAST(AT91_REG *) 0x00600858) // (LCDC) Interrupt Clear Register
+#define AT91C_LCDC_FRMA2 (AT91_CAST(AT91_REG *) 0x00600014) // (LCDC) DMA Frame Address Register 2
+#define AT91C_LCDC_LCDFRCFG (AT91_CAST(AT91_REG *) 0x00600810) // (LCDC) LCD Frame Config Register
+#define AT91C_LCDC_FRMP2 (AT91_CAST(AT91_REG *) 0x0060000C) // (LCDC) DMA Frame Pointer Register 2
+#define AT91C_LCDC_LCDCON1 (AT91_CAST(AT91_REG *) 0x00600800) // (LCDC) LCD Control 1 Register
+#define AT91C_LCDC_FRMCFG (AT91_CAST(AT91_REG *) 0x00600018) // (LCDC) DMA Frame Configuration Register
+#define AT91C_LCDC_DP5_7 (AT91_CAST(AT91_REG *) 0x0060082C) // (LCDC) Dithering Pattern DP5_7 Register
+#define AT91C_LCDC_GPR (AT91_CAST(AT91_REG *) 0x0060085C) // (LCDC) General Purpose Register
+#define AT91C_LCDC_FIFO (AT91_CAST(AT91_REG *) 0x00600814) // (LCDC) LCD FIFO Register
+#define AT91C_LCDC_CTRSTCON (AT91_CAST(AT91_REG *) 0x00600840) // (LCDC) Contrast Control Register
+#define AT91C_LCDC_DP3_4 (AT91_CAST(AT91_REG *) 0x00600830) // (LCDC) Dithering Pattern DP3_4 Register
+#define AT91C_LCDC_FRMA1 (AT91_CAST(AT91_REG *) 0x00600010) // (LCDC) DMA Frame Address Register 1
+#define AT91C_LCDC_TIM2 (AT91_CAST(AT91_REG *) 0x0060080C) // (LCDC) LCD Timing Config 2 Register
+#define AT91C_LCDC_BA1 (AT91_CAST(AT91_REG *) 0x00600000) // (LCDC) DMA Base Address Register 1
+#define AT91C_LCDC_DP3_5 (AT91_CAST(AT91_REG *) 0x00600824) // (LCDC) Dithering Pattern DP3_5 Register
+#define AT91C_LCDC_DP6_7 (AT91_CAST(AT91_REG *) 0x00600838) // (LCDC) Dithering Pattern DP6_7 Register
+#define AT91C_LCDC_DMACON (AT91_CAST(AT91_REG *) 0x0060001C) // (LCDC) DMA Control Register
+#define AT91C_LCDC_IMR (AT91_CAST(AT91_REG *) 0x00600850) // (LCDC) Interrupt Mask Register
+#define AT91C_LCDC_ITR (AT91_CAST(AT91_REG *) 0x00600860) // (LCDC) Interrupts Test Register
+// ========== Register definition for LCDC_16B_TFT peripheral ==========
+#define AT91C_TFT_DP4_7 (AT91_CAST(AT91_REG *) 0x00600820) // (LCDC_16B_TFT) Dithering Pattern DP4_7 Register
+#define AT91C_TFT_PWRCON (AT91_CAST(AT91_REG *) 0x0060083C) // (LCDC_16B_TFT) Power Control Register
+#define AT91C_TFT_LUT_ENTRY (AT91_CAST(AT91_REG *) 0x00600C00) // (LCDC_16B_TFT) LUT Entries Register
+#define AT91C_TFT_TIM1 (AT91_CAST(AT91_REG *) 0x00600808) // (LCDC_16B_TFT) LCD Timing Config 1 Register
+#define AT91C_TFT_CTRSTVAL (AT91_CAST(AT91_REG *) 0x00600844) // (LCDC_16B_TFT) Contrast Value Register
+#define AT91C_TFT_ISR (AT91_CAST(AT91_REG *) 0x00600854) // (LCDC_16B_TFT) Interrupt Enable Register
+#define AT91C_TFT_IDR (AT91_CAST(AT91_REG *) 0x0060084C) // (LCDC_16B_TFT) Interrupt Disable Register
+#define AT91C_TFT_DP2_3 (AT91_CAST(AT91_REG *) 0x00600828) // (LCDC_16B_TFT) Dithering Pattern DP2_3 Register
+#define AT91C_TFT_DP1_2 (AT91_CAST(AT91_REG *) 0x0060081C) // (LCDC_16B_TFT) Dithering Pattern DP1_2 Register
+#define AT91C_TFT_FRMP1 (AT91_CAST(AT91_REG *) 0x00600008) // (LCDC_16B_TFT) DMA Frame Pointer Register 1
+#define AT91C_TFT_LCDCON2 (AT91_CAST(AT91_REG *) 0x00600804) // (LCDC_16B_TFT) LCD Control 2 Register
+#define AT91C_TFT_DP4_5 (AT91_CAST(AT91_REG *) 0x00600834) // (LCDC_16B_TFT) Dithering Pattern DP4_5 Register
+#define AT91C_TFT_IRR (AT91_CAST(AT91_REG *) 0x00600864) // (LCDC_16B_TFT) Interrupts Raw Status Register
+#define AT91C_TFT_IER (AT91_CAST(AT91_REG *) 0x00600848) // (LCDC_16B_TFT) Interrupt Enable Register
+#define AT91C_TFT_MVAL (AT91_CAST(AT91_REG *) 0x00600818) // (LCDC_16B_TFT) LCD Mode Toggle Rate Value Register
+#define AT91C_TFT_BA2 (AT91_CAST(AT91_REG *) 0x00600004) // (LCDC_16B_TFT) DMA Base Address Register 2
+#define AT91C_TFT_DMA2DCFG (AT91_CAST(AT91_REG *) 0x00600020) // (LCDC_16B_TFT) DMA 2D addressing configuration
+#define AT91C_TFT_ICR (AT91_CAST(AT91_REG *) 0x00600858) // (LCDC_16B_TFT) Interrupt Clear Register
+#define AT91C_TFT_FRMA2 (AT91_CAST(AT91_REG *) 0x00600014) // (LCDC_16B_TFT) DMA Frame Address Register 2
+#define AT91C_TFT_LCDFRCFG (AT91_CAST(AT91_REG *) 0x00600810) // (LCDC_16B_TFT) LCD Frame Config Register
+#define AT91C_TFT_FRMP2 (AT91_CAST(AT91_REG *) 0x0060000C) // (LCDC_16B_TFT) DMA Frame Pointer Register 2
+#define AT91C_TFT_LCDCON1 (AT91_CAST(AT91_REG *) 0x00600800) // (LCDC_16B_TFT) LCD Control 1 Register
+#define AT91C_TFT_FRMCFG (AT91_CAST(AT91_REG *) 0x00600018) // (LCDC_16B_TFT) DMA Frame Configuration Register
+#define AT91C_TFT_DP5_7 (AT91_CAST(AT91_REG *) 0x0060082C) // (LCDC_16B_TFT) Dithering Pattern DP5_7 Register
+#define AT91C_TFT_GPR (AT91_CAST(AT91_REG *) 0x0060085C) // (LCDC_16B_TFT) General Purpose Register
+#define AT91C_TFT_FIFO (AT91_CAST(AT91_REG *) 0x00600814) // (LCDC_16B_TFT) LCD FIFO Register
+#define AT91C_TFT_CTRSTCON (AT91_CAST(AT91_REG *) 0x00600840) // (LCDC_16B_TFT) Contrast Control Register
+#define AT91C_TFT_DP3_4 (AT91_CAST(AT91_REG *) 0x00600830) // (LCDC_16B_TFT) Dithering Pattern DP3_4 Register
+#define AT91C_TFT_FRMA1 (AT91_CAST(AT91_REG *) 0x00600010) // (LCDC_16B_TFT) DMA Frame Address Register 1
+#define AT91C_TFT_TIM2 (AT91_CAST(AT91_REG *) 0x0060080C) // (LCDC_16B_TFT) LCD Timing Config 2 Register
+#define AT91C_TFT_BA1 (AT91_CAST(AT91_REG *) 0x00600000) // (LCDC_16B_TFT) DMA Base Address Register 1
+#define AT91C_TFT_DP3_5 (AT91_CAST(AT91_REG *) 0x00600824) // (LCDC_16B_TFT) Dithering Pattern DP3_5 Register
+#define AT91C_TFT_DP6_7 (AT91_CAST(AT91_REG *) 0x00600838) // (LCDC_16B_TFT) Dithering Pattern DP6_7 Register
+#define AT91C_TFT_DMACON (AT91_CAST(AT91_REG *) 0x0060001C) // (LCDC_16B_TFT) DMA Control Register
+#define AT91C_TFT_IMR (AT91_CAST(AT91_REG *) 0x00600850) // (LCDC_16B_TFT) Interrupt Mask Register
+#define AT91C_TFT_ITR (AT91_CAST(AT91_REG *) 0x00600860) // (LCDC_16B_TFT) Interrupts Test Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91SAM9G10
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_SPI0_MISO (AT91C_PIO_PA0) // SPI0 Master In Slave
+#define AT91C_PA0_MCDA0 (AT91C_PIO_PA0) // Multimedia Card A Data 0
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_SPI0_MOSI (AT91C_PIO_PA1) // SPI0 Master Out Slave
+#define AT91C_PA1_MCCDA (AT91C_PIO_PA1) // Multimedia Card A Command
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data
+#define AT91C_PA10_PCK3 (AT91C_PIO_PA10) // PMC Programmable clock Output 3
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TSYNC (AT91C_PIO_PA11) // Trace Synchronization Signal
+#define AT91C_PA11_SCK1 (AT91C_PIO_PA11) // USART1 Serial Clock
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_TCLK (AT91C_PIO_PA12) // Trace Clock
+#define AT91C_PA12_RTS1 (AT91C_PIO_PA12) // USART1 Ready To Send
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_TPS0 (AT91C_PIO_PA13) // Trace ARM Pipeline Status 0
+#define AT91C_PA13_CTS1 (AT91C_PIO_PA13) // USART1 Clear To Send
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_TPS1 (AT91C_PIO_PA14) // Trace ARM Pipeline Status 1
+#define AT91C_PA14_SCK2 (AT91C_PIO_PA14) // USART2 Serial Clock
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TPS2 (AT91C_PIO_PA15) // Trace ARM Pipeline Status 2
+#define AT91C_PA15_RTS2 (AT91C_PIO_PA15) // USART2 Ready To Send
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TPK0 (AT91C_PIO_PA16) // Trace Packet Port 0
+#define AT91C_PA16_CTS2 (AT91C_PIO_PA16) // USART2 Clear To Send
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TPK1 (AT91C_PIO_PA17) // Trace Packet Port 1
+#define AT91C_PA17_TF1 (AT91C_PIO_PA17) // SSC1 Transmit Frame Sync
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_TPK2 (AT91C_PIO_PA18) // Trace Packet Port 2
+#define AT91C_PA18_TK1 (AT91C_PIO_PA18) // SSC1 Transmit Clock
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_TPK3 (AT91C_PIO_PA19) // Trace Packet Port 3
+#define AT91C_PA19_TD1 (AT91C_PIO_PA19) // SSC1 Transmit Data
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_SPI0_SPCK (AT91C_PIO_PA2) // SPI0 Serial Clock
+#define AT91C_PA2_MCCK (AT91C_PIO_PA2) // Multimedia Card Clock
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_TPK4 (AT91C_PIO_PA20) // Trace Packet Port 4
+#define AT91C_PA20_RD1 (AT91C_PIO_PA20) // SSC1 Receive Data
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TPK5 (AT91C_PIO_PA21) // Trace Packet Port 5
+#define AT91C_PA21_RK1 (AT91C_PIO_PA21) // SSC1 Receive Clock
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TPK6 (AT91C_PIO_PA22) // Trace Packet Port 6
+#define AT91C_PA22_RF1 (AT91C_PIO_PA22) // SSC1 Receive Frame Sync
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TPK7 (AT91C_PIO_PA23) // Trace Packet Port 7
+#define AT91C_PA23_RTS0 (AT91C_PIO_PA23) // USART0 Ready To Send
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_TPK8 (AT91C_PIO_PA24) // Trace Packet Port 8
+#define AT91C_PA24_SPI1_NPCS1 (AT91C_PIO_PA24) // SPI1 Peripheral Chip Select 1
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_TPK9 (AT91C_PIO_PA25) // Trace Packet Port 9
+#define AT91C_PA25_SPI1_NPCS2 (AT91C_PIO_PA25) // SPI1 Peripheral Chip Select 2
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_TPK10 (AT91C_PIO_PA26) // Trace Packet Port 10
+#define AT91C_PA26_SPI1_NPCS3 (AT91C_PIO_PA26) // SPI1 Peripheral Chip Select 3
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_TPK11 (AT91C_PIO_PA27) // Trace Packet Port 11
+#define AT91C_PA27_SPI0_NPCS1 (AT91C_PIO_PA27) // SPI0 Peripheral Chip Select 1
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_TPK12 (AT91C_PIO_PA28) // Trace Packet Port 12
+#define AT91C_PA28_SPI0_NPCS2 (AT91C_PIO_PA28) // SPI0 Peripheral Chip Select 2
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_TPK13 (AT91C_PIO_PA29) // Trace Packet Port 13
+#define AT91C_PA29_SPI0_NPCS3 (AT91C_PIO_PA29) // SPI0 Peripheral Chip Select 3
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_SPI0_NPCS0 (AT91C_PIO_PA3) // SPI0 Peripheral Chip Select 0
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_TPK14 (AT91C_PIO_PA30) // Trace Packet Port 14
+#define AT91C_PA30_A23 (AT91C_PIO_PA30) // Address Bus bit 23
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_TPK15 (AT91C_PIO_PA31) // Trace Packet Port 15
+#define AT91C_PA31_A24 (AT91C_PIO_PA31) // Address Bus bit 24
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_SPI0_NPCS1 (AT91C_PIO_PA4) // SPI0 Peripheral Chip Select 1
+#define AT91C_PA4_MCDA1 (AT91C_PIO_PA4) // Multimedia Card A Data 1
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_SPI0_NPCS2 (AT91C_PIO_PA5) // SPI0 Peripheral Chip Select 2
+#define AT91C_PA5_MCDA2 (AT91C_PIO_PA5) // Multimedia Card A Data 2
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_SPI0_NPCS3 (AT91C_PIO_PA6) // SPI0 Peripheral Chip Select 3
+#define AT91C_PA6_MCDA3 (AT91C_PIO_PA6) // Multimedia Card A Data 3
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_TWD (AT91C_PIO_PA7) // TWI Two-wire Serial Data
+#define AT91C_PA7_PCK0 (AT91C_PIO_PA7) // PMC Programmable clock Output 0
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_TWCK (AT91C_PIO_PA8) // TWI Two-wire Serial Clock
+#define AT91C_PA8_PCK1 (AT91C_PIO_PA8) // PMC Programmable clock Output 1
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data
+#define AT91C_PA9_PCK2 (AT91C_PIO_PA9) // PMC Programmable clock Output 2
+#define AT91C_PIO_PB0 (1 << 0) // Pin Controlled by PB0
+#define AT91C_PB0_LCDVSYNC (AT91C_PIO_PB0) // LCD Vertical Synchronization
+#define AT91C_PIO_PB1 (1 << 1) // Pin Controlled by PB1
+#define AT91C_PB1_LCDHSYNC (AT91C_PIO_PB1) // LCD Horizontal Synchronization
+#define AT91C_PIO_PB10 (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_LCDD5 (AT91C_PIO_PB10) // LCD Data Bus Bit 5
+#define AT91C_PB10_LCDD10 (AT91C_PIO_PB10) // LCD Data Bus Bit 10
+#define AT91C_PIO_PB11 (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_LCDD6 (AT91C_PIO_PB11) // LCD Data Bus Bit 6
+#define AT91C_PB11_LCDD11 (AT91C_PIO_PB11) // LCD Data Bus Bit 11
+#define AT91C_PIO_PB12 (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_LCDD7 (AT91C_PIO_PB12) // LCD Data Bus Bit 7
+#define AT91C_PB12_LCDD12 (AT91C_PIO_PB12) // LCD Data Bus Bit 12
+#define AT91C_PIO_PB13 (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_LCDD8 (AT91C_PIO_PB13) // LCD Data Bus Bit 8
+#define AT91C_PB13_LCDD13 (AT91C_PIO_PB13) // LCD Data Bus Bit 13
+#define AT91C_PIO_PB14 (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_LCDD9 (AT91C_PIO_PB14) // LCD Data Bus Bit 9
+#define AT91C_PB14_LCDD14 (AT91C_PIO_PB14) // LCD Data Bus Bit 14
+#define AT91C_PIO_PB15 (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_LCDD10 (AT91C_PIO_PB15) // LCD Data Bus Bit 10
+#define AT91C_PB15_LCDD15 (AT91C_PIO_PB15) // LCD Data Bus Bit 15
+#define AT91C_PIO_PB16 (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_LCDD11 (AT91C_PIO_PB16) // LCD Data Bus Bit 11
+#define AT91C_PB16_LCDD19 (AT91C_PIO_PB16) // LCD Data Bus Bit 19
+#define AT91C_PIO_PB17 (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_LCDD12 (AT91C_PIO_PB17) // LCD Data Bus Bit 12
+#define AT91C_PB17_LCDD20 (AT91C_PIO_PB17) // LCD Data Bus Bit 20
+#define AT91C_PIO_PB18 (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_LCDD13 (AT91C_PIO_PB18) // LCD Data Bus Bit 13
+#define AT91C_PB18_LCDD21 (AT91C_PIO_PB18) // LCD Data Bus Bit 21
+#define AT91C_PIO_PB19 (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_LCDD14 (AT91C_PIO_PB19) // LCD Data Bus Bit 14
+#define AT91C_PB19_LCDD22 (AT91C_PIO_PB19) // LCD Data Bus Bit 22
+#define AT91C_PIO_PB2 (1 << 2) // Pin Controlled by PB2
+#define AT91C_PB2_LCDDOTCK (AT91C_PIO_PB2) // LCD Dot Clock
+#define AT91C_PB2_PCK0 (AT91C_PIO_PB2) // PMC Programmable clock Output 0
+#define AT91C_PIO_PB20 (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_LCDD15 (AT91C_PIO_PB20) // LCD Data Bus Bit 15
+#define AT91C_PB20_LCDD23 (AT91C_PIO_PB20) // LCD Data Bus Bit 23
+#define AT91C_PIO_PB21 (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_TF0 (AT91C_PIO_PB21) // SSC0 Transmit Frame Sync
+#define AT91C_PB21_LCDD16 (AT91C_PIO_PB21) // LCD Data Bus Bit 16
+#define AT91C_PIO_PB22 (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_TK0 (AT91C_PIO_PB22) // SSC0 Transmit Clock
+#define AT91C_PB22_LCDD17 (AT91C_PIO_PB22) // LCD Data Bus Bit 17
+#define AT91C_PIO_PB23 (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TD0 (AT91C_PIO_PB23) // SSC0 Transmit Data
+#define AT91C_PB23_LCDD18 (AT91C_PIO_PB23) // LCD Data Bus Bit 18
+#define AT91C_PIO_PB24 (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_RD0 (AT91C_PIO_PB24) // SSC0 Receive Data
+#define AT91C_PB24_LCDD19 (AT91C_PIO_PB24) // LCD Data Bus Bit 19
+#define AT91C_PIO_PB25 (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_RK0 (AT91C_PIO_PB25) // SSC0 Receive Clock
+#define AT91C_PB25_LCDD20 (AT91C_PIO_PB25) // LCD Data Bus Bit 20
+#define AT91C_PIO_PB26 (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_RF0 (AT91C_PIO_PB26) // SSC0 Receive Frame Sync
+#define AT91C_PB26_LCDD21 (AT91C_PIO_PB26) // LCD Data Bus Bit 21
+#define AT91C_PIO_PB27 (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_SPI1_NPCS1 (AT91C_PIO_PB27) // SPI1 Peripheral Chip Select 1
+#define AT91C_PB27_LCDD22 (AT91C_PIO_PB27) // LCD Data Bus Bit 22
+#define AT91C_PIO_PB28 (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_SPI1_NPCS0 (AT91C_PIO_PB28) // SPI1 Peripheral Chip Select 0
+#define AT91C_PB28_LCDD23 (AT91C_PIO_PB28) // LCD Data Bus Bit 23
+#define AT91C_PIO_PB29 (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_SPI1_SPCK (AT91C_PIO_PB29) // SPI1 Serial Clock
+#define AT91C_PB29_IRQ2 (AT91C_PIO_PB29) // Interrupt input 2
+#define AT91C_PIO_PB3 (1 << 3) // Pin Controlled by PB3
+#define AT91C_PB3_LCDDEN (AT91C_PIO_PB3) // LCD Data Enable
+#define AT91C_PIO_PB30 (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_SPI1_MISO (AT91C_PIO_PB30) // SPI1 Master In Slave
+#define AT91C_PB30_IRQ1 (AT91C_PIO_PB30) // Interrupt input 1
+#define AT91C_PIO_PB31 (1 << 31) // Pin Controlled by PB31
+#define AT91C_PB31_SPI1_MOSI (AT91C_PIO_PB31) // SPI1 Master Out Slave
+#define AT91C_PB31_PCK2 (AT91C_PIO_PB31) // PMC Programmable clock Output 2
+#define AT91C_PIO_PB4 (1 << 4) // Pin Controlled by PB4
+#define AT91C_PB4_LCDCC (AT91C_PIO_PB4) // LCD Contrast Control
+#define AT91C_PB4_LCDD2 (AT91C_PIO_PB4) // LCD Data Bus Bit 2
+#define AT91C_PIO_PB5 (1 << 5) // Pin Controlled by PB5
+#define AT91C_PB5_LCDD0 (AT91C_PIO_PB5) // LCD Data Bus Bit 0
+#define AT91C_PB5_LCDD3 (AT91C_PIO_PB5) // LCD Data Bus Bit 3
+#define AT91C_PIO_PB6 (1 << 6) // Pin Controlled by PB6
+#define AT91C_PB6_LCDD1 (AT91C_PIO_PB6) // LCD Data Bus Bit 1
+#define AT91C_PB6_LCDD4 (AT91C_PIO_PB6) // LCD Data Bus Bit 4
+#define AT91C_PIO_PB7 (1 << 7) // Pin Controlled by PB7
+#define AT91C_PB7_LCDD2 (AT91C_PIO_PB7) // LCD Data Bus Bit 2
+#define AT91C_PB7_LCDD5 (AT91C_PIO_PB7) // LCD Data Bus Bit 5
+#define AT91C_PIO_PB8 (1 << 8) // Pin Controlled by PB8
+#define AT91C_PB8_LCDD3 (AT91C_PIO_PB8) // LCD Data Bus Bit 3
+#define AT91C_PB8_LCDD6 (AT91C_PIO_PB8) // LCD Data Bus Bit 6
+#define AT91C_PIO_PB9 (1 << 9) // Pin Controlled by PB9
+#define AT91C_PB9_LCDD4 (AT91C_PIO_PB9) // LCD Data Bus Bit 4
+#define AT91C_PB9_LCDD7 (AT91C_PIO_PB9) // LCD Data Bus Bit 7
+#define AT91C_PIO_PC0 (1 << 0) // Pin Controlled by PC0
+#define AT91C_PC0_SMOE (AT91C_PIO_PC0) // SmartMedia Output Enable
+#define AT91C_PC0_NCS6 (AT91C_PIO_PC0) // Chip Select 6
+#define AT91C_PIO_PC1 (1 << 1) // Pin Controlled by PC1
+#define AT91C_PC1_SMWE (AT91C_PIO_PC1) // SmartMedia Write Enable
+#define AT91C_PC1_NCS7 (AT91C_PIO_PC1) // Chip Select 7
+#define AT91C_PIO_PC10 (1 << 10) // Pin Controlled by PC10
+#define AT91C_PC10_RTS0 (AT91C_PIO_PC10) // USART0 Ready To Send
+#define AT91C_PC10_SCK0 (AT91C_PIO_PC10) // USART0 Serial Clock
+#define AT91C_PIO_PC11 (1 << 11) // Pin Controlled by PC11
+#define AT91C_PC11_CTS0 (AT91C_PIO_PC11) // USART0 Clear To Send
+#define AT91C_PC11_FIQ (AT91C_PIO_PC11) // AIC Fast Interrupt Input
+#define AT91C_PIO_PC12 (1 << 12) // Pin Controlled by PC12
+#define AT91C_PC12_TXD1 (AT91C_PIO_PC12) // USART1 Transmit Data
+#define AT91C_PC12_NCS6 (AT91C_PIO_PC12) // Chip Select 6
+#define AT91C_PIO_PC13 (1 << 13) // Pin Controlled by PC13
+#define AT91C_PC13_RXD1 (AT91C_PIO_PC13) // USART1 Receive Data
+#define AT91C_PC13_NCS7 (AT91C_PIO_PC13) // Chip Select 7
+#define AT91C_PIO_PC14 (1 << 14) // Pin Controlled by PC14
+#define AT91C_PC14_TXD2 (AT91C_PIO_PC14) // USART2 Transmit Data
+#define AT91C_PC14_SPI1_NPCS2 (AT91C_PIO_PC14) // SPI1 Peripheral Chip Select 2
+#define AT91C_PIO_PC15 (1 << 15) // Pin Controlled by PC15
+#define AT91C_PC15_RXD2 (AT91C_PIO_PC15) // USART2 Receive Data
+#define AT91C_PC15_SPI1_NPCS3 (AT91C_PIO_PC15) // SPI1 Peripheral Chip Select 3
+#define AT91C_PIO_PC16 (1 << 16) // Pin Controlled by PC16
+#define AT91C_PC16_D16 (AT91C_PIO_PC16) // Data Bus [16]
+#define AT91C_PC16_TCLK0 (AT91C_PIO_PC16) // Timer Counter 0 external clock input
+#define AT91C_PIO_PC17 (1 << 17) // Pin Controlled by PC17
+#define AT91C_PC17_D17 (AT91C_PIO_PC17) // Data Bus [17]
+#define AT91C_PC17_TCLK1 (AT91C_PIO_PC17) // Timer Counter 1 external clock input
+#define AT91C_PIO_PC18 (1 << 18) // Pin Controlled by PC18
+#define AT91C_PC18_D18 (AT91C_PIO_PC18) // Data Bus [18]
+#define AT91C_PC18_TCLK2 (AT91C_PIO_PC18) // Timer Counter 2 external clock input
+#define AT91C_PIO_PC19 (1 << 19) // Pin Controlled by PC19
+#define AT91C_PC19_D19 (AT91C_PIO_PC19) // Data Bus [19]
+#define AT91C_PC19_TIOA0 (AT91C_PIO_PC19) // Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PC2 (1 << 2) // Pin Controlled by PC2
+#define AT91C_PC2_NWAIT (AT91C_PIO_PC2) // NWAIT
+#define AT91C_PC2_IRQ0 (AT91C_PIO_PC2) // Interrupt input 0
+#define AT91C_PIO_PC20 (1 << 20) // Pin Controlled by PC20
+#define AT91C_PC20_D20 (AT91C_PIO_PC20) // Data Bus [20]
+#define AT91C_PC20_TIOB0 (AT91C_PIO_PC20) // Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PC21 (1 << 21) // Pin Controlled by PC21
+#define AT91C_PC21_D21 (AT91C_PIO_PC21) // Data Bus [21]
+#define AT91C_PC21_TIOA1 (AT91C_PIO_PC21) // Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PC22 (1 << 22) // Pin Controlled by PC22
+#define AT91C_PC22_D22 (AT91C_PIO_PC22) // Data Bus [22]
+#define AT91C_PC22_TIOB1 (AT91C_PIO_PC22) // Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PC23 (1 << 23) // Pin Controlled by PC23
+#define AT91C_PC23_D23 (AT91C_PIO_PC23) // Data Bus [23]
+#define AT91C_PC23_TIOA2 (AT91C_PIO_PC23) // Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PC24 (1 << 24) // Pin Controlled by PC24
+#define AT91C_PC24_D24 (AT91C_PIO_PC24) // Data Bus [24]
+#define AT91C_PC24_TIOB2 (AT91C_PIO_PC24) // Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PC25 (1 << 25) // Pin Controlled by PC25
+#define AT91C_PC25_D25 (AT91C_PIO_PC25) // Data Bus [25]
+#define AT91C_PC25_TF2 (AT91C_PIO_PC25) // SSC2 Transmit Frame Sync
+#define AT91C_PIO_PC26 (1 << 26) // Pin Controlled by PC26
+#define AT91C_PC26_D26 (AT91C_PIO_PC26) // Data Bus [26]
+#define AT91C_PC26_TK2 (AT91C_PIO_PC26) // SSC2 Transmit Clock
+#define AT91C_PIO_PC27 (1 << 27) // Pin Controlled by PC27
+#define AT91C_PC27_D27 (AT91C_PIO_PC27) // Data Bus [27]
+#define AT91C_PC27_TD2 (AT91C_PIO_PC27) // SSC2 Transmit Data
+#define AT91C_PIO_PC28 (1 << 28) // Pin Controlled by PC28
+#define AT91C_PC28_D28 (AT91C_PIO_PC28) // Data Bus [28]
+#define AT91C_PC28_RD2 (AT91C_PIO_PC28) // SSC2 Receive Data
+#define AT91C_PIO_PC29 (1 << 29) // Pin Controlled by PC29
+#define AT91C_PC29_D29 (AT91C_PIO_PC29) // Data Bus [29]
+#define AT91C_PC29_RK2 (AT91C_PIO_PC29) // SSC2 Receive Clock
+#define AT91C_PIO_PC3 (1 << 3) // Pin Controlled by PC3
+#define AT91C_PC3_A25_CFRNW (AT91C_PIO_PC3) // Address Bus[25] / Compact Flash Read Not Write
+#define AT91C_PIO_PC30 (1 << 30) // Pin Controlled by PC30
+#define AT91C_PC30_D30 (AT91C_PIO_PC30) // Data Bus [30]
+#define AT91C_PC30_RF2 (AT91C_PIO_PC30) // SSC2 Receive Frame Sync
+#define AT91C_PIO_PC31 (1 << 31) // Pin Controlled by PC31
+#define AT91C_PC31_D31 (AT91C_PIO_PC31) // Data Bus [31]
+#define AT91C_PC31_PCK1 (AT91C_PIO_PC31) // PMC Programmable clock Output 1
+#define AT91C_PIO_PC4 (1 << 4) // Pin Controlled by PC4
+#define AT91C_PC4_NCS4_CFCS0 (AT91C_PIO_PC4) // Chip Select 4 / CompactFlash Chip Select 0
+#define AT91C_PIO_PC5 (1 << 5) // Pin Controlled by PC5
+#define AT91C_PC5_NCS5_CFCS1 (AT91C_PIO_PC5) // Chip Select 5 / CompactFlash Chip Select 1
+#define AT91C_PIO_PC6 (1 << 6) // Pin Controlled by PC6
+#define AT91C_PC6_CFCE1 (AT91C_PIO_PC6) // CompactFlash Chip Enable 1
+#define AT91C_PIO_PC7 (1 << 7) // Pin Controlled by PC7
+#define AT91C_PC7_CFCE2 (AT91C_PIO_PC7) // CompactFlash Chip Enable 2
+#define AT91C_PIO_PC8 (1 << 8) // Pin Controlled by PC8
+#define AT91C_PC8_TXD0 (AT91C_PIO_PC8) // USART0 Transmit Data
+#define AT91C_PC8_PCK2 (AT91C_PIO_PC8) // PMC Programmable clock Output 2
+#define AT91C_PIO_PC9 (1 << 9) // Pin Controlled by PC9
+#define AT91C_PC9_RXD0 (AT91C_PIO_PC9) // USART0 Receive Data
+#define AT91C_PC9_PCK3 (AT91C_PIO_PC9) // PMC Programmable clock Output 3
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91SAM9G10
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Interrupt
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
+#define AT91C_ID_PIOC ( 4) // Parallel IO Controller C
+#define AT91C_ID_US0 ( 6) // USART 0
+#define AT91C_ID_US1 ( 7) // USART 1
+#define AT91C_ID_US2 ( 8) // USART 2
+#define AT91C_ID_MCI ( 9) // Multimedia Card Interface
+#define AT91C_ID_UDP (10) // USB Device Port
+#define AT91C_ID_TWI (11) // Two-Wire Interface
+#define AT91C_ID_SPI0 (12) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1 (13) // Serial Peripheral Interface 1
+#define AT91C_ID_SSC0 (14) // Serial Synchronous Controller 0
+#define AT91C_ID_SSC1 (15) // Serial Synchronous Controller 1
+#define AT91C_ID_SSC2 (16) // Serial Synchronous Controller 2
+#define AT91C_ID_TC0 (17) // Timer Counter 0
+#define AT91C_ID_TC1 (18) // Timer Counter 1
+#define AT91C_ID_TC2 (19) // Timer Counter 2
+#define AT91C_ID_UHP (20) // USB Host Port
+#define AT91C_ID_LCDC (21) // LCD Controller
+#define AT91C_ID_IRQ0 (29) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (30) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ID_IRQ2 (31) // Advanced Interrupt Controller (IRQ2)
+#define AT91C_ALL_INT (0xE03FFFDF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91SAM9G10
+// *****************************************************************************
+#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFEA00) // (SYS) Base Address
+#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address
+#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address
+#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address
+#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_PIOC (AT91_CAST(AT91PS_PIO) 0xFFFFF800) // (PIOC) Base Address
+#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB0 (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB0) Base Address
+#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address
+#define AT91C_BASE_PDC_MCI (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_MCI) Base Address
+#define AT91C_BASE_MCI (AT91_CAST(AT91PS_MCI) 0xFFFA8000) // (MCI) Base Address
+#define AT91C_BASE_TWI (AT91_CAST(AT91PS_TWI) 0xFFFAC000) // (TWI) Base Address
+#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US2 (AT91_CAST(AT91PS_PDC) 0xFFFB8100) // (PDC_US2) Base Address
+#define AT91C_BASE_US2 (AT91_CAST(AT91PS_USART) 0xFFFB8000) // (US2) Base Address
+#define AT91C_BASE_PDC_SSC0 (AT91_CAST(AT91PS_PDC) 0xFFFBC100) // (PDC_SSC0) Base Address
+#define AT91C_BASE_SSC0 (AT91_CAST(AT91PS_SSC) 0xFFFBC000) // (SSC0) Base Address
+#define AT91C_BASE_PDC_SSC1 (AT91_CAST(AT91PS_PDC) 0xFFFC0100) // (PDC_SSC1) Base Address
+#define AT91C_BASE_SSC1 (AT91_CAST(AT91PS_SSC) 0xFFFC0000) // (SSC1) Base Address
+#define AT91C_BASE_PDC_SSC2 (AT91_CAST(AT91PS_PDC) 0xFFFC4100) // (PDC_SSC2) Base Address
+#define AT91C_BASE_SSC2 (AT91_CAST(AT91PS_SSC) 0xFFFC4000) // (SSC2) Base Address
+#define AT91C_BASE_PDC_SPI0 (AT91_CAST(AT91PS_PDC) 0xFFFC8100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0 (AT91_CAST(AT91PS_SPI) 0xFFFC8000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_SPI1 (AT91_CAST(AT91PS_PDC) 0xFFFCC100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1 (AT91_CAST(AT91PS_SPI) 0xFFFCC000) // (SPI1) Base Address
+#define AT91C_BASE_UHP (AT91_CAST(AT91PS_UHP) 0x00500000) // (UHP) Base Address
+#define AT91C_BASE_LCDC (AT91_CAST(AT91PS_LCDC) 0x00600000) // (LCDC) Base Address
+#define AT91C_BASE_LCDC_16B_TFT (AT91_CAST(AT91PS_LCDC) 0x00600000) // (LCDC_16B_TFT) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91SAM9G10
+// *****************************************************************************
+// ITCM
+#define AT91C_ITCM (0x00100000) // Maximum ITCM Area base address
+#define AT91C_ITCM_SIZE (0x00010000) // Maximum ITCM Area size in byte (64 Kbytes)
+// DTCM
+#define AT91C_DTCM (0x00200000) // Maximum DTCM Area base address
+#define AT91C_DTCM_SIZE (0x00010000) // Maximum DTCM Area size in byte (64 Kbytes)
+// IRAM
+#define AT91C_IRAM (0x00300000) // Maximum Internal SRAM base address
+#define AT91C_IRAM_SIZE (0x00004000) // Maximum Internal SRAM size in byte (16 Kbytes)
+// IRAM_MIN
+#define AT91C_IRAM_MIN (0x00300000) // Minimum Internal RAM base address
+#define AT91C_IRAM_MIN_SIZE (0x00008000) // Minimum Internal RAM size in byte (32 Kbytes)
+// IROM
+#define AT91C_IROM (0x00400000) // Internal ROM base address
+#define AT91C_IROM_SIZE (0x00008000) // Internal ROM size in byte (32 Kbytes)
+// EBI_CS0
+#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM_16BIT
+#define AT91C_EBI_SDRAM_16BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_16BIT_SIZE (0x02000000) // SDRAM on EBI Chip Select 1 size in byte (32768 Kbytes)
+// EBI_SDRAM_32BIT
+#define AT91C_EBI_SDRAM_32BIT (0x20000000) // SDRAM on EBI Chip Select 1 base address
+#define AT91C_EBI_SDRAM_32BIT_SIZE (0x04000000) // SDRAM on EBI Chip Select 1 size in byte (65536 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM (0x40000000) // SmartMedia on Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on Chip Select 5 base address
+#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CS6
+#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
+#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
+// EBI_CS7
+#define AT91C_EBI_CS7 (0x80000000) // EBI Chip Select 7 base address
+#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
+
+#endif
diff --git a/boards/at91sam9g10-ek/at91sam9g10/chip.h b/boards/at91sam9g10-ek/at91sam9g10/chip.h new file mode 100644 index 0000000..46e08fa --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/chip.h @@ -0,0 +1,114 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+/// Definition of AT91SAM9G10 characteristics and features
+///
+/// !Usage
+/// -# For ARM core feature, see "AT91SAM9G10 - ARM core features".
+/// -# For IP features, see "AT91SAM9G10 - IP features".
+/// -# For misc, see "AT91SAM9G10 - Misc".
+//------------------------------------------------------------------------------
+
+#ifndef CHIP_H
+#define CHIP_H
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "AT91SAM9G10 - ARM core features"
+/// This page lists several characteristics related to the ARM core
+///
+
+//ARM core features
+
+/// ARM core definition.
+#define arm926ej_s
+
+/// family definition.
+//#define at91sam9g10 (already defined)
+
+/// temporary define, to be removed
+#define CP15_PRESENT
+
+//------------------------------------------------------------------------------
+/// \page "AT91SAM9G10 - IP features"
+/// This page lists several characteristics related to the embedded IP
+///
+
+//IP FEATURES
+
+/// Indicates chip has an UDP Full Speed.
+#define CHIP_USB_UDP
+
+/// Indicates chip has an Host Full Speed.
+#define CHIP_USB_UHP_OHCI
+
+/// Indicates chip has an internal pull-up set by matrix.
+#define CHIP_USB_PULLUP_MATRIX
+
+/// Number of USB endpoints
+#define CHIP_USB_NUMENDPOINTS 6
+
+/// Endpoints max paxcket size
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \
+ ((i == 0) ? 8 : \
+ ((i == 1) ? 64 : \
+ ((i == 2) ? 64 : \
+ ((i == 3) ? 64 : \
+ ((i == 4) ? 256 : \
+ ((i == 5) ? 256 : 0 ))))))
+
+/// Endpoints Number of Bank
+#define CHIP_USB_ENDPOINTS_BANKS(i) \
+ ((i == 0) ? 1 : \
+ ((i == 1) ? 2 : \
+ ((i == 2) ? 2 : \
+ ((i == 3) ? 1 : \
+ ((i == 4) ? 2 : \
+ ((i == 5) ? 2 : 0 ))))))
+
+//------------------------------------------------------------------------------
+/// \page "AT91SAM9G10 - Misc "
+/// This page lists misc features
+///
+
+//Misc
+
+#endif //#ifndef CHIP_H
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/chip.mak b/boards/at91sam9g10-ek/at91sam9g10/chip.mak new file mode 100644 index 0000000..37ca43a --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/chip.mak @@ -0,0 +1,34 @@ +# ----------------------------------------------------------------------------
+# ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2008, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# Defines which are the specific available IP for the chip AT91SAM9G10
+CHIP_CORE = arm926ej_s
+CHIP_IP_MCI = MCI_PDC
+CHIP_IP_UDP = USB_UDP
+CHIP_IP_UHP = USB_OHCI
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/norflash.icf b/boards/at91sam9g10-ek/at91sam9g10/norflash.icf new file mode 100644 index 0000000..fdb4bf3 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/norflash.icf @@ -0,0 +1,53 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_NOR_start__ = 0x10000000;
+define symbol __ICFEDIT_region_NOR_end__ = 0x1FFFFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__ = 0x100;
+define symbol __ICFEDIT_size_lowlevel__ = 0x400;
+define symbol __ICFEDIT_size_vectors__ = 0x100;
+define symbol __ICFEDIT_size_cstack__ = 0x800;
+define symbol __ICFEDIT_size_sysstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_NOR_start__;
+export symbol __ICFEDIT_region_NOR_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_sysstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region = mem:[from __ICFEDIT_region_NOR_start__ size __ICFEDIT_size_startup__];
+define region OBJ_region = mem:[from __ICFEDIT_region_NOR_start__+__ICFEDIT_size_startup__ size __ICFEDIT_size_lowlevel__];
+define region NOR_region = mem:[from __ICFEDIT_region_NOR_start__+__ICFEDIT_size_startup__ + __ICFEDIT_size_lowlevel__ to __ICFEDIT_region_NOR_end__];
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { readwrite };
+initialize by copy { section .vectors };
+initialize by copy { object board_lowlevel.o,object board_memories.o };
+do not initialize { section .noinit };
+
+place in STA_region { section .cstartup };
+place in OBJ_region { object board_lowlevel.o,object board_memories.o };
+place in NOR_region { readonly };
+place in VEC_region { section .vectors };
+place in RAM_region { readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/norflash.lds b/boards/at91sam9g10-ek/at91sam9g10/norflash.lds new file mode 100644 index 0000000..be4438c --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/norflash.lds @@ -0,0 +1,91 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in internal SRAM on the AT91SAM9G10
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x00300000, LENGTH = 16K
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 64M
+ ebi_cs0 (RX) : ORIGIN = 0x10000000, LENGTH = 256M
+}
+
+SECTIONS
+{
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ *board_lowlevel.o(.text*)
+ *board_memories.o(.text*)
+ . = ALIGN(4);
+ _eprerelocate = .;
+ } >sram
+
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed = .;
+ } >ebi_cs0
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ *(.vectors)
+ *(.ramfunc)
+ *(.data)
+ . = ALIGN(4);
+ _epostrelocate = .;
+ } >sram
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sram
+
+ _sstack = 0x304000;
+}
+end = .;
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/norflash.sct b/boards/at91sam9g10-ek/at91sam9g10/norflash.sct new file mode 100644 index 0000000..1a0bbd4 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/norflash.sct @@ -0,0 +1,53 @@ +; * ----------------------------------------------------------------------------
+; * ATMEL Microcontroller Software Support
+; * ----------------------------------------------------------------------------
+; * Copyright (c) 2008, Atmel Corporation
+; *
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *
+; * - Redistributions of source code must retain the above copyright notice,
+; * this list of conditions and the disclaimer below.
+; *
+; * Atmel's name may not be used to endorse or promote products derived from
+; * this software without specific prior written permission.
+; *
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * ----------------------------------------------------------------------------
+
+; *------------------------------------------------------------------------------
+; * Linker scatter for running in norflash on the AT91SAM9G10
+; *----------------------------------------------------------------------------*/
+
+Load_region 0x10000000 0x10000000 {
+
+ Fixed_region 0x10000000 {
+ *(cstartup +First)
+ .ANY (+RO)
+ }
+
+ Relocate_region 0x300000 0x4000 {
+ *.o (VECTOR, +First)
+ board_lowlevel.o (+RO)
+ board_memories.o (+RO)
+ .ANY (+RW +ZI)
+ }
+
+ ARM_LIB_HEAP 0x303000 EMPTY 0x800 {
+ }
+
+ ARM_LIB_STACK 0x304000 EMPTY -0x800 {
+ }
+
+}
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sdram.icf b/boards/at91sam9g10-ek/at91sam9g10/sdram.icf new file mode 100644 index 0000000..8b3fe00 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sdram.icf @@ -0,0 +1,46 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_SDRAM_end__ = 0x23FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__ = 0x100;
+define symbol __ICFEDIT_size_vectors__ = 0x100;
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_sysstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_SDRAM_start__;
+export symbol __ICFEDIT_region_SDRAM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_startup__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_sysstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { section .vectors };
+do not initialize { section .noinit };
+
+place in STA_region { section .cstartup };
+place in VEC_region { section .vectors };
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sdram.lds b/boards/at91sam9g10-ek/at91sam9g10/sdram.lds new file mode 100644 index 0000000..1ba9036 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sdram.lds @@ -0,0 +1,88 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in external SDRAM on the AT91SAM9G10
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x300000, LENGTH = 0x4000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.data)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed = .;
+ } >sdram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ *(.vectors);
+ *(.ramfunc)
+ . = ALIGN(4);
+ _epostrelocate = .;
+ } >sram
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sdram
+
+ _sstack = 0x24000000;
+}
+end = .;
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sdram.sct b/boards/at91sam9g10-ek/at91sam9g10/sdram.sct new file mode 100644 index 0000000..abe6160 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sdram.sct @@ -0,0 +1,49 @@ +; * ----------------------------------------------------------------------------
+; * ATMEL Microcontroller Software Support
+; * ----------------------------------------------------------------------------
+; * Copyright (c) 2008, Atmel Corporation
+; *
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *
+; * - Redistributions of source code must retain the above copyright notice,
+; * this list of conditions and the disclaimer below.
+; *
+; * Atmel's name may not be used to endorse or promote products derived from
+; * this software without specific prior written permission.
+; *
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * ----------------------------------------------------------------------------
+
+; *------------------------------------------------------------------------------
+; * Linker scatter for running in external SDRAM on the AT91SAM9G10
+; *----------------------------------------------------------------------------*/
+
+Load_region 0x20000000 0x4000000 {
+
+ Fixed_region 0x20000000 {
+ *(cstartup +First)
+ .ANY (+RO +RW +ZI)
+ }
+
+ Relocate_region 0x300000 0x4000 {
+ *.o (VECTOR, +First)
+ }
+
+ ARM_LIB_HEAP 0x23FFE000 EMPTY 0x1000 {
+ }
+
+ ARM_LIB_STACK 0x24000000 EMPTY -0x1000 {
+ }
+}
\ No newline at end of file diff --git a/boards/at91sam9g10-ek/at91sam9g10/sdram_flashloader.icf b/boards/at91sam9g10-ek/at91sam9g10/sdram_flashloader.icf new file mode 100644 index 0000000..936224f --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sdram_flashloader.icf @@ -0,0 +1,45 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x00000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0;
+define symbol __ICFEDIT_region_ROM_end__ = 0x0;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x20FFFFFF;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x200;
+define symbol __ICFEDIT_size_svcstack__ = 0x0;
+define symbol __ICFEDIT_size_irqstack__ = 0x0;
+define symbol __ICFEDIT_size_fiqstack__ = 0x0;
+define symbol __ICFEDIT_size_undstack__ = 0x0;
+define symbol __ICFEDIT_size_abtstack__ = 0x0;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+/**** End of ICF editor section. ###ICF###*/
+
+
+define memory mem with size = 4G;
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
+define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
+define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+//initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__ICFEDIT_intvec_start__ {section .intvec };
+
+place at start of RAM_region { block RamTop with fixed order {readonly, section LOWEND}};
+place at end of RAM_region { block RamBottom with fixed order {section HIGHSTART, readwrite, section .noinit,
+ block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
+ block UND_STACK, block ABT_STACK, block HEAP}};
+
+
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sdram_samba.lds b/boards/at91sam9g10-ek/at91sam9g10/sdram_samba.lds new file mode 100644 index 0000000..ba78d7f --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sdram_samba.lds @@ -0,0 +1,91 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in external SDRAM on the AT91SAM9G10
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x300000, LENGTH = 0x4000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.data)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed = .;
+ } >sdram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ *(.vectors);
+ . = ALIGN(4);
+ _epostrelocate = .;
+ } >sram
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sdram
+
+ _sstack = 0x24000000;
+}
+end = .;
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sram.icf b/boards/at91sam9g10-ek/at91sam9g10/sram.icf new file mode 100644 index 0000000..a2b8a57 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sram.icf @@ -0,0 +1,36 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x300000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x303FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_vectors__ = 0x100;
+define symbol __ICFEDIT_size_cstack__ = 0x1000;
+define symbol __ICFEDIT_size_sysstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+/*-Exports-*/
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_sysstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
+define block SYS_STACK with alignment = 8, size = __ICFEDIT_size_sysstack__ { };
+define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
+
+do not initialize { section .noinit };
+
+place in VEC_region { section .vectors };
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SYS_STACK, block CSTACK, block HEAP };
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sram.lds b/boards/at91sam9g10-ek/at91sam9g10/sram.lds new file mode 100644 index 0000000..2ec67fd --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sram.lds @@ -0,0 +1,101 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2006, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in internal SRAM on the AT91SAM9G10
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x300000, LENGTH = 0x4000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed0 :
+ {
+ . = ALIGN(4);
+ _sfixed0 = .;
+ *(.vectors)
+ *(.ramfunc)
+ *(.text*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed0 = .;
+ _efixed = .;
+ } >sram
+
+ .fixed1 :
+ {
+ . = ALIGN(4);
+ _sfixed1 = .;
+ *(.rodata*)
+ *(.data)
+ . = ALIGN(4);
+ _efixed1 = .;
+ } >sram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ . = ALIGN(4);
+ _epostrelocate = .;
+ }
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sram
+
+ _sstack = 0x304000;
+}
+end = .;
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sram.sct b/boards/at91sam9g10-ek/at91sam9g10/sram.sct new file mode 100644 index 0000000..faf3718 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sram.sct @@ -0,0 +1,53 @@ +; * ----------------------------------------------------------------------------
+; * ATMEL Microcontroller Software Support
+; * ----------------------------------------------------------------------------
+; * Copyright (c) 2008, Atmel Corporation
+; *
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *
+; * - Redistributions of source code must retain the above copyright notice,
+; * this list of conditions and the disclaimer below.
+; *
+; * Atmel's name may not be used to endorse or promote products derived from
+; * this software without specific prior written permission.
+; *
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * ----------------------------------------------------------------------------
+
+; *------------------------------------------------------------------------------
+; * Linker scatter for running in internal SRAM on the AT91SAM9G10
+; *----------------------------------------------------------------------------*/
+
+Load_region 0x300000 0x4000 {
+
+ Fixed_region 0x300000 {
+ *.o (VECTOR, +First)
+ .ANY (+RO)
+ }
+
+ Relocate_region +0 {
+ *(cstartup +First)
+ .ANY (+RW +ZI)
+ }
+
+ ScatterAssert((ImageLength(Fixed_region) + ImageLength(Relocate_region)) < 0x3000)
+
+ ARM_LIB_HEAP 0x303000 EMPTY 0x800 {
+ }
+
+ ARM_LIB_STACK 0x304000 EMPTY -0x800 {
+ }
+}
+
diff --git a/boards/at91sam9g10-ek/at91sam9g10/sram_samba.lds b/boards/at91sam9g10-ek/at91sam9g10/sram_samba.lds new file mode 100644 index 0000000..cb17d72 --- /dev/null +++ b/boards/at91sam9g10-ek/at91sam9g10/sram_samba.lds @@ -0,0 +1,101 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in internal SRAM on the AT91SAM9G10
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ romcodesram (W!RX) : ORIGIN = 0x300000, LENGTH = 0x1000
+ sram (W!RX) : ORIGIN = 0x301000, LENGTH = 0x3000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed0 :
+ {
+ . = ALIGN(4);
+ _sfixed0 = .;
+ *(.vectors)
+ *(.text*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed0 = .;
+ _efixed = .;
+ } >sram
+
+ .fixed1 :
+ {
+ . = ALIGN(4);
+ _sfixed1 = .;
+ *(.rodata*)
+ *(.data)
+ . = ALIGN(4);
+ _efixed1 = .;
+ } >sram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ . = ALIGN(4);
+ _epostrelocate = .;
+ }
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sram
+
+ _sstack = 0x304000;
+}
+end = .;
+
diff --git a/boards/at91sam9g10-ek/board.h b/boards/at91sam9g10-ek/board.h new file mode 100644 index 0000000..69aa813 --- /dev/null +++ b/boards/at91sam9g10-ek/board.h @@ -0,0 +1,494 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+/// Definition and functions for using AT91SAM9G10-related features, such
+/// has PIO pins, memories, etc.
+///
+/// !Usage
+/// -# The code for booting the board is provided by board_cstartup.S and
+/// board_lowlevel.c.
+/// -# For using board PIOs, board characteristics (clock, etc.) and external
+/// components, see board.h.
+/// -# For manipulating memories (remapping, SDRAM, etc.), see board_memories.h.
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+/// Definition of AT91SAM9G10-EK characteristics, AT91SAM9G10-dependant PIOs and
+/// external components interfacing.
+///
+/// !Usage
+/// -# For operating frequency information, see "SAM9G10-EK - Operating frequencies".
+/// -# For using portable PIO definitions, see "SAM9G10-EK - PIO definitions".
+/// -# Several USB definitions are included here (see "SAM9G10-EK - USB device").
+/// -# For external components definitions, see "SAM9G10-EK - External components".
+/// -# For memory-related definitions, see "SAM9G10-EK - Memories".
+//------------------------------------------------------------------------------
+
+#ifndef BOARD_H
+#define BOARD_H
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#if defined(at91sam9g10)
+ #include "at91sam9g10/chip.h"
+ #include "at91sam9g10/AT91SAM9G10.h"
+#else
+ #error Board does not support the specified chip.
+#endif
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - Board Description"
+/// This page lists several definition related to the board description.
+///
+/// !Definitions
+/// - BOARD_NAME
+
+/// Name of the board.
+#define BOARD_NAME "AT91SAM9G10-EK"
+/// Board definition.
+#define at91sam9g10ek
+
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - Operating frequencies"
+/// This page lists several definition related to the board operating frequency
+/// (when using the initialization done by board_lowlevel.c).
+///
+/// !Definitions
+/// - BOARD_MAINOSC
+/// - BOARD_MCK
+
+/// Frequency of the board main oscillator.
+#define BOARD_MAINOSC 18432000
+
+/// Master clock frequency (when using board_lowlevel.c).
+#define BOARD_MCK ((18432000 * 101 / 7) / 2)
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - USB device"
+///
+/// !Constants
+/// - BOARD_USB_BMATTRIBUTES
+
+/// USB attributes configuration descriptor (bus or self powered, remote wakeup)
+#define BOARD_USB_BMATTRIBUTES USBConfigurationDescriptor_SELFPOWERED_NORWAKEUP
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - PIO definitions"
+/// This pages lists all the pio definitions contained in board.h. The constants
+/// are named using the following convention: PIN_* for a constant which defines
+/// a single Pin instance (but may include several PIOs sharing the same
+/// controller), and PINS_* for a list of Pin instances.
+///
+/// !DBGU
+/// - PINS_DBGU
+///
+/// !LEDs
+/// - PIN_LED_0
+/// - PIN_LED_1
+/// - PIN_LED_2
+/// - PINS_LEDS
+/// - LED_POWER
+/// - LED_DS1
+/// - LED_DS2
+///
+/// !Push buttons
+/// - PIN_PUSHBUTTON_1
+/// - PIN_PUSHBUTTON_2
+/// - PIN_PUSHBUTTON_3
+/// - PIN_PUSHBUTTON_4
+/// - PINS_PUSHBUTTONS
+/// - PUSHBUTTON_BP1
+/// - PUSHBUTTON_BP2
+/// - PUSHBUTTON_BP3
+/// - PUSHBUTTON_BP4
+/// - JOYSTICK_LEFT
+/// - JOYSTICK_RIGHT
+///
+/// !SPI0
+/// - PIN_SPI0_MISO
+/// - PIN_SPI0_MOSI
+/// - PIN_SPI0_SPCK
+/// - PINS_SPI0
+/// - PIN_SPI0_NPCS0
+/// - PIN_SPI0_NPCS2
+/// - PIN_SPI0_NPCS3
+///
+/// !SSC
+/// - PINS_SSC_TX
+///
+/// !USB
+/// - PIN_USB_VBUS
+
+/// List of all DBGU pin definitions.
+#define PINS_DBGU {(1<<9) | (1<<10), AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// LED #0 pin definition.
+#define PIN_LED_0 {1 << 23, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_0, PIO_DEFAULT}
+/// LED #1 pin definition.
+#define PIN_LED_1 {1 << 13, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+/// LED #2 pin definition.
+#define PIN_LED_2 {1 << 14, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+/// List of all LED pins definitions.
+#define PINS_LEDS PIN_LED_0, PIN_LED_1, PIN_LED_2
+/// Power LED index.
+#define LED_POWER 0
+/// DS1 LED index.
+#define LED_DS1 1
+/// DS2 LED index.
+#define LED_DS2 2
+
+/// Push button #1 pin definition.
+#define PIN_PUSHBUTTON_1 {1 << 27, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// Push button #2 pin definition.
+#define PIN_PUSHBUTTON_2 {1 << 26, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// Push button #3 pin definition.
+#define PIN_PUSHBUTTON_3 {1 << 25, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// Push button #4 pin definition.
+#define PIN_PUSHBUTTON_4 {1 << 24, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_PULLUP}
+/// List of all pushbutton pins definitions.
+#define PINS_PUSHBUTTONS PIN_PUSHBUTTON_1, PIN_PUSHBUTTON_2, PIN_PUSHBUTTON_3, PIN_PUSHBUTTON_4
+/// Push button #1 index.
+#define PUSHBUTTON_BP1 0
+/// Push button #2 index.
+#define PUSHBUTTON_BP2 1
+/// Push button #3 index.
+#define PUSHBUTTON_BP3 2
+/// Push button #4 index.
+#define PUSHBUTTON_BP4 3
+/// Simulated joystick LEFT index.
+#define JOYSTICK_LEFT 0
+/// Simulated joystick RIGHT index.
+#define JOYSTICK_RIGHT 1
+
+/// SPI0 MISO pin definition.
+#define PIN_SPI0_MISO {1 << 0, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+/// SPI0 MOSI pin definition.
+#define PIN_SPI0_MOSI {1 << 1, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+/// SPI0 SPCK pin definition.
+#define PIN_SPI0_SPCK {1 << 2, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+/// SPI0 chip select 0 pin definition.
+#define PIN_SPI0_NPCS0 {1 << 3, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+/// SPI0 chip select 2 pin definition.
+#define PIN_SPI0_NPCS2_PA5 {1 << 5, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+#define PIN_SPI0_NPCS2_PA28 {1 << 28, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_PULLUP}
+/// SPI0 chip select 3 pin definition.
+#define PIN_SPI0_NPCS3 {1 << 6, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_PULLUP}
+/// List of SPI0 pin definitions (MISO, MOSI & SPCK).
+#define PINS_SPI0 PIN_SPI0_MISO, PIN_SPI0_MOSI, PIN_SPI0_SPCK
+
+/// SSC transmitter pins definition.
+#define PINS_SSC_TX { (1 << 21) | (1 << 22) | (1 << 23), \
+ AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// USB VBus monitoring pin definition.
+#define PIN_USB_VBUS {1 << 29, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_INPUT, PIO_DEFAULT}
+
+/// MCI peripheral pins definition.
+#define PINS_MCI {0x00000077, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_B, PIO_DEFAULT}
+
+/// TWI pins definition.
+#define TWI_V3XX
+#define PINS_TWI {0x00000180, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_PERIPH_A, PIO_DEFAULT}
+
+/// SD boot slot
+#define BOARD_SD_BOOT_MCISLOT 0
+
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - External components"
+/// This page lists the definitions related to external on-board components
+/// located in the board.h file for the AT91SAM9G10-EK.
+///
+/// !AT45 Dataflash
+/// - BOARD_AT45_A_SPI_BASE
+/// - BOARD_AT45_A_SPI_ID
+/// - BOARD_AT45_A_SPI_PINS
+/// - BOARD_AT45_A_SPI
+/// - BOARD_AT45_A_NPCS
+/// - BOARD_AT45_A_NPCS_PIN
+///
+/// !AT26 Serial Flash
+/// - BOARD_AT26_A_SPI_BASE
+/// - BOARD_AT26_A_SPI_ID
+/// - BOARD_AT26_A_SPI_PINS
+/// - BOARD_AT26_A_SPI
+/// - BOARD_AT26_A_NPCS
+/// - BOARD_AT26_A_NPCS_PIN
+
+/// !LCD
+/// - PINS_LCD
+/// - BOARD_LCD_WIDTH
+/// - BOARD_LCD_HEIGHT
+/// - BOARD_LCD_BPP
+/// - BOARD_LCD_IFWIDTH
+/// - BOARD_LCD_FRAMESIZE_PIXELS
+/// - BOARD_LCD_FRAMESIZE
+/// - BOARD_LCD_FRAMERATE
+/// - BOARD_LCD_PIXELCLOCK
+/// - BOARD_LCD_DISPLAYTYPE
+/// - BOARD_LCD_POLARITY_INVVD
+/// - BOARD_LCD_POLARITY_INVFRAME
+/// - BOARD_LCD_POLARITY_INVLINE
+/// - BOARD_LCD_POLARITY_INVCLK
+/// - BOARD_LCD_POLARITY_INVDVAL
+/// - BOARD_LCD_CLOCKMODE
+/// - BOARD_LCD_TIMING_VFP
+/// - BOARD_LCD_TIMING_VBP
+/// - BOARD_LCD_TIMING_VPW
+/// - BOARD_LCD_TIMING_VHDLY
+/// - BOARD_LCD_TIMING_HFP
+/// - BOARD_LCD_TIMING_HBP
+/// - BOARD_LCD_TIMING_HPW
+///
+/// !TouchScreen
+/// - BOARD_TSC_ADS7843
+/// - PIN_TCS_IRQ
+/// - PIN_TCS_BUSY
+/// - BOARD_TSC_SPI_BASE
+/// - BOARD_TSC_SPI_ID
+/// - BOARD_TSC_SPI_PINS
+/// - BOARD_TSC_NPCS
+/// - BOARD_TSC_NPCS_PIN
+///
+/// !SD Card
+/// - BOARD_SD_MCI_BASE
+/// - BOARD_SD_MCI_ID
+/// - BOARD_SD_PINS
+/// - BOARD_SD_PIN_CD
+/// - BOARD_SD_PIN_WP
+/// - BOARD_SD_SLOT
+///
+/// !SD Card SPI
+/// - BOARD_SD_SPI_BASE
+/// - BOARD_SD_SPI_ID
+/// - BOARD_SD_SPI_PINS
+/// - BOARD_SD_NPCS
+///
+
+/// Base address of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_BASE AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_ID AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the dataflash.
+#define BOARD_AT45_A_SPI_PINS PINS_SPI0
+/// Dataflahs SPI number.
+#define BOARD_AT45_A_SPI 0
+/// Chip select connected to the dataflash.
+#define BOARD_AT45_A_NPCS 0
+/// Chip select pin connected to the dataflash.
+#define BOARD_AT45_A_NPCS_PIN PIN_SPI0_NPCS0
+
+/// Base address of SPI peripheral connected to the serialflash.
+#define BOARD_AT26_A_SPI_BASE AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the serialflash.
+#define BOARD_AT26_A_SPI_ID AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the serialflash.
+#define BOARD_AT26_A_SPI_PINS PINS_SPI0
+/// Serialflash SPI number.
+#define BOARD_AT26_A_SPI 0
+/// Chip select connected to the serialflash.
+#define BOARD_AT26_A_NPCS 3
+/// Chip select pin connected to the serialflash.
+#define BOARD_AT26_A_NPCS_PIN PIN_SPI0_NPCS3
+
+/// LCD pins list.
+#define PINS_LCD \
+ {0x001F9F9E, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_A, PIO_DEFAULT}, \
+ {0x1F800000, AT91C_BASE_PIOB, AT91C_ID_PIOB, PIO_PERIPH_B, PIO_DEFAULT}, \
+ {1 << 12, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_OUTPUT_1, PIO_DEFAULT}
+/// Board is wired in BGR 565.
+#define BOARD_LCD_BGR565
+/// Display width in pixels.
+#define BOARD_LCD_WIDTH 240
+/// Display height in pixels.
+#define BOARD_LCD_HEIGHT 320
+/// Display resolution in bits per pixel (bpp).
+#define BOARD_LCD_BPP AT91C_LCDC_PIXELSIZE_TWENTYFOURBITSPERPIXEL
+/// Display interface width in bits.
+#define BOARD_LCD_IFWIDTH 24
+/// Frame size in pixels (height * width * bpp).
+#define BOARD_LCD_FRAMESIZE_PIXELS (BOARD_LCD_WIDTH * BOARD_LCD_HEIGHT * 24)
+/// Frame size in words (height * width * bpp / 32)
+#define BOARD_LCD_FRAMESIZE (BOARD_LCD_FRAMESIZE_PIXELS / 32)
+/// Frame rate in Hz.
+#define BOARD_LCD_FRAMERATE 60
+/// Pixel clock rate in Hz (frameSize * frameRate / interfaceWidth).
+#define BOARD_LCD_PIXELCLOCK (BOARD_LCD_FRAMESIZE_PIXELS * BOARD_LCD_FRAMERATE / BOARD_LCD_IFWIDTH)
+/// LCD display type.
+#define BOARD_LCD_DISPLAYTYPE AT91C_LCDC_DISTYPE_TFT
+/// LCDC polarity.
+#define BOARD_LCD_POLARITY_INVVD AT91C_LCDC_INVVD_NORMALPOL
+/// LCDVSYNC polarity.
+#define BOARD_LCD_POLARITY_INVFRAME AT91C_LCDC_INVFRAME_NORMALPOL
+/// LCDHSYNC polarity.
+#define BOARD_LCD_POLARITY_INVLINE AT91C_LCDC_INVLINE_NORMALPOL
+/// LCDDOTCLK polarity.
+#define BOARD_LCD_POLARITY_INVCLK AT91C_LCDC_INVCLK_NORMALPOL
+/// LCDDEN polarity.
+#define BOARD_LCD_POLARITY_INVDVAL AT91C_LCDC_INVDVAL_NORMALPOL
+/// Pixel clock mode.
+#define BOARD_LCD_CLOCKMODE AT91C_LCDC_CLKMOD_ALWAYSACTIVE
+/// Vertical front porch in number of lines.
+#define BOARD_LCD_TIMING_VFP 2
+/// Vertical back porch in number of lines.
+#define BOARD_LCD_TIMING_VBP 4
+/// Vertical pulse width in LCDDOTCLK cycles.
+#define BOARD_LCD_TIMING_VPW 1
+/// Number of cycles between VSYNC edge and HSYNC rising edge.
+#define BOARD_LCD_TIMING_VHDLY 1
+/// Horizontal front porch in LCDDOTCLK cycles.
+#define BOARD_LCD_TIMING_HFP 11
+/// Horizontal back porch in LCDDOTCLK cycles.
+#define BOARD_LCD_TIMING_HBP 17
+/// Horizontal pulse width in LCDDOTCLK cycles.
+#define BOARD_LCD_TIMING_HPW 5
+
+/// Indicates board has an ADS7843 external component to manage Touch Screen
+#define BOARD_TSC_ADS7843
+
+/// Touchscreen controller IRQ pin definition.
+#define PIN_TCS_IRQ {AT91C_PIO_PC2, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
+/// Touchscreen controller Busy pin definition.
+#define PIN_TCS_BUSY {AT91C_PIO_PA11, AT91C_BASE_PIOA, AT91C_ID_PIOA, PIO_INPUT, PIO_DEFAULT}
+
+/// Base address of SPI peripheral connected to the touchscreen controller.
+#define BOARD_TSC_SPI_BASE AT91C_BASE_SPI0
+/// Identifier of SPI peripheral connected to the touchscreen controller.
+#define BOARD_TSC_SPI_ID AT91C_ID_SPI0
+/// Pins of the SPI peripheral connected to the touchscreen controller.
+#define BOARD_TSC_SPI_PINS PINS_SPI0
+/// Chip select connected to the touchscreen controller.
+#define BOARD_TSC_NPCS 2
+/// Chip select pin connected to the touchscreen controller.
+#define BOARD_TSC_NPCS_PIN PIN_SPI0_NPCS2_PA28
+
+/// Base address of the MCI peripheral connected to the SD card.
+#define BOARD_SD_MCI_BASE AT91C_BASE_MCI
+/// Identifier of the MCI peripheral connected to the SD card.
+#define BOARD_SD_MCI_ID AT91C_ID_MCI
+/// List of pins to configure to access the SD card
+#define BOARD_SD_PINS PINS_MCI
+/// MCI slot connected to the SD card.
+#define BOARD_SD_SLOT MCI_SD_SLOTA
+
+/// Base address of the SPI peripheral connected to the SD card.
+#define BOARD_SD_SPI_BASE AT91C_BASE_SPI0
+/// Identifier of the SPI peripheral connected to the SD card.
+#define BOARD_SD_SPI_ID AT91C_ID_SPI0
+/// List of pins to configure to access the SD card
+#define BOARD_SD_SPI_PINS PINS_SPI0, PIN_SPI0_NPCS0
+/// NPCS number
+#define BOARD_SD_NPCS 0
+
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - Memories"
+/// This page lists definitions related to external on-board memories.
+///
+/// !SDRAM
+/// - BOARD_SDRAM_SIZE
+/// - PIN_SDRAM
+/// - BOARD_SDRAM_BUSWIDTH
+///
+/// !Nandflash
+/// - PINS_NANDFLASH
+/// - PIN_NF_OE
+/// - PIN_NF_WE
+/// - BOARD_NF_COMMAND_ADDR
+/// - BOARD_NF_ADDRESS_ADDR
+/// - BOARD_NF_DATA_ADDR
+/// - BOARD_NF_CE_PIN
+/// - BOARD_NF_RB_PIN
+///
+/// !NorFlash
+/// - BOARD_NORFLASH_ADDR
+/// - BOARD_NORFLASH_DFT_BUS_SIZE
+
+/// Board SDRAM size
+#define BOARD_SDRAM_SIZE (64*1024*1024) // 64 MB
+/// List of all SDRAM pins definitions.
+#define PINS_SDRAM {0xFFFF0000, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
+/// SDRAM bus width.
+#define BOARD_SDRAM_BUSWIDTH 32
+
+/// Nandflash controller peripheral pins definition.
+#define PINS_NANDFLASH PIN_NF_OE, PIN_NF_WE, BOARD_NF_CE_PIN, BOARD_NF_RB_PIN
+/// Nandflash output enable pin definition.
+#define PIN_NF_OE {1 << 0, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
+/// Nandflash write enable pin definition
+#define PIN_NF_WE {1 << 1, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_PERIPH_A, PIO_DEFAULT}
+/// Nandflash chip enable pin definition.
+#define BOARD_NF_CE_PIN {1 << 14, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_OUTPUT_1, PIO_DEFAULT}
+/// Nandflash ready/busy pin definition.
+#define BOARD_NF_RB_PIN {1 << 15, AT91C_BASE_PIOC, AT91C_ID_PIOC, PIO_INPUT, PIO_PULLUP}
+/// Address for transferring command bytes to the nandflash.
+#define BOARD_NF_COMMAND_ADDR 0x40200000
+/// Address for transferring address bytes to the nandflash.
+#define BOARD_NF_ADDRESS_ADDR 0x40400000
+/// Address for transferring data bytes to the nandflash.
+#define BOARD_NF_DATA_ADDR 0x40000000
+
+/// Address for transferring command bytes to the norflash.
+#define BOARD_NORFLASH_ADDR 0x10000000
+/// Default NOR bus size after power up reset
+#define BOARD_NORFLASH_DFT_BUS_SIZE 16
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "SAM9G10-EK - Individual chip definition"
+/// This page lists the definitions related to different chip's definition
+/// located in the board.h file for the SAM9G10-EK.
+
+/// Twi eeprom
+#define BOARD_ID_TWI_EEPROM AT91C_ID_TWI
+#define BOARD_BASE_TWI_EEPROM AT91C_BASE_TWI
+#define BOARD_PINS_TWI_EEPROM PINS_TWI
+//------------------------------------------------------------------------------
+
+#endif //#ifndef BOARD_H
+
diff --git a/boards/at91sam9g10-ek/board.mak b/boards/at91sam9g10-ek/board.mak new file mode 100644 index 0000000..95277a1 --- /dev/null +++ b/boards/at91sam9g10-ek/board.mak @@ -0,0 +1,32 @@ +# ----------------------------------------------------------------------------
+# ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2008, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# Defines which are the available memory targets for the AT91SAM9G10-EK board.
+
+MEMORIES = sdram sram
+
diff --git a/boards/at91sam9g10-ek/board_cstartup.S b/boards/at91sam9g10-ek/board_cstartup.S new file mode 100644 index 0000000..37a89b9 --- /dev/null +++ b/boards/at91sam9g10-ek/board_cstartup.S @@ -0,0 +1,189 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#include "board.h"
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+#define IRQ_STACK_SIZE 8*3*4
+
+#define ARM_MODE_ABT 0x17
+#define ARM_MODE_FIQ 0x11
+#define ARM_MODE_IRQ 0x12
+#define ARM_MODE_SVC 0x13
+
+#define I_BIT 0x80
+#define F_BIT 0x40
+
+//------------------------------------------------------------------------------
+// Startup routine
+//------------------------------------------------------------------------------
+
+ .align 4
+ .arm
+
+/* Exception vectors
+ *******************/
+ .section .vectors, "a", %progbits
+
+resetVector:
+ ldr pc, =resetHandler /* Reset */
+undefVector:
+ b undefVector /* Undefined instruction */
+swiVector:
+ b swiVector /* Software interrupt */
+prefetchAbortVector:
+ b prefetchAbortVector /* Prefetch abort */
+dataAbortVector:
+ b dataAbortVector /* Data abort */
+reservedVector:
+ b reservedVector /* Reserved for future use */
+irqVector:
+ b irqHandler /* Interrupt */
+fiqVector:
+ /* Fast interrupt */
+//------------------------------------------------------------------------------
+/// Handles a fast interrupt request by branching to the address defined in the
+/// AIC.
+//------------------------------------------------------------------------------
+fiqHandler:
+ b fiqHandler
+
+//------------------------------------------------------------------------------
+/// Handles incoming interrupt requests by branching to the corresponding
+/// handler, as defined in the AIC. Supports interrupt nesting.
+//------------------------------------------------------------------------------
+irqHandler:
+
+/* Save interrupt context on the stack to allow nesting */
+ sub lr, lr, #4
+ stmfd sp!, {lr}
+ mrs lr, SPSR
+ stmfd sp!, {r0, lr}
+
+/* Write in the IVR to support Protect Mode */
+ ldr lr, =AT91C_BASE_AIC
+ ldr r0, [r14, #AIC_IVR]
+ str lr, [r14, #AIC_IVR]
+
+/* Branch to interrupt handler in Supervisor mode */
+ msr CPSR_c, #ARM_MODE_SVC
+ stmfd sp!, {r1-r3, r4, r12, lr}
+ blx r0
+ ldmia sp!, {r1-r3, r4, r12, lr}
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT
+
+/* Acknowledge interrupt */
+ ldr lr, =AT91C_BASE_AIC
+ str lr, [r14, #AIC_EOICR]
+
+/* Restore interrupt context and branch back to calling code */
+ ldmia sp!, {r0, lr}
+ msr SPSR_cxsf, lr
+ ldmia sp!, {pc}^
+
+//------------------------------------------------------------------------------
+/// Initializes the chip and branches to the main() function.
+//------------------------------------------------------------------------------
+ .section .text
+ .global entry
+
+entry:
+resetHandler:
+
+/* Useless instruction for referencing the .vectors section */
+ ldr r0, =resetVector
+
+/* Set pc to actual code location (i.e. not in remap zone) */
+ ldr pc, =1f
+
+/* Initialize the prerelocate segment */
+1:
+ ldr r0, =_efixed
+ ldr r1, =_sprerelocate
+ ldr r2, =_eprerelocate
+1:
+ cmp r1, r2
+ ldrcc r3, [r0], #4
+ strcc r3, [r1], #4
+ bcc 1b
+
+/* Perform low-level initialization of the chip using LowLevelInit() */
+ ldr r4, =_sstack
+ mov sp, r4
+ stmfd sp!, {r0}
+ ldr r0, =LowLevelInit
+ blx r0
+
+/* Initialize the postrelocate segment */
+
+ ldmfd sp!, {r0}
+ ldr r1, =_spostrelocate
+ ldr r2, =_epostrelocate
+1:
+ cmp r1, r2
+ ldrcc r3, [r0], #4
+ strcc r3, [r1], #4
+ bcc 1b
+
+/* Clear the zero segment */
+ ldr r0, =_szero
+ ldr r1, =_ezero
+ mov r2, #0
+1:
+ cmp r0, r1
+ strcc r2, [r0], #4
+ bcc 1b
+
+/* Setup stacks
+ **************/
+/* IRQ mode */
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+ mov sp, r4
+ sub r4, r4, #IRQ_STACK_SIZE
+
+/* Supervisor mode (interrupts enabled) */
+ msr CPSR_c, #ARM_MODE_SVC | F_BIT
+ mov sp, r4
+
+/* Branch to main()
+ ******************/
+ ldr r0, =main
+ blx r0
+
+/* Loop indefinitely when program is finished */
+1:
+ b 1b
+
diff --git a/boards/at91sam9g10-ek/board_cstartup_iar.s b/boards/at91sam9g10-ek/board_cstartup_iar.s new file mode 100644 index 0000000..3f2de25 --- /dev/null +++ b/boards/at91sam9g10-ek/board_cstartup_iar.s @@ -0,0 +1,187 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+ IAR startup file for AT91SAM9G10 microcontrollers.
+ */
+
+ MODULE ?cstartup
+
+ ;; Forward declaration of sections.
+ SECTION IRQ_STACK:DATA:NOROOT(2)
+ SECTION CSTACK:DATA:NOROOT(3)
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#define __ASSEMBLY__
+#include "board.h"
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+#define ARM_MODE_ABT 0x17
+#define ARM_MODE_FIQ 0x11
+#define ARM_MODE_IRQ 0x12
+#define ARM_MODE_SVC 0x13
+#define ARM_MODE_SYS 0x1F
+
+#define I_BIT 0x80
+#define F_BIT 0x40
+
+//------------------------------------------------------------------------------
+// Startup routine
+//------------------------------------------------------------------------------
+
+/*
+ Exception vectors
+ */
+ SECTION .vectors:CODE:NOROOT(2)
+
+ PUBLIC resetVector
+ PUBLIC irqHandler
+
+ EXTERN Undefined_Handler
+ EXTERN SWI_Handler
+ EXTERN Prefetch_Handler
+ EXTERN Abort_Handler
+ EXTERN FIQ_Handler
+
+ ARM
+
+__iar_init$$done: ; The interrupt vector is not needed
+ ; until after copy initialization is done
+
+resetVector:
+ ; All default exception handlers (except reset) are
+ ; defined as weak symbol definitions.
+ ; If a handler is defined by the application it will take precedence.
+ LDR pc, =resetHandler ; Reset
+ LDR pc, Undefined_Addr ; Undefined instructions
+ LDR pc, SWI_Addr ; Software interrupt (SWI/SYS)
+ LDR pc, Prefetch_Addr ; Prefetch abort
+ LDR pc, Abort_Addr ; Data abort
+ B . ; RESERVED
+ LDR pc, =irqHandler ; IRQ
+ LDR pc, FIQ_Addr ; FIQ
+
+Undefined_Addr: DCD Undefined_Handler
+SWI_Addr: DCD SWI_Handler
+Prefetch_Addr: DCD Prefetch_Handler
+Abort_Addr: DCD Abort_Handler
+FIQ_Addr: DCD FIQ_Handler
+
+/*
+ Handles incoming interrupt requests by branching to the corresponding
+ handler, as defined in the AIC. Supports interrupt nesting.
+ */
+irqHandler:
+ /* Save interrupt context on the stack to allow nesting */
+ SUB lr, lr, #4
+ STMFD sp!, {lr}
+ MRS lr, SPSR
+ STMFD sp!, {r0, lr}
+
+ /* Write in the IVR to support Protect Mode */
+ LDR lr, =AT91C_BASE_AIC
+ LDR r0, [r14, #AIC_IVR]
+ STR lr, [r14, #AIC_IVR]
+
+ /* Branch to interrupt handler in Supervisor mode */
+ MSR CPSR_c, #ARM_MODE_SYS
+ STMFD sp!, {r1-r3, r4, r12, lr}
+
+ /* Check for 8-byte alignment and save lr plus a */
+ /* word to indicate the stack adjustment used (0 or 4) */
+ AND r1, sp, #4
+ SUB sp, sp, r1
+ STMFD sp!, {r1, lr}
+
+ BLX r0
+
+ LDMIA sp!, {r1, lr}
+ ADD sp, sp, r1
+
+ LDMIA sp!, {r1-r3, r4, r12, lr}
+ MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
+
+ /* Acknowledge interrupt */
+ LDR lr, =AT91C_BASE_AIC
+ STR lr, [r14, #AIC_EOICR]
+
+ /* Restore interrupt context and branch back to calling code */
+ LDMIA sp!, {r0, lr}
+ MSR SPSR_cxsf, lr
+ LDMIA sp!, {pc}^
+
+
+/*
+ After a reset, execution starts here, the mode is ARM, supervisor
+ with interrupts disabled.
+ Initializes the chip and branches to the main() function.
+ */
+ SECTION .cstartup:CODE:NOROOT(2)
+
+ PUBLIC resetHandler
+ EXTERN LowLevelInit
+ EXTERN ?main
+ REQUIRE resetVector
+ ARM
+
+resetHandler:
+
+ /* Set pc to actual code location (i.e. not in remap zone) */
+ LDR pc, =label
+
+ /* Perform low-level initialization of the chip using LowLevelInit() */
+label:
+ LDR r0, =LowLevelInit
+ LDR r4, =SFE(CSTACK)
+ MOV sp, r4
+ BLX r0
+
+ /* Set up the interrupt stack pointer. */
+ MSR cpsr_c, #ARM_MODE_IRQ | I_BIT | F_BIT ; Change the mode
+ LDR sp, =SFE(IRQ_STACK)
+
+ /* Set up the SYS stack pointer. */
+ MSR cpsr_c, #ARM_MODE_SYS | F_BIT ; Change the mode
+ LDR sp, =SFE(CSTACK)
+
+ /* Branch to main() */
+ LDR r0, =?main
+ BLX r0
+
+ /* Loop indefinitely when program is finished */
+loop4:
+ B loop4
+
+ END
diff --git a/boards/at91sam9g10-ek/board_cstartup_keil.s b/boards/at91sam9g10-ek/board_cstartup_keil.s new file mode 100644 index 0000000..f5a4198 --- /dev/null +++ b/boards/at91sam9g10-ek/board_cstartup_keil.s @@ -0,0 +1,208 @@ +; * ----------------------------------------------------------------------------
+; * ATMEL Microcontroller Software Support
+; * ----------------------------------------------------------------------------
+; * Copyright (c) 2008, Atmel Corporation
+; *
+; * All rights reserved.
+; *
+; * Redistribution and use in source and binary forms, with or without
+; * modification, are permitted provided that the following conditions are met:
+; *
+; * - Redistributions of source code must retain the above copyright notice,
+; * this list of conditions and the disclaimer below.
+; *
+; * Atmel's name may not be used to endorse or promote products derived from
+; * this software without specific prior written permission.
+; *
+; * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+; * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+; * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+; * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+; * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+; * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+; * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+; * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+; * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+; * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+; * ----------------------------------------------------------------------------
+
+
+; KEIL startup file for AT91SAM9G10 microcontrollers.
+
+; ------------------------------------------------------------------------------
+; Definitions
+; ------------------------------------------------------------------------------
+
+; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
+
+ARM_MODE_USR EQU 0x10
+ARM_MODE_FIQ EQU 0x11
+ARM_MODE_IRQ EQU 0x12
+ARM_MODE_SVC EQU 0x13
+ARM_MODE_ABT EQU 0x17
+ARM_MODE_UND EQU 0x1B
+ARM_MODE_SYS EQU 0x1F
+
+I_BIT EQU 0x80 ; when I bit is set, IRQ is disabled
+F_BIT EQU 0x40 ; when F bit is set, FIQ is disabled
+
+AT91C_BASE_AIC EQU 0xFFFFF000
+AIC_IVR EQU 0x100
+AIC_EOICR EQU 0x130
+
+UND_Stack_Size EQU 0x00000000
+SVC_Stack_Size EQU 0x00000100
+ABT_Stack_Size EQU 0x00000000
+FIQ_Stack_Size EQU 0x00000000
+IRQ_Stack_Size EQU 0x00000080
+USR_Stack_Size EQU 0x00000400
+
+ PRESERVE8
+
+; Area Definition and Entry Point
+; Startup Code must be linked first at Address at which it expects to run.
+
+ AREA VECTOR, CODE
+ ARM
+
+; Exception Vectors
+
+Vectors
+ LDR pc,=resetHandler
+undefVector
+ b undefVector ; Undefined instruction
+swiVector
+ b swiVector ; Software interrupt
+prefetchAbortVector
+ b prefetchAbortVector ; Prefetch abort
+dataAbortVector
+ b dataAbortVector ; Data abort
+reservedVector
+ b reservedVector ; Reserved for future use
+irqVector
+ b irqHandler ; Interrupt
+fiqVector
+ ; Fast interrupt
+
+;------------------------------------------------------------------------------
+; Handles a fast interrupt request by branching to the address defined in the
+; AIC.
+;------------------------------------------------------------------------------
+fiqHandler
+ b fiqHandler
+
+;------------------------------------------------------------------------------
+; Handles incoming interrupt requests by branching to the corresponding
+; handler, as defined in the AIC. Supports interrupt nesting.
+;------------------------------------------------------------------------------
+irqHandler
+ ; Save interrupt context on the stack to allow nesting */
+ SUB lr, lr, #4
+ STMFD sp!, {lr}
+ MRS lr, SPSR
+ STMFD sp!, {r0,r1,lr}
+
+ ; Write in the IVR to support Protect Mode */
+ LDR lr, =AT91C_BASE_AIC
+ LDR r0, [r14, #AIC_IVR]
+ STR lr, [r14, #AIC_IVR]
+
+ ; Branch to interrupt handler in Supervisor mode */
+ MSR CPSR_c, #ARM_MODE_SVC
+ STMFD sp!, {r1-r4, r12, lr}
+ MOV lr, pc
+ BX r0
+ LDMIA sp!, {r1-r4, r12, lr}
+ MSR CPSR_c, #ARM_MODE_IRQ | I_BIT
+
+ ; Acknowledge interrupt */
+ LDR lr, =AT91C_BASE_AIC
+ STR lr, [r14, #AIC_EOICR]
+
+ ; Restore interrupt context and branch back to calling code
+ LDMIA sp!, {r0,r1,lr}
+ MSR SPSR_cxsf, lr
+ LDMIA sp!, {pc}^
+
+;------------------------------------------------------------------------------
+; After a reset, execution starts here, the mode is ARM, supervisor
+; with interrupts disabled.
+; Initializes the chip and branches to the main() function.
+;------------------------------------------------------------------------------
+
+ AREA cstartup, CODE
+ ENTRY ; Entry point for the application
+
+
+; Reset Handler
+
+ EXPORT resetHandler
+ IMPORT |Image$$Fixed_region$$Limit|
+ IMPORT |Image$$Relocate_region$$Base|
+ IMPORT |Image$$Relocate_region$$ZI$$Base|
+ IMPORT |Image$$Relocate_region$$ZI$$Limit|
+ IMPORT |Image$$ARM_LIB_STACK$$Base|
+ IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+ ; Perform low-level initialization of the chip using LowLevelInit()
+ IMPORT LowLevelInit
+
+resetHandler
+
+ ; Set pc to actual code location (i.e. not in remap zone)
+ LDR pc, =label
+label
+ ; Set up temporary stack (Top of the SRAM)
+ LDR r0, = |Image$$ARM_LIB_STACK$$ZI$$Limit|
+ MOV sp, r0
+ ; Call Low level init
+ LDR r0, =LowLevelInit
+ MOV lr, pc
+ BX r0
+
+
+;Initialize the Relocate_region segment
+ LDR r0, = |Image$$Fixed_region$$Limit|
+ LDR r1, = |Image$$Relocate_region$$Base|
+ LDR r3, = |Image$$Relocate_region$$ZI$$Base|
+
+ CMP r0, r1
+ BEQ %1
+
+
+ ; Copy init data
+0 CMP r1, r3
+ LDRCC r2, [r0], #4
+ STRCC r2, [r1], #4
+ BCC %0
+
+1 LDR r1, =|Image$$Relocate_region$$ZI$$Limit|
+ MOV r2, #0
+2 CMP r3, r1
+ STRCC r2, [r3], #4
+ BCC %2
+
+
+; Setup Stack for each mode
+
+ LDR R0, = |Image$$ARM_LIB_STACK$$ZI$$Limit|
+
+; Enter IRQ Mode and set its Stack Pointer
+ MSR CPSR_c, #ARM_MODE_IRQ:OR:I_BIT:OR:F_BIT
+ MOV SP, R0
+ SUB R4, SP, #IRQ_Stack_Size
+
+; Supervisor mode (interrupts enabled)
+ MSR CPSR_c, #ARM_MODE_SVC | F_BIT
+ MOV SP, R4
+
+; Enter the C code
+
+ IMPORT __main
+ LDR R0, =__main
+ BX R0
+loop4
+ B loop4
+
+ END
+
diff --git a/boards/at91sam9g10-ek/board_lowlevel.c b/boards/at91sam9g10-ek/board_lowlevel.c new file mode 100644 index 0000000..836a911 --- /dev/null +++ b/boards/at91sam9g10-ek/board_lowlevel.c @@ -0,0 +1,180 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#include "board.h"
+#include "board_memories.h"
+#include <pmc/pmc.h>
+
+//------------------------------------------------------------------------------
+// Internal definitions
+//------------------------------------------------------------------------------
+/*
+ Constants: Clock and PLL settings
+
+ BOARD_OSCOUNT - Startup time of main oscillator (in number of slow clock
+ ticks).
+ BOARD_USBDIV - USB PLL divisor value to obtain a 48MHz clock.
+ BOARD_CKGR_PLL - PLL frequency range.
+ BOARD_PLLCOUNT - PLL startup time (in number of slow clock ticks).
+ BOARD_MUL - PLL MUL value.
+ BOARD_DIV - PLL DIV value.
+ BOARD_PRESCALER - Master clock prescaler value.
+*/
+#define BOARD_OSCOUNT (AT91C_CKGR_OSCOUNT & (64 << 8))
+#define BOARD_CKGR_PLLA (AT91C_CKGR_SRCA | AT91C_CKGR_OUTA_2)
+#define BOARD_PLLACOUNT (63 << 8)
+#define BOARD_MULA (AT91C_CKGR_MULA & (100 << 16))
+#define BOARD_DIVA (AT91C_CKGR_DIVA & 7)
+#define BOARD_PRESCALER AT91C_PMC_MDIV_2
+
+#define BOARD_USBDIV AT91C_CKGR_USBDIV_2
+#define BOARD_CKGR_PLLB AT91C_CKGR_OUTB_0
+#define BOARD_PLLBCOUNT BOARD_PLLACOUNT
+#define BOARD_MULB (124 << 16)
+#define BOARD_DIVB 12
+
+//------------------------------------------------------------------------------
+// Internal functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Default spurious interrupt handler. Infinite loop.
+//------------------------------------------------------------------------------
+void defaultSpuriousHandler( void )
+{
+ //while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Default handler for fast interrupt requests. Infinite loop.
+//------------------------------------------------------------------------------
+void defaultFiqHandler( void )
+{
+ while (1);
+}
+
+//------------------------------------------------------------------------------
+/// Default handler for standard interrupt requests. Infinite loop.
+//------------------------------------------------------------------------------
+void defaultIrqHandler( void )
+{
+ while (1);
+}
+
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Performs the low-level initialization of the chip.
+//------------------------------------------------------------------------------
+void LowLevelInit( void )
+{
+ unsigned char i;
+
+#if !defined(sdram)
+
+ /* Initialize main oscillator
+ ****************************/
+ AT91C_BASE_PMC->PMC_MOR = BOARD_OSCOUNT | AT91C_CKGR_MOSCEN;
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS));
+
+ /* Initialize PLLA at 266MHz */
+ AT91C_BASE_PMC->PMC_PLLAR = BOARD_CKGR_PLLA
+ | BOARD_PLLACOUNT
+ | BOARD_MULA
+ | BOARD_DIVA;
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA));
+
+ // Initialize PLLB for USB usage (if not already locked)
+ if (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB)) {
+ AT91C_BASE_PMC->PMC_PLLBR = BOARD_USBDIV
+ | BOARD_CKGR_PLLB
+ | BOARD_PLLBCOUNT
+ | BOARD_MULB
+ | BOARD_DIVB;
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB));
+ }
+
+ /* Wait for the master clock if it was already initialized */
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+ /* Switch to fast clock
+ **********************/
+ /* Switch to main oscillator + prescaler */
+ AT91C_BASE_PMC->PMC_MCKR = BOARD_PRESCALER;
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+ /* Switch to PLL + prescaler */
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLLA_CLK;
+ while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY));
+#endif //#if !defined(sdram)
+
+ /* Initialize AIC
+ ****************/
+ AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
+ AT91C_BASE_AIC->AIC_SVR[0] = (unsigned int) defaultFiqHandler;
+ for (i = 1; i < 31; i++) {
+
+ AT91C_BASE_AIC->AIC_SVR[i] = (unsigned int) defaultIrqHandler;
+ }
+ AT91C_BASE_AIC->AIC_SPU = (unsigned int) defaultSpuriousHandler;
+
+ // Unstack nested interrupts
+ for (i = 0; i < 8 ; i++) {
+
+ AT91C_BASE_AIC->AIC_EOICR = 0;
+ }
+
+ // Enable Debug mode
+ //AT91C_BASE_AIC->AIC_DCR = AT91C_AIC_DCR_PROT;
+
+ /* Watchdog initialization
+ *************************/
+ AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+
+ /* Remap
+ *******/
+ BOARD_RemapRam();
+
+ // Disable RTT and PIT interrupts (potential problem when program A
+ // configures RTT, then program B wants to use PIT only, interrupts
+ // from the RTT will still occur since they both use AT91C_ID_SYS)
+ AT91C_BASE_RTTC->RTTC_RTMR &= ~(AT91C_RTTC_ALMIEN | AT91C_RTTC_RTTINCIEN);
+ AT91C_BASE_PITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;
+
+#if defined(norflash)
+ BOARD_ConfigureNorFlash(BOARD_NORFLASH_DFT_BUS_SIZE);
+#endif
+}
+
diff --git a/boards/at91sam9g10-ek/board_lowlevel.h b/boards/at91sam9g10-ek/board_lowlevel.h new file mode 100644 index 0000000..1475670 --- /dev/null +++ b/boards/at91sam9g10-ek/board_lowlevel.h @@ -0,0 +1,52 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+///
+/// !Purpose
+///
+/// Provides the low-level initialization function that gets called on chip
+/// startup.
+///
+/// !Usage
+///
+/// LowLevelInit() is called in #board_cstartup.S#.
+//------------------------------------------------------------------------------
+
+#ifndef BOARD_LOWLEVEL_H
+#define BOARD_LOWLEVEL_H
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+extern void LowLevelInit(void);
+
+#endif // BOARD_LOWLEVEL_H
+
diff --git a/boards/at91sam9g10-ek/board_memories.c b/boards/at91sam9g10-ek/board_memories.c new file mode 100644 index 0000000..e99877e --- /dev/null +++ b/boards/at91sam9g10-ek/board_memories.c @@ -0,0 +1,398 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*
+ Title: Memories implementation
+*/
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#include <board.h>
+#include <pio/pio.h>
+
+/*
+ Macros:
+ READ - Reads a register value. Useful to add trace information to read
+ accesses.
+ WRITE - Writes data in a register. Useful to add trace information to
+ write accesses.
+*/
+#define READ(peripheral, register) (peripheral->register)
+#define WRITE(peripheral, register, value) (peripheral->register = value)
+
+//------------------------------------------------------------------------------
+// Internal definitions
+//------------------------------------------------------------------------------
+/*
+ Constants: Remap types
+ BOARD_ROM - ROM or EBI CS0 is mirrored in the remap zone.
+ BOARD_RAM - RAM is mirrored in the remap zone.
+*/
+#define BOARD_ROM 0
+#define BOARD_RAM 1
+
+//------------------------------------------------------------------------------
+// Internal functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Returns the current remap (see <Remap types>).
+//------------------------------------------------------------------------------
+static unsigned char BOARD_GetRemap( void )
+{
+ unsigned int *remap = (unsigned int *) 0;
+ unsigned int *ram = (unsigned int *) AT91C_IRAM;
+
+ // Try to write in 0 and see if this affects the RAM
+ unsigned int temp = *ram;
+ *ram = temp + 1;
+ if (*remap == *ram) {
+
+ *ram = temp;
+ return BOARD_RAM;
+ }
+ else {
+
+ *ram = temp;
+ return BOARD_ROM;
+ }
+}
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Changes the mapping of the chip so that the remap area mirrors the
+/// internal ROM or the EBI CS0.
+//------------------------------------------------------------------------------
+void BOARD_RemapRom()
+{
+ if (BOARD_GetRemap() != BOARD_ROM) {
+ WRITE(AT91C_BASE_MATRIX, MATRIX_MCFG, 0);
+ }
+}
+
+//------------------------------------------------------------------------------
+/// Changes the mapping of the chip so that the remap area mirrors the
+/// internal RAM.
+//------------------------------------------------------------------------------
+void BOARD_RemapRam()
+{
+ if (BOARD_GetRemap() != BOARD_RAM) {
+ WRITE(AT91C_BASE_MATRIX, MATRIX_MCFG, (AT91C_MATRIX_RCA926I | AT91C_MATRIX_RCA926D));
+ }
+}
+
+//------------------------------------------------------------------------------
+/// Initialize and configure the SDRAM
+//------------------------------------------------------------------------------
+void BOARD_ConfigureSdram(unsigned char busWidth)
+{
+
+ volatile unsigned int i;
+ static const Pin pinsSdram[] = {PINS_SDRAM};
+ volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
+ unsigned short sdrc_dbw = 0;
+ unsigned int tmp = 0;
+
+ switch (busWidth) {
+ case 16:
+ sdrc_dbw = AT91C_SDRAMC_DBW_16_BITS;
+ break;
+
+ case 32:
+ default:
+ sdrc_dbw = AT91C_SDRAMC_DBW_32_BITS;
+ break;
+
+ }
+
+ // Enable corresponding PIOs
+ PIO_Configure(pinsSdram, 1);
+
+ // Enable EBI chip select for the SDRAM
+ tmp = READ(AT91C_BASE_MATRIX, MATRIX_EBICSA) | AT91C_MATRIX_CS1A_SDRAMC;
+ WRITE(AT91C_BASE_MATRIX, MATRIX_EBICSA, tmp);
+
+
+
+ // CFG Control Register
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
+ | AT91C_SDRAMC_NR_13
+ | AT91C_SDRAMC_CAS_3
+ | AT91C_SDRAMC_NB_4_BANKS
+ | sdrc_dbw
+ | AT91C_SDRAMC_TWR_2
+ | AT91C_SDRAMC_TRC_9
+ | AT91C_SDRAMC_TRP_3
+ | AT91C_SDRAMC_TRCD_3
+ | AT91C_SDRAMC_TRAS_6
+ | AT91C_SDRAMC_TXSR_10);
+
+ for (i = 0; i < 1000; i++);
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
+ pSdram[0] = 0x00000000;
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
+ pSdram[0] = 0x00000000; // Perform PRCHG
+
+ for (i = 0; i < 10000; i++);
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
+ pSdram[1] = 0x00000001; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
+ pSdram[2] = 0x00000002; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
+ pSdram[3] = 0x00000003; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
+ pSdram[4] = 0x00000004; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
+ pSdram[5] = 0x00000005; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
+ pSdram[6] = 0x00000006; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
+ pSdram[7] = 0x00000007; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
+ pSdram[8] = 0x00000008; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
+ pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (BOARD_MCK * 7) / 1000000); // Set Refresh Timer
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
+ pSdram[0] = 0x00000000; // Perform Normal mode
+}
+
+//------------------------------------------------------------------------------
+/// Initialize and configure the SDRAM for a 48 MHz MCK (ROM code clock settings)
+//------------------------------------------------------------------------------
+void BOARD_ConfigureSdram48MHz(unsigned char busWidth)
+{
+ volatile unsigned int i;
+ static const Pin pinsSdram[] = {PINS_SDRAM};
+ volatile unsigned int *pSdram = (unsigned int *) AT91C_EBI_SDRAM;
+ unsigned short sdrc_dbw = 0;
+ unsigned int tmp = 0;
+
+ switch (busWidth) {
+ case 16:
+ sdrc_dbw = AT91C_SDRAMC_DBW_16_BITS;
+ break;
+
+ case 32:
+ default:
+ sdrc_dbw = AT91C_SDRAMC_DBW_32_BITS;
+ break;
+
+ }
+
+ // Enable corresponding PIOs
+ PIO_Configure(pinsSdram, 1);
+
+ // Enable EBI chip select for the SDRAM
+ tmp = READ(AT91C_BASE_MATRIX, MATRIX_EBICSA) | AT91C_MATRIX_CS1A_SDRAMC;
+ WRITE(AT91C_BASE_MATRIX, MATRIX_EBICSA, tmp);
+
+
+ // CFG Control Register
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_CR, AT91C_SDRAMC_NC_9
+ | AT91C_SDRAMC_NR_13
+ | AT91C_SDRAMC_CAS_2
+ | AT91C_SDRAMC_NB_4_BANKS
+ | sdrc_dbw
+ | AT91C_SDRAMC_TWR_1
+ | AT91C_SDRAMC_TRC_4
+ | AT91C_SDRAMC_TRP_1
+ | AT91C_SDRAMC_TRCD_1
+ | AT91C_SDRAMC_TRAS_2
+ | AT91C_SDRAMC_TXSR_3);
+
+ for (i = 0; i < 1000; i++);
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NOP_CMD); // Perform NOP
+ pSdram[0] = 0x00000000;
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_PRCGALL_CMD); // Set PRCHG AL
+ pSdram[0] = 0x00000000; // Perform PRCHG
+
+ for (i = 0; i < 10000; i++);
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 1st CBR
+ pSdram[1] = 0x00000001; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 2 CBR
+ pSdram[2] = 0x00000002; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 3 CBR
+ pSdram[3] = 0x00000003; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 4 CBR
+ pSdram[4] = 0x00000004; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 5 CBR
+ pSdram[5] = 0x00000005; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 6 CBR
+ pSdram[6] = 0x00000006; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 7 CBR
+ pSdram[7] = 0x00000007; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_RFSH_CMD); // Set 8 CBR
+ pSdram[8] = 0x00000008; // Perform CBR
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_LMR_CMD); // Set LMR operation
+ pSdram[9] = 0xcafedede; // Perform LMR burst=1, lat=2
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_TR, (48000000 * 7) / 1000000); // Set Refresh Timer
+
+ WRITE(AT91C_BASE_SDRAMC, SDRAMC_MR, AT91C_SDRAMC_MODE_NORMAL_CMD); // Set Normal mode
+ pSdram[0] = 0x00000000; // Perform Normal mode
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NandFlash access. Pins must be configured after or
+/// before calling this function.
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNandFlash(unsigned char busWidth)
+{
+ // Configure EBI
+ AT91C_BASE_MATRIX->MATRIX_EBICSA |= AT91C_MATRIX_CS3A_SM;
+
+ // Configure SMC
+ AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
+ AT91C_BASE_SMC->SMC_PULSE3 = 0x03030303;
+ AT91C_BASE_SMC->SMC_CYCLE3 = 0x00050005;
+ AT91C_BASE_SMC->SMC_CTRL3 = 0x00020003;
+
+ if (busWidth == 8) {
+
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+ }
+ else if (busWidth == 16) {
+
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+ }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NandFlash access at 48MHz. Pins must be configured
+/// after or before calling this function.
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth)
+{
+ // Configure EBI
+ AT91C_BASE_MATRIX->MATRIX_EBICSA |= AT91C_MATRIX_CS3A_SM;
+
+ // Configure SMC
+ AT91C_BASE_SMC->SMC_SETUP3 = 0x00010001;
+ AT91C_BASE_SMC->SMC_PULSE3 = 0x04030302;
+ AT91C_BASE_SMC->SMC_CYCLE3 = 0x00070004;
+ AT91C_BASE_SMC->SMC_CTRL3 = (AT91C_SMC_READMODE
+ | AT91C_SMC_WRITEMODE
+ | AT91C_SMC_NWAITM_NWAIT_DISABLE
+ | ((0x1 << 16) & AT91C_SMC_TDF));
+
+ if (busWidth == 8) {
+
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+ }
+ else if (busWidth == 16) {
+
+ AT91C_BASE_SMC->SMC_CTRL3 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+ }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NorFlash access
+/// \Param busWidth Bus width
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNorFlash(unsigned char busWidth)
+{
+ // Configure SMC
+
+ AT91C_BASE_SMC->SMC_SETUP0 = 0x00000002;
+ AT91C_BASE_SMC->SMC_PULSE0 = 0x0A0A0A06;
+ AT91C_BASE_SMC->SMC_CYCLE0 = 0x000A000A;
+ AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE
+ | AT91C_SMC_WRITEMODE
+ | AT91C_SMC_NWAITM_NWAIT_DISABLE
+ | ((0x1 << 16) & AT91C_SMC_TDF));
+
+ if (busWidth == 8) {
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+ }
+ else if (busWidth == 16) {
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+ }
+ else if (busWidth == 32) {
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
+ }
+}
+
+
+//------------------------------------------------------------------------------
+/// Configures the EBI for NorFlash access at 48MHz.
+/// \Param busWidth Bus width
+//------------------------------------------------------------------------------
+void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth)
+{
+ // Configure SMC
+ AT91C_BASE_SMC->SMC_SETUP0 = 0x00000001;
+ AT91C_BASE_SMC->SMC_PULSE0 = 0x07070703;
+ AT91C_BASE_SMC->SMC_CYCLE0 = 0x00070007;
+ AT91C_BASE_SMC->SMC_CTRL0 = (AT91C_SMC_READMODE
+ | AT91C_SMC_WRITEMODE
+ | AT91C_SMC_NWAITM_NWAIT_DISABLE
+ | ((0x1 << 16) & AT91C_SMC_TDF));
+
+ if (busWidth == 8) {
+
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_EIGTH_BITS;
+ }
+ else if (busWidth == 16) {
+
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS;
+ }
+ else if (busWidth == 32) {
+
+ AT91C_BASE_SMC->SMC_CTRL0 |= AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS;
+ }
+}
+
diff --git a/boards/at91sam9g10-ek/board_memories.h b/boards/at91sam9g10-ek/board_memories.h new file mode 100644 index 0000000..fdfdcef --- /dev/null +++ b/boards/at91sam9g10-ek/board_memories.h @@ -0,0 +1,54 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef BOARD_MEMORIES_H
+#define BOARD_MEMORIES_H
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+
+extern void BOARD_RemapRom(void);
+
+extern void BOARD_RemapRam(void);
+
+extern void BOARD_ConfigureSdram(unsigned char busWidth);
+
+extern void BOARD_ConfigureSdram48MHz(unsigned char busWidth);
+
+extern void BOARD_ConfigureNandFlash(unsigned char busWidth);
+
+extern void BOARD_ConfigureNandFlash48MHz(unsigned char busWidth);
+
+extern void BOARD_ConfigureNorFlash(unsigned char busWidth);
+
+extern void BOARD_ConfigureNorFlash48MHz(unsigned char busWidth);
+
+#endif //#ifndef BOARD_MEMORIES_H
+
diff --git a/boards/at91sam9g10-ek/board_powermode.c b/boards/at91sam9g10-ek/board_powermode.c new file mode 100644 index 0000000..710b10a --- /dev/null +++ b/boards/at91sam9g10-ek/board_powermode.c @@ -0,0 +1,64 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#include "board.h"
+#include <pmc/pmc.h>
+
+//------------------------------------------------------------------------------
+// Internal definitions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Internal functions
+//------------------------------------------------------------------------------
+
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Put the CPU in IDLE mode with CP15
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ PMC_CPUInIdleMode();
+}
+
+//------------------------------------------------------------------------------
+/// Returns to normal mode automatically
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+}
diff --git a/boards/at91sam9g10-ek/board_powermode.h b/boards/at91sam9g10-ek/board_powermode.h new file mode 100644 index 0000000..fd6372f --- /dev/null +++ b/boards/at91sam9g10-ek/board_powermode.h @@ -0,0 +1,50 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+///
+/// !Usage
+///
+//------------------------------------------------------------------------------
+
+#ifndef BOARD_POWERMODE_H
+#define BOARD_POWERMODE_H
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+extern void LowPowerMode(void);
+
+extern void NormalPowerMode(void);
+
+#endif //#ifndef BOARD_MEMORIES_H
+
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