diff options
Diffstat (limited to 'boards/at91cap7-stk/at91cap7')
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/at91cap7.h | 2499 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/chip.h | 108 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/chip.mak | 32 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sdram.icf | 48 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sdram.lds | 89 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sdram_samba.lds | 87 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sram.icf | 38 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sram.lds | 80 | ||||
| -rw-r--r-- | boards/at91cap7-stk/at91cap7/sram_samba.lds | 97 |
9 files changed, 3078 insertions, 0 deletions
diff --git a/boards/at91cap7-stk/at91cap7/at91cap7.h b/boards/at91cap7-stk/at91cap7/at91cap7.h new file mode 100644 index 0000000..5bf9f24 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/at91cap7.h @@ -0,0 +1,2499 @@ +// ----------------------------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ----------------------------------------------------------------------------
+// Copyright (c) 2008, Atmel Corporation
+//
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the disclaimer below.
+//
+// Atmel's name may not be used to endorse or promote products derived from
+// this software without specific prior written permission.
+//
+// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// ----------------------------------------------------------------------------
+// File Name : AT91CAP7.h
+// Object : AT91CAP7 definitions
+// Generated : AT91 SW Application Group 04/02/2009 (11:44:12)
+//
+// CVS Reference : /AT91CAP7.pl/1.1/Wed Aug 16 15:50:23 2006//
+// CVS Reference : /SYS_AT91CAP7.pl/1.1/Thu Aug 17 08:05:51 2006//
+// CVS Reference : // CVS Reference : // CVS Reference : // CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
+// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
+// CVS Reference : /AIC_6075A.pl/1.1/Mon Jul 12 17:04:01 2004//
+// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
+// CVS Reference : // CVS Reference : // CVS Reference : // CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
+// CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
+// CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
+// CVS Reference : // CVS Reference : /TC_6082A.pl/1.8/Thu Oct 9 07:51:40 2008//
+// CVS Reference : // CVS Reference : // CVS Reference : // ----------------------------------------------------------------------------
+
+#ifndef AT91CAP7_H
+#define AT91CAP7_H
+
+#ifndef __ASSEMBLY__
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+#define AT91_CAST(a) (a)
+#else
+#define AT91_CAST(a)
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR SDRAM Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SDRAMC {
+ AT91_REG SDRAMC_MR; // SDRAM Controller Mode Register
+ AT91_REG SDRAMC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG SDRAMC_CR; // SDRAM Controller Configuration Register
+ AT91_REG SDRAMC_HSR; // SDRAM Controller High Speed Register
+ AT91_REG SDRAMC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SDRAMC_MDR; // SDRAM Memory Device Register
+} AT91S_SDRAMC, *AT91PS_SDRAMC;
+#else
+#define SDRAMC_MR (AT91_CAST(AT91_REG *) 0x00000000) // (SDRAMC_MR) SDRAM Controller Mode Register
+#define SDRAMC_TR (AT91_CAST(AT91_REG *) 0x00000004) // (SDRAMC_TR) SDRAM Controller Refresh Timer Register
+#define SDRAMC_CR (AT91_CAST(AT91_REG *) 0x00000008) // (SDRAMC_CR) SDRAM Controller Configuration Register
+#define SDRAMC_HSR (AT91_CAST(AT91_REG *) 0x0000000C) // (SDRAMC_HSR) SDRAM Controller High Speed Register
+#define SDRAMC_LPR (AT91_CAST(AT91_REG *) 0x00000010) // (SDRAMC_LPR) SDRAM Controller Low Power Register
+#define SDRAMC_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SDRAMC_IER) SDRAM Controller Interrupt Enable Register
+#define SDRAMC_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SDRAMC_IDR) SDRAM Controller Interrupt Disable Register
+#define SDRAMC_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SDRAMC_IMR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_ISR (AT91_CAST(AT91_REG *) 0x00000020) // (SDRAMC_ISR) SDRAM Controller Interrupt Mask Register
+#define SDRAMC_MDR (AT91_CAST(AT91_REG *) 0x00000024) // (SDRAMC_MDR) SDRAM Memory Device Register
+
+#endif
+// -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register --------
+#define AT91C_SDRAMC_MODE (0x7 << 0) // (SDRAMC) Mode
+#define AT91C_SDRAMC_MODE_NORMAL_CMD (0x0) // (SDRAMC) Normal Mode
+#define AT91C_SDRAMC_MODE_NOP_CMD (0x1) // (SDRAMC) Issue a NOP Command at every access
+#define AT91C_SDRAMC_MODE_PRCGALL_CMD (0x2) // (SDRAMC) Issue a All Banks Precharge Command at every access
+#define AT91C_SDRAMC_MODE_LMR_CMD (0x3) // (SDRAMC) Issue a Load Mode Register at every access
+#define AT91C_SDRAMC_MODE_RFSH_CMD (0x4) // (SDRAMC) Issue a Refresh
+#define AT91C_SDRAMC_MODE_EXT_LMR_CMD (0x5) // (SDRAMC) Issue an Extended Load Mode Register
+#define AT91C_SDRAMC_MODE_DEEP_CMD (0x6) // (SDRAMC) Enter Deep Power Mode
+// -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register --------
+#define AT91C_SDRAMC_COUNT (0xFFF << 0) // (SDRAMC) Refresh Counter
+// -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register --------
+#define AT91C_SDRAMC_NC (0x3 << 0) // (SDRAMC) Number of Column Bits
+#define AT91C_SDRAMC_NC_8 (0x0) // (SDRAMC) 8 Bits
+#define AT91C_SDRAMC_NC_9 (0x1) // (SDRAMC) 9 Bits
+#define AT91C_SDRAMC_NC_10 (0x2) // (SDRAMC) 10 Bits
+#define AT91C_SDRAMC_NC_11 (0x3) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR (0x3 << 2) // (SDRAMC) Number of Row Bits
+#define AT91C_SDRAMC_NR_11 (0x0 << 2) // (SDRAMC) 11 Bits
+#define AT91C_SDRAMC_NR_12 (0x1 << 2) // (SDRAMC) 12 Bits
+#define AT91C_SDRAMC_NR_13 (0x2 << 2) // (SDRAMC) 13 Bits
+#define AT91C_SDRAMC_NB (0x1 << 4) // (SDRAMC) Number of Banks
+#define AT91C_SDRAMC_NB_2_BANKS (0x0 << 4) // (SDRAMC) 2 banks
+#define AT91C_SDRAMC_NB_4_BANKS (0x1 << 4) // (SDRAMC) 4 banks
+#define AT91C_SDRAMC_CAS (0x3 << 5) // (SDRAMC) CAS Latency
+#define AT91C_SDRAMC_CAS_1 (0x1 << 5) // (SDRAMC) 1 cycle
+#define AT91C_SDRAMC_CAS_2 (0x2 << 5) // (SDRAMC) 2 cycles
+#define AT91C_SDRAMC_CAS_3 (0x3 << 5) // (SDRAMC) 3 cycles
+#define AT91C_SDRAMC_DBW (0x1 << 7) // (SDRAMC) Data Bus Width
+#define AT91C_SDRAMC_DBW_32_BITS (0x0 << 7) // (SDRAMC) 32 Bits datas bus
+#define AT91C_SDRAMC_DBW_16_BITS (0x1 << 7) // (SDRAMC) 16 Bits datas bus
+#define AT91C_SDRAMC_TWR (0xF << 8) // (SDRAMC) Number of Write Recovery Time Cycles
+#define AT91C_SDRAMC_TWR_0 (0x0 << 8) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TWR_1 (0x1 << 8) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TWR_2 (0x2 << 8) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TWR_3 (0x3 << 8) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TWR_4 (0x4 << 8) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TWR_5 (0x5 << 8) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TWR_6 (0x6 << 8) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TWR_7 (0x7 << 8) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TWR_8 (0x8 << 8) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TWR_9 (0x9 << 8) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TWR_10 (0xA << 8) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TWR_11 (0xB << 8) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TWR_12 (0xC << 8) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TWR_13 (0xD << 8) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TWR_14 (0xE << 8) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TWR_15 (0xF << 8) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRC (0xF << 12) // (SDRAMC) Number of RAS Cycle Time Cycles
+#define AT91C_SDRAMC_TRC_0 (0x0 << 12) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRC_1 (0x1 << 12) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRC_2 (0x2 << 12) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRC_3 (0x3 << 12) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRC_4 (0x4 << 12) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRC_5 (0x5 << 12) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRC_6 (0x6 << 12) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRC_7 (0x7 << 12) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRC_8 (0x8 << 12) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRC_9 (0x9 << 12) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRC_10 (0xA << 12) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRC_11 (0xB << 12) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRC_12 (0xC << 12) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRC_13 (0xD << 12) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRC_14 (0xE << 12) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRC_15 (0xF << 12) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRP (0xF << 16) // (SDRAMC) Number of RAS Precharge Time Cycles
+#define AT91C_SDRAMC_TRP_0 (0x0 << 16) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRP_1 (0x1 << 16) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRP_2 (0x2 << 16) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRP_3 (0x3 << 16) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRP_4 (0x4 << 16) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRP_5 (0x5 << 16) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRP_6 (0x6 << 16) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRP_7 (0x7 << 16) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRP_8 (0x8 << 16) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRP_9 (0x9 << 16) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRP_10 (0xA << 16) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRP_11 (0xB << 16) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRP_12 (0xC << 16) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRP_13 (0xD << 16) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRP_14 (0xE << 16) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRP_15 (0xF << 16) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRCD (0xF << 20) // (SDRAMC) Number of RAS to CAS Delay Cycles
+#define AT91C_SDRAMC_TRCD_0 (0x0 << 20) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRCD_1 (0x1 << 20) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRCD_2 (0x2 << 20) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRCD_3 (0x3 << 20) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRCD_4 (0x4 << 20) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRCD_5 (0x5 << 20) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRCD_6 (0x6 << 20) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRCD_7 (0x7 << 20) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRCD_8 (0x8 << 20) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRCD_9 (0x9 << 20) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRCD_10 (0xA << 20) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRCD_11 (0xB << 20) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRCD_12 (0xC << 20) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRCD_13 (0xD << 20) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRCD_14 (0xE << 20) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRCD_15 (0xF << 20) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TRAS (0xF << 24) // (SDRAMC) Number of RAS Active Time Cycles
+#define AT91C_SDRAMC_TRAS_0 (0x0 << 24) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TRAS_1 (0x1 << 24) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TRAS_2 (0x2 << 24) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TRAS_3 (0x3 << 24) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TRAS_4 (0x4 << 24) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TRAS_5 (0x5 << 24) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TRAS_6 (0x6 << 24) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TRAS_7 (0x7 << 24) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TRAS_8 (0x8 << 24) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TRAS_9 (0x9 << 24) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TRAS_10 (0xA << 24) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TRAS_11 (0xB << 24) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TRAS_12 (0xC << 24) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TRAS_13 (0xD << 24) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TRAS_14 (0xE << 24) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TRAS_15 (0xF << 24) // (SDRAMC) Value : 15
+#define AT91C_SDRAMC_TXSR (0xF << 28) // (SDRAMC) Number of Command Recovery Time Cycles
+#define AT91C_SDRAMC_TXSR_0 (0x0 << 28) // (SDRAMC) Value : 0
+#define AT91C_SDRAMC_TXSR_1 (0x1 << 28) // (SDRAMC) Value : 1
+#define AT91C_SDRAMC_TXSR_2 (0x2 << 28) // (SDRAMC) Value : 2
+#define AT91C_SDRAMC_TXSR_3 (0x3 << 28) // (SDRAMC) Value : 3
+#define AT91C_SDRAMC_TXSR_4 (0x4 << 28) // (SDRAMC) Value : 4
+#define AT91C_SDRAMC_TXSR_5 (0x5 << 28) // (SDRAMC) Value : 5
+#define AT91C_SDRAMC_TXSR_6 (0x6 << 28) // (SDRAMC) Value : 6
+#define AT91C_SDRAMC_TXSR_7 (0x7 << 28) // (SDRAMC) Value : 7
+#define AT91C_SDRAMC_TXSR_8 (0x8 << 28) // (SDRAMC) Value : 8
+#define AT91C_SDRAMC_TXSR_9 (0x9 << 28) // (SDRAMC) Value : 9
+#define AT91C_SDRAMC_TXSR_10 (0xA << 28) // (SDRAMC) Value : 10
+#define AT91C_SDRAMC_TXSR_11 (0xB << 28) // (SDRAMC) Value : 11
+#define AT91C_SDRAMC_TXSR_12 (0xC << 28) // (SDRAMC) Value : 12
+#define AT91C_SDRAMC_TXSR_13 (0xD << 28) // (SDRAMC) Value : 13
+#define AT91C_SDRAMC_TXSR_14 (0xE << 28) // (SDRAMC) Value : 14
+#define AT91C_SDRAMC_TXSR_15 (0xF << 28) // (SDRAMC) Value : 15
+// -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
+#define AT91C_SDRAMC_DA (0x1 << 0) // (SDRAMC) Decode Cycle Enable Bit
+#define AT91C_SDRAMC_DA_DISABLE (0x0) // (SDRAMC) Disable Decode Cycle
+#define AT91C_SDRAMC_DA_ENABLE (0x1) // (SDRAMC) Enable Decode Cycle
+// -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
+#define AT91C_SDRAMC_LPCB (0x3 << 0) // (SDRAMC) Low-power Configurations
+#define AT91C_SDRAMC_LPCB_DISABLE (0x0) // (SDRAMC) Disable Low Power Features
+#define AT91C_SDRAMC_LPCB_SELF_REFRESH (0x1) // (SDRAMC) Enable SELF_REFRESH
+#define AT91C_SDRAMC_LPCB_POWER_DOWN (0x2) // (SDRAMC) Enable POWER_DOWN
+#define AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN (0x3) // (SDRAMC) Enable DEEP_POWER_DOWN
+#define AT91C_SDRAMC_PASR (0x7 << 4) // (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TCSR (0x3 << 8) // (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
+#define AT91C_SDRAMC_DS (0x3 << 10) // (SDRAMC) Drive Strenght (only for Low Power SDRAM)
+#define AT91C_SDRAMC_TIMEOUT (0x3 << 12) // (SDRAMC) Time to define when Low Power Mode is enabled
+#define AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES (0x0 << 12) // (SDRAMC) Activate SDRAM Low Power Mode Immediately
+#define AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES (0x1 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+#define AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES (0x2 << 12) // (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
+// -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
+#define AT91C_SDRAMC_RES (0x1 << 0) // (SDRAMC) Refresh Error Status
+// -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
+// -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
+// -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
+// -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
+#define AT91C_SDRAMC_MD (0x3 << 0) // (SDRAMC) Memory Device Type
+#define AT91C_SDRAMC_MD_SDRAM (0x0) // (SDRAMC) SDRAM Mode
+#define AT91C_SDRAMC_MD_LOW_POWER_SDRAM (0x1) // (SDRAMC) SDRAM Low Power Mode
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Static Memory Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SMC {
+ AT91_REG SMC_SETUP0; // Setup Register for CS 0
+ AT91_REG SMC_PULSE0; // Pulse Register for CS 0
+ AT91_REG SMC_CYCLE0; // Cycle Register for CS 0
+ AT91_REG SMC_CTRL0; // Control Register for CS 0
+ AT91_REG SMC_SETUP1; // Setup Register for CS 1
+ AT91_REG SMC_PULSE1; // Pulse Register for CS 1
+ AT91_REG SMC_CYCLE1; // Cycle Register for CS 1
+ AT91_REG SMC_CTRL1; // Control Register for CS 1
+ AT91_REG SMC_SETUP2; // Setup Register for CS 2
+ AT91_REG SMC_PULSE2; // Pulse Register for CS 2
+ AT91_REG SMC_CYCLE2; // Cycle Register for CS 2
+ AT91_REG SMC_CTRL2; // Control Register for CS 2
+ AT91_REG SMC_SETUP3; // Setup Register for CS 3
+ AT91_REG SMC_PULSE3; // Pulse Register for CS 3
+ AT91_REG SMC_CYCLE3; // Cycle Register for CS 3
+ AT91_REG SMC_CTRL3; // Control Register for CS 3
+ AT91_REG SMC_SETUP4; // Setup Register for CS 4
+ AT91_REG SMC_PULSE4; // Pulse Register for CS 4
+ AT91_REG SMC_CYCLE4; // Cycle Register for CS 4
+ AT91_REG SMC_CTRL4; // Control Register for CS 4
+ AT91_REG SMC_SETUP5; // Setup Register for CS 5
+ AT91_REG SMC_PULSE5; // Pulse Register for CS 5
+ AT91_REG SMC_CYCLE5; // Cycle Register for CS 5
+ AT91_REG SMC_CTRL5; // Control Register for CS 5
+ AT91_REG SMC_SETUP6; // Setup Register for CS 6
+ AT91_REG SMC_PULSE6; // Pulse Register for CS 6
+ AT91_REG SMC_CYCLE6; // Cycle Register for CS 6
+ AT91_REG SMC_CTRL6; // Control Register for CS 6
+ AT91_REG SMC_SETUP7; // Setup Register for CS 7
+ AT91_REG SMC_PULSE7; // Pulse Register for CS 7
+ AT91_REG SMC_CYCLE7; // Cycle Register for CS 7
+ AT91_REG SMC_CTRL7; // Control Register for CS 7
+} AT91S_SMC, *AT91PS_SMC;
+#else
+#define SETUP0 (AT91_CAST(AT91_REG *) 0x00000000) // (SETUP0) Setup Register for CS 0
+#define PULSE0 (AT91_CAST(AT91_REG *) 0x00000004) // (PULSE0) Pulse Register for CS 0
+#define CYCLE0 (AT91_CAST(AT91_REG *) 0x00000008) // (CYCLE0) Cycle Register for CS 0
+#define CTRL0 (AT91_CAST(AT91_REG *) 0x0000000C) // (CTRL0) Control Register for CS 0
+#define SETUP1 (AT91_CAST(AT91_REG *) 0x00000010) // (SETUP1) Setup Register for CS 1
+#define PULSE1 (AT91_CAST(AT91_REG *) 0x00000014) // (PULSE1) Pulse Register for CS 1
+#define CYCLE1 (AT91_CAST(AT91_REG *) 0x00000018) // (CYCLE1) Cycle Register for CS 1
+#define CTRL1 (AT91_CAST(AT91_REG *) 0x0000001C) // (CTRL1) Control Register for CS 1
+#define SETUP2 (AT91_CAST(AT91_REG *) 0x00000020) // (SETUP2) Setup Register for CS 2
+#define PULSE2 (AT91_CAST(AT91_REG *) 0x00000024) // (PULSE2) Pulse Register for CS 2
+#define CYCLE2 (AT91_CAST(AT91_REG *) 0x00000028) // (CYCLE2) Cycle Register for CS 2
+#define CTRL2 (AT91_CAST(AT91_REG *) 0x0000002C) // (CTRL2) Control Register for CS 2
+#define SETUP3 (AT91_CAST(AT91_REG *) 0x00000030) // (SETUP3) Setup Register for CS 3
+#define PULSE3 (AT91_CAST(AT91_REG *) 0x00000034) // (PULSE3) Pulse Register for CS 3
+#define CYCLE3 (AT91_CAST(AT91_REG *) 0x00000038) // (CYCLE3) Cycle Register for CS 3
+#define CTRL3 (AT91_CAST(AT91_REG *) 0x0000003C) // (CTRL3) Control Register for CS 3
+#define SETUP4 (AT91_CAST(AT91_REG *) 0x00000040) // (SETUP4) Setup Register for CS 4
+#define PULSE4 (AT91_CAST(AT91_REG *) 0x00000044) // (PULSE4) Pulse Register for CS 4
+#define CYCLE4 (AT91_CAST(AT91_REG *) 0x00000048) // (CYCLE4) Cycle Register for CS 4
+#define CTRL4 (AT91_CAST(AT91_REG *) 0x0000004C) // (CTRL4) Control Register for CS 4
+#define SETUP5 (AT91_CAST(AT91_REG *) 0x00000050) // (SETUP5) Setup Register for CS 5
+#define PULSE5 (AT91_CAST(AT91_REG *) 0x00000054) // (PULSE5) Pulse Register for CS 5
+#define CYCLE5 (AT91_CAST(AT91_REG *) 0x00000058) // (CYCLE5) Cycle Register for CS 5
+#define CTRL5 (AT91_CAST(AT91_REG *) 0x0000005C) // (CTRL5) Control Register for CS 5
+#define SETUP6 (AT91_CAST(AT91_REG *) 0x00000060) // (SETUP6) Setup Register for CS 6
+#define PULSE6 (AT91_CAST(AT91_REG *) 0x00000064) // (PULSE6) Pulse Register for CS 6
+#define CYCLE6 (AT91_CAST(AT91_REG *) 0x00000068) // (CYCLE6) Cycle Register for CS 6
+#define CTRL6 (AT91_CAST(AT91_REG *) 0x0000006C) // (CTRL6) Control Register for CS 6
+#define SETUP7 (AT91_CAST(AT91_REG *) 0x00000070) // (SETUP7) Setup Register for CS 7
+#define PULSE7 (AT91_CAST(AT91_REG *) 0x00000074) // (PULSE7) Pulse Register for CS 7
+#define CYCLE7 (AT91_CAST(AT91_REG *) 0x00000078) // (CYCLE7) Cycle Register for CS 7
+#define CTRL7 (AT91_CAST(AT91_REG *) 0x0000007C) // (CTRL7) Control Register for CS 7
+
+#endif
+// -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
+#define AT91C_SMC_NWESETUP (0x3F << 0) // (SMC) NWE Setup Length
+#define AT91C_SMC_NCSSETUPWR (0x3F << 8) // (SMC) NCS Setup Length in WRite Access
+#define AT91C_SMC_NRDSETUP (0x3F << 16) // (SMC) NRD Setup Length
+#define AT91C_SMC_NCSSETUPRD (0x3F << 24) // (SMC) NCS Setup Length in ReaD Access
+// -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
+#define AT91C_SMC_NWEPULSE (0x7F << 0) // (SMC) NWE Pulse Length
+#define AT91C_SMC_NCSPULSEWR (0x7F << 8) // (SMC) NCS Pulse Length in WRite Access
+#define AT91C_SMC_NRDPULSE (0x7F << 16) // (SMC) NRD Pulse Length
+#define AT91C_SMC_NCSPULSERD (0x7F << 24) // (SMC) NCS Pulse Length in ReaD Access
+// -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
+#define AT91C_SMC_NWECYCLE (0x1FF << 0) // (SMC) Total Write Cycle Length
+#define AT91C_SMC_NRDCYCLE (0x1FF << 16) // (SMC) Total Read Cycle Length
+// -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
+#define AT91C_SMC_READMODE (0x1 << 0) // (SMC) Read Mode
+#define AT91C_SMC_WRITEMODE (0x1 << 1) // (SMC) Write Mode
+#define AT91C_SMC_NWAITM (0x3 << 5) // (SMC) NWAIT Mode
+#define AT91C_SMC_NWAITM_NWAIT_DISABLE (0x0 << 5) // (SMC) External NWAIT disabled.
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN (0x2 << 5) // (SMC) External NWAIT enabled in frozen mode.
+#define AT91C_SMC_NWAITM_NWAIT_ENABLE_READY (0x3 << 5) // (SMC) External NWAIT enabled in ready mode.
+#define AT91C_SMC_BAT (0x1 << 8) // (SMC) Byte Access Type
+#define AT91C_SMC_BAT_BYTE_SELECT (0x0 << 8) // (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
+#define AT91C_SMC_BAT_BYTE_WRITE (0x1 << 8) // (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
+#define AT91C_SMC_DBW (0x3 << 12) // (SMC) Data Bus Width
+#define AT91C_SMC_DBW_WIDTH_EIGTH_BITS (0x0 << 12) // (SMC) 8 bits.
+#define AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS (0x1 << 12) // (SMC) 16 bits.
+#define AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS (0x2 << 12) // (SMC) 32 bits.
+#define AT91C_SMC_TDF (0xF << 16) // (SMC) Data Float Time.
+#define AT91C_SMC_TDFEN (0x1 << 20) // (SMC) TDF Enabled.
+#define AT91C_SMC_PMEN (0x1 << 24) // (SMC) Page Mode Enabled.
+#define AT91C_SMC_PS (0x3 << 28) // (SMC) Page Size
+#define AT91C_SMC_PS_SIZE_FOUR_BYTES (0x0 << 28) // (SMC) 4 bytes.
+#define AT91C_SMC_PS_SIZE_EIGHT_BYTES (0x1 << 28) // (SMC) 8 bytes.
+#define AT91C_SMC_PS_SIZE_SIXTEEN_BYTES (0x2 << 28) // (SMC) 16 bytes.
+#define AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES (0x3 << 28) // (SMC) 32 bytes.
+// -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
+// -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
+// -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
+// -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
+// -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Slave Priority Registers
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX_PRS {
+ AT91_REG MATRIX_PRAS; // Slave Priority Registers A for Slave
+ AT91_REG MATRIX_PRBS; // Slave Priority Registers B for Slave
+} AT91S_MATRIX_PRS, *AT91PS_MATRIX_PRS;
+#else
+#define MATRIX_PRAS (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_PRAS) Slave Priority Registers A for Slave
+#define MATRIX_PRBS (AT91_CAST(AT91_REG *) 0x00000004) // (MATRIX_PRBS) Slave Priority Registers B for Slave
+
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR AHB Matrix Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_MATRIX {
+ AT91_REG MATRIX_MCFG[6]; // Master Configuration Register
+ AT91_REG Reserved0[10]; //
+ AT91_REG MATRIX_SCFG[10]; // Slave Configuration Register
+ AT91_REG Reserved1[6]; //
+ AT91S_MATRIX_PRS MATRIX_PRS[10]; // Slave Priority Registers
+ AT91_REG Reserved2[12]; //
+ AT91_REG MATRIX_MRCR; // Master Remp Control Register
+ AT91_REG Reserved3[11]; //
+ AT91_REG MATRIX_EBICSA; // EBI Chip Select Assignment Register
+ AT91_REG MATRIX_USBPCR; // USB Pad Pullup Control Register
+} AT91S_MATRIX, *AT91PS_MATRIX;
+#else
+#define MATRIX_MCFG (AT91_CAST(AT91_REG *) 0x00000000) // (MATRIX_MCFG) Master Configuration Register
+#define MATRIX_SCFG (AT91_CAST(AT91_REG *) 0x00000040) // (MATRIX_SCFG) Slave Configuration Register
+#define MATRIX_MRCR (AT91_CAST(AT91_REG *) 0x00000100) // (MATRIX_MRCR) Master Remp Control Register
+#define MATRIX_EBICSA (AT91_CAST(AT91_REG *) 0x00000130) // (MATRIX_EBICSA) EBI Chip Select Assignment Register
+#define MATRIX_USBPCR (AT91_CAST(AT91_REG *) 0x00000134) // (MATRIX_USBPCR) USB Pad Pullup Control Register
+
+#endif
+// -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register rom --------
+#define AT91C_MATRIX_ULBT (0x7 << 0) // (MATRIX) Undefined Length Burst Type
+// -------- MATRIX_SCFG : (MATRIX Offset: 0x40) Slave Configuration Register --------
+#define AT91C_MATRIX_SLOT_CYCLE (0xFF << 0) // (MATRIX) Maximum Number of Allowed Cycles for a Burst
+#define AT91C_MATRIX_DEFMSTR_TYPE (0x3 << 16) // (MATRIX) Default Master Type
+#define AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR (0x0 << 16) // (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
+#define AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR (0x1 << 16) // (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
+#define AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR (0x2 << 16) // (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
+#define AT91C_MATRIX_FIXED_DEFMSTR (0x7 << 18) // (MATRIX) Fixed Index of Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_ARM7TDMI (0x0 << 18) // (MATRIX) ARM7TDMI Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_PDC (0x1 << 18) // (MATRIX) PDC Master is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_MPMA (0x2 << 18) // (MATRIX) MP Master A is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_MPMB (0x3 << 18) // (MATRIX) MP Master B is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_MPMC (0x4 << 18) // (MATRIX) MP Master C is Default Master
+#define AT91C_MATRIX_FIXED_DEFMSTR_MPMD (0x5 << 18) // (MATRIX) MP Master D is Default Master
+#define AT91C_MATRIX_ARBT (0x3 << 24) // (MATRIX) Arbitration Type
+// -------- MATRIX_MRCR : (MATRIX Offset: 0x100) MRCR Register --------
+#define AT91C_MATRIX_RCB0_ARM7TDMI (0x1 << 0) // (MATRIX) Remap Command Bit for ARM7TDMI
+#define AT91C_MATRIX_RCB1_PDC (0x1 << 1) // (MATRIX) Remap Command Bit for PDC
+#define AT91C_MATRIX_RCB2_MPMA (0x1 << 2) // (MATRIX) Remap Command Bit for MP Master A
+#define AT91C_MATRIX_RCB3_MPMB (0x1 << 3) // (MATRIX) Remap Command Bit for MP Master B
+#define AT91C_MATRIX_RCB4_MPMC (0x1 << 4) // (MATRIX) Remap Command Bit for MP Master C
+#define AT91C_MATRIX_RCB5_MPMD (0x1 << 5) // (MATRIX) Remap Command Bit for MP Master D
+// -------- MATRIX_EBICSA : (MATRIX Offset: 0x130) EBI Chip Select Assignment Register --------
+#define AT91C_MATRIX_EBI (0x1 << 1) // (MATRIX) EBI Chip Select 1 Assignment
+#define AT91C_MATRIX_EBI_CS1A (0x0 << 1) // (MATRIX) EBI Chip Select 1 is assigned to the Static Memory Controller
+#define AT91C_MATRIX_EBI_CS1A_SDRAMC (0x1 << 1) // (MATRIX) EBI Chip Select 1 is assigned to the SDRAM Controller
+#define AT91C_MATRIX_EBI_CS3A (0x0 << 3) // (MATRIX) EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC
+#define AT91C_MATRIX_EBI_CS3A_SM (0x1 << 3) // (MATRIX) EBI Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated
+#define AT91C_MATRIX_EBI_CS4A (0x0 << 4) // (MATRIX) EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC
+#define AT91C_MATRIX_EBI_CS4A_CF0 (0x1 << 4) // (MATRIX) EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated
+#define AT91C_MATRIX_EBI_CS5A (0x0 << 5) // (MATRIX) EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC
+#define AT91C_MATRIX_EBI_CS5A_CF1 (0x1 << 5) // (MATRIX) EBI Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated
+#define AT91C_MATRIX_EBI_DBPUC (0x1 << 8) // (MATRIX) EBI Data Bus Pull-Up Configuration
+// -------- MATRIX_USBPCR : (MATRIX Offset: 0x134) USB Pad Pull-up Control Register --------
+#define AT91C_MATRIX_USBPCR_PUON (0x1 << 30) // (MATRIX) UDP Pad Pull-up Enable
+#define AT91C_MATRIX_USBPCR_IDLE (0x1 << 31) // (MATRIX) Pull-up Idle
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Peripheral DMA Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PDC {
+ AT91_REG PDC_RPR; // Receive Pointer Register
+ AT91_REG PDC_RCR; // Receive Counter Register
+ AT91_REG PDC_TPR; // Transmit Pointer Register
+ AT91_REG PDC_TCR; // Transmit Counter Register
+ AT91_REG PDC_RNPR; // Receive Next Pointer Register
+ AT91_REG PDC_RNCR; // Receive Next Counter Register
+ AT91_REG PDC_TNPR; // Transmit Next Pointer Register
+ AT91_REG PDC_TNCR; // Transmit Next Counter Register
+ AT91_REG PDC_PTCR; // PDC Transfer Control Register
+ AT91_REG PDC_PTSR; // PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+#else
+#define PDC_RPR (AT91_CAST(AT91_REG *) 0x00000000) // (PDC_RPR) Receive Pointer Register
+#define PDC_RCR (AT91_CAST(AT91_REG *) 0x00000004) // (PDC_RCR) Receive Counter Register
+#define PDC_TPR (AT91_CAST(AT91_REG *) 0x00000008) // (PDC_TPR) Transmit Pointer Register
+#define PDC_TCR (AT91_CAST(AT91_REG *) 0x0000000C) // (PDC_TCR) Transmit Counter Register
+#define PDC_RNPR (AT91_CAST(AT91_REG *) 0x00000010) // (PDC_RNPR) Receive Next Pointer Register
+#define PDC_RNCR (AT91_CAST(AT91_REG *) 0x00000014) // (PDC_RNCR) Receive Next Counter Register
+#define PDC_TNPR (AT91_CAST(AT91_REG *) 0x00000018) // (PDC_TNPR) Transmit Next Pointer Register
+#define PDC_TNCR (AT91_CAST(AT91_REG *) 0x0000001C) // (PDC_TNCR) Transmit Next Counter Register
+#define PDC_PTCR (AT91_CAST(AT91_REG *) 0x00000020) // (PDC_PTCR) PDC Transfer Control Register
+#define PDC_PTSR (AT91_CAST(AT91_REG *) 0x00000024) // (PDC_PTSR) PDC Transfer Status Register
+
+#endif
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
+#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Debug Unit
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_DBGU {
+ AT91_REG DBGU_CR; // Control Register
+ AT91_REG DBGU_MR; // Mode Register
+ AT91_REG DBGU_IER; // Interrupt Enable Register
+ AT91_REG DBGU_IDR; // Interrupt Disable Register
+ AT91_REG DBGU_IMR; // Interrupt Mask Register
+ AT91_REG DBGU_CSR; // Channel Status Register
+ AT91_REG DBGU_RHR; // Receiver Holding Register
+ AT91_REG DBGU_THR; // Transmitter Holding Register
+ AT91_REG DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved0[7]; //
+ AT91_REG DBGU_CIDR; // Chip ID Register
+ AT91_REG DBGU_EXID; // Chip ID Extension Register
+ AT91_REG DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved1[45]; //
+ AT91_REG DBGU_RPR; // Receive Pointer Register
+ AT91_REG DBGU_RCR; // Receive Counter Register
+ AT91_REG DBGU_TPR; // Transmit Pointer Register
+ AT91_REG DBGU_TCR; // Transmit Counter Register
+ AT91_REG DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG DBGU_PTSR; // PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+#else
+#define DBGU_CR (AT91_CAST(AT91_REG *) 0x00000000) // (DBGU_CR) Control Register
+#define DBGU_MR (AT91_CAST(AT91_REG *) 0x00000004) // (DBGU_MR) Mode Register
+#define DBGU_IER (AT91_CAST(AT91_REG *) 0x00000008) // (DBGU_IER) Interrupt Enable Register
+#define DBGU_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (DBGU_IDR) Interrupt Disable Register
+#define DBGU_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (DBGU_IMR) Interrupt Mask Register
+#define DBGU_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (DBGU_CSR) Channel Status Register
+#define DBGU_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (DBGU_RHR) Receiver Holding Register
+#define DBGU_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (DBGU_THR) Transmitter Holding Register
+#define DBGU_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (DBGU_BRGR) Baud Rate Generator Register
+#define DBGU_CIDR (AT91_CAST(AT91_REG *) 0x00000040) // (DBGU_CIDR) Chip ID Register
+#define DBGU_EXID (AT91_CAST(AT91_REG *) 0x00000044) // (DBGU_EXID) Chip ID Extension Register
+#define DBGU_FNTR (AT91_CAST(AT91_REG *) 0x00000048) // (DBGU_FNTR) Force NTRST Register
+
+#endif
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
+#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
+#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type
+#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity
+#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity
+#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space)
+#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark)
+#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity
+#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode
+#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
+#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
+#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_AIC {
+ AT91_REG AIC_SMR[32]; // Source Mode Register
+ AT91_REG AIC_SVR[32]; // Source Vector Register
+ AT91_REG AIC_IVR; // IRQ Vector Register
+ AT91_REG AIC_FVR; // FIQ Vector Register
+ AT91_REG AIC_ISR; // Interrupt Status Register
+ AT91_REG AIC_IPR; // Interrupt Pending Register
+ AT91_REG AIC_IMR; // Interrupt Mask Register
+ AT91_REG AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG AIC_SPU; // Spurious Vector Register
+ AT91_REG AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved1[1]; //
+ AT91_REG AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG AIC_FFSR; // Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+#else
+#define AIC_SMR (AT91_CAST(AT91_REG *) 0x00000000) // (AIC_SMR) Source Mode Register
+#define AIC_SVR (AT91_CAST(AT91_REG *) 0x00000080) // (AIC_SVR) Source Vector Register
+#define AIC_IVR (AT91_CAST(AT91_REG *) 0x00000100) // (AIC_IVR) IRQ Vector Register
+#define AIC_FVR (AT91_CAST(AT91_REG *) 0x00000104) // (AIC_FVR) FIQ Vector Register
+#define AIC_ISR (AT91_CAST(AT91_REG *) 0x00000108) // (AIC_ISR) Interrupt Status Register
+#define AIC_IPR (AT91_CAST(AT91_REG *) 0x0000010C) // (AIC_IPR) Interrupt Pending Register
+#define AIC_IMR (AT91_CAST(AT91_REG *) 0x00000110) // (AIC_IMR) Interrupt Mask Register
+#define AIC_CISR (AT91_CAST(AT91_REG *) 0x00000114) // (AIC_CISR) Core Interrupt Status Register
+#define AIC_IECR (AT91_CAST(AT91_REG *) 0x00000120) // (AIC_IECR) Interrupt Enable Command Register
+#define AIC_IDCR (AT91_CAST(AT91_REG *) 0x00000124) // (AIC_IDCR) Interrupt Disable Command Register
+#define AIC_ICCR (AT91_CAST(AT91_REG *) 0x00000128) // (AIC_ICCR) Interrupt Clear Command Register
+#define AIC_ISCR (AT91_CAST(AT91_REG *) 0x0000012C) // (AIC_ISCR) Interrupt Set Command Register
+#define AIC_EOICR (AT91_CAST(AT91_REG *) 0x00000130) // (AIC_EOICR) End of Interrupt Command Register
+#define AIC_SPU (AT91_CAST(AT91_REG *) 0x00000134) // (AIC_SPU) Spurious Vector Register
+#define AIC_DCR (AT91_CAST(AT91_REG *) 0x00000138) // (AIC_DCR) Debug Control Register (Protect)
+#define AIC_FFER (AT91_CAST(AT91_REG *) 0x00000140) // (AIC_FFER) Fast Forcing Enable Register
+#define AIC_FFDR (AT91_CAST(AT91_REG *) 0x00000144) // (AIC_FFDR) Fast Forcing Disable Register
+#define AIC_FFSR (AT91_CAST(AT91_REG *) 0x00000148) // (AIC_FFSR) Fast Forcing Status Register
+
+#endif
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
+#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level
+#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level
+#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type
+#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE (0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
+#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED (0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
+#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL (0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
+#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE (0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
+#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
+#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PIO {
+ AT91_REG PIO_PER; // PIO Enable Register
+ AT91_REG PIO_PDR; // PIO Disable Register
+ AT91_REG PIO_PSR; // PIO Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PIO_OER; // Output Enable Register
+ AT91_REG PIO_ODR; // Output Disable Registerr
+ AT91_REG PIO_OSR; // Output Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PIO_IFER; // Input Filter Enable Register
+ AT91_REG PIO_IFDR; // Input Filter Disable Register
+ AT91_REG PIO_IFSR; // Input Filter Status Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG PIO_SODR; // Set Output Data Register
+ AT91_REG PIO_CODR; // Clear Output Data Register
+ AT91_REG PIO_ODSR; // Output Data Status Register
+ AT91_REG PIO_PDSR; // Pin Data Status Register
+ AT91_REG PIO_IER; // Interrupt Enable Register
+ AT91_REG PIO_IDR; // Interrupt Disable Register
+ AT91_REG PIO_IMR; // Interrupt Mask Register
+ AT91_REG PIO_ISR; // Interrupt Status Register
+ AT91_REG PIO_MDER; // Multi-driver Enable Register
+ AT91_REG PIO_MDDR; // Multi-driver Disable Register
+ AT91_REG PIO_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved3[1]; //
+ AT91_REG PIO_PPUDR; // Pull-up Disable Register
+ AT91_REG PIO_PPUER; // Pull-up Enable Register
+ AT91_REG PIO_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved4[1]; //
+ AT91_REG PIO_ASR; // Select A Register
+ AT91_REG PIO_BSR; // Select B Register
+ AT91_REG PIO_ABSR; // AB Select Status Register
+ AT91_REG Reserved5[9]; //
+ AT91_REG PIO_OWER; // Output Write Enable Register
+ AT91_REG PIO_OWDR; // Output Write Disable Register
+ AT91_REG PIO_OWSR; // Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+#else
+#define PIO_PER (AT91_CAST(AT91_REG *) 0x00000000) // (PIO_PER) PIO Enable Register
+#define PIO_PDR (AT91_CAST(AT91_REG *) 0x00000004) // (PIO_PDR) PIO Disable Register
+#define PIO_PSR (AT91_CAST(AT91_REG *) 0x00000008) // (PIO_PSR) PIO Status Register
+#define PIO_OER (AT91_CAST(AT91_REG *) 0x00000010) // (PIO_OER) Output Enable Register
+#define PIO_ODR (AT91_CAST(AT91_REG *) 0x00000014) // (PIO_ODR) Output Disable Registerr
+#define PIO_OSR (AT91_CAST(AT91_REG *) 0x00000018) // (PIO_OSR) Output Status Register
+#define PIO_IFER (AT91_CAST(AT91_REG *) 0x00000020) // (PIO_IFER) Input Filter Enable Register
+#define PIO_IFDR (AT91_CAST(AT91_REG *) 0x00000024) // (PIO_IFDR) Input Filter Disable Register
+#define PIO_IFSR (AT91_CAST(AT91_REG *) 0x00000028) // (PIO_IFSR) Input Filter Status Register
+#define PIO_SODR (AT91_CAST(AT91_REG *) 0x00000030) // (PIO_SODR) Set Output Data Register
+#define PIO_CODR (AT91_CAST(AT91_REG *) 0x00000034) // (PIO_CODR) Clear Output Data Register
+#define PIO_ODSR (AT91_CAST(AT91_REG *) 0x00000038) // (PIO_ODSR) Output Data Status Register
+#define PIO_PDSR (AT91_CAST(AT91_REG *) 0x0000003C) // (PIO_PDSR) Pin Data Status Register
+#define PIO_IER (AT91_CAST(AT91_REG *) 0x00000040) // (PIO_IER) Interrupt Enable Register
+#define PIO_IDR (AT91_CAST(AT91_REG *) 0x00000044) // (PIO_IDR) Interrupt Disable Register
+#define PIO_IMR (AT91_CAST(AT91_REG *) 0x00000048) // (PIO_IMR) Interrupt Mask Register
+#define PIO_ISR (AT91_CAST(AT91_REG *) 0x0000004C) // (PIO_ISR) Interrupt Status Register
+#define PIO_MDER (AT91_CAST(AT91_REG *) 0x00000050) // (PIO_MDER) Multi-driver Enable Register
+#define PIO_MDDR (AT91_CAST(AT91_REG *) 0x00000054) // (PIO_MDDR) Multi-driver Disable Register
+#define PIO_MDSR (AT91_CAST(AT91_REG *) 0x00000058) // (PIO_MDSR) Multi-driver Status Register
+#define PIO_PPUDR (AT91_CAST(AT91_REG *) 0x00000060) // (PIO_PPUDR) Pull-up Disable Register
+#define PIO_PPUER (AT91_CAST(AT91_REG *) 0x00000064) // (PIO_PPUER) Pull-up Enable Register
+#define PIO_PPUSR (AT91_CAST(AT91_REG *) 0x00000068) // (PIO_PPUSR) Pull-up Status Register
+#define PIO_ASR (AT91_CAST(AT91_REG *) 0x00000070) // (PIO_ASR) Select A Register
+#define PIO_BSR (AT91_CAST(AT91_REG *) 0x00000074) // (PIO_BSR) Select B Register
+#define PIO_ABSR (AT91_CAST(AT91_REG *) 0x00000078) // (PIO_ABSR) AB Select Status Register
+#define PIO_OWER (AT91_CAST(AT91_REG *) 0x000000A0) // (PIO_OWER) Output Write Enable Register
+#define PIO_OWDR (AT91_CAST(AT91_REG *) 0x000000A4) // (PIO_OWDR) Output Write Disable Register
+#define PIO_OWSR (AT91_CAST(AT91_REG *) 0x000000A8) // (PIO_OWSR) Output Write Status Register
+
+#endif
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Clock Generator Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_CKGR {
+ AT91_REG CKGR_MOR; // Main Oscillator Register
+ AT91_REG CKGR_MCFR; // Main Clock Frequency Register
+ AT91_REG CKGR_PLLAR; // PLL A Register
+ AT91_REG CKGR_PLLBR; // PLL B Register
+} AT91S_CKGR, *AT91PS_CKGR;
+#else
+#define CKGR_MOR (AT91_CAST(AT91_REG *) 0x00000000) // (CKGR_MOR) Main Oscillator Register
+#define CKGR_MCFR (AT91_CAST(AT91_REG *) 0x00000004) // (CKGR_MCFR) Main Clock Frequency Register
+#define CKGR_PLLAR (AT91_CAST(AT91_REG *) 0x00000008) // (CKGR_PLLAR) PLL A Register
+#define CKGR_PLLBR (AT91_CAST(AT91_REG *) 0x0000000C) // (CKGR_PLLBR) PLL B Register
+
+#endif
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
+#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
+#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLAR : (CKGR Offset: 0x8) PLL A Register --------
+#define AT91C_CKGR_DIVA (0xFF << 0) // (CKGR) Divider A Selected
+#define AT91C_CKGR_DIVA_0 (0x0) // (CKGR) Divider A output is 0
+#define AT91C_CKGR_DIVA_BYPASS (0x1) // (CKGR) Divider A is bypassed
+#define AT91C_CKGR_PLLACOUNT (0x3F << 8) // (CKGR) PLL A Counter
+#define AT91C_CKGR_OUTA (0x3 << 14) // (CKGR) PLL A Output Frequency Range
+#define AT91C_CKGR_OUTA_0 (0x0 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_1 (0x1 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_2 (0x2 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_OUTA_3 (0x3 << 14) // (CKGR) Please refer to the PLLA datasheet
+#define AT91C_CKGR_MULA (0x7FF << 16) // (CKGR) PLL A Multiplier
+#define AT91C_CKGR_SRCA (0x1 << 29) // (CKGR)
+// -------- CKGR_PLLBR : (CKGR Offset: 0xc) PLL B Register --------
+#define AT91C_CKGR_DIVB (0xFF << 0) // (CKGR) Divider B Selected
+#define AT91C_CKGR_DIVB_0 (0x0) // (CKGR) Divider B output is 0
+#define AT91C_CKGR_DIVB_BYPASS (0x1) // (CKGR) Divider B is bypassed
+#define AT91C_CKGR_PLLBCOUNT (0x3F << 8) // (CKGR) PLL B Counter
+#define AT91C_CKGR_OUTB (0x3 << 14) // (CKGR) PLL B Output Frequency Range
+#define AT91C_CKGR_OUTB_0 (0x0 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_1 (0x1 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_2 (0x2 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_OUTB_3 (0x3 << 14) // (CKGR) Please refer to the PLLB datasheet
+#define AT91C_CKGR_MULB (0x7FF << 16) // (CKGR) PLL B Multiplier
+#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Power Management Controler
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PMC {
+ AT91_REG PMC_SCER; // System Clock Enable Register
+ AT91_REG PMC_SCDR; // System Clock Disable Register
+ AT91_REG PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG PMC_MOR; // Main Oscillator Register
+ AT91_REG PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG PMC_PLLAR; // PLL A Register
+ AT91_REG PMC_PLLBR; // PLL B Register
+ AT91_REG PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved2[3]; //
+ AT91_REG PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG PMC_IER; // Interrupt Enable Register
+ AT91_REG PMC_IDR; // Interrupt Disable Register
+ AT91_REG PMC_SR; // Status Register
+ AT91_REG PMC_IMR; // Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+#else
+#define PMC_SCER (AT91_CAST(AT91_REG *) 0x00000000) // (PMC_SCER) System Clock Enable Register
+#define PMC_SCDR (AT91_CAST(AT91_REG *) 0x00000004) // (PMC_SCDR) System Clock Disable Register
+#define PMC_SCSR (AT91_CAST(AT91_REG *) 0x00000008) // (PMC_SCSR) System Clock Status Register
+#define PMC_PCER (AT91_CAST(AT91_REG *) 0x00000010) // (PMC_PCER) Peripheral Clock Enable Register
+#define PMC_PCDR (AT91_CAST(AT91_REG *) 0x00000014) // (PMC_PCDR) Peripheral Clock Disable Register
+#define PMC_PCSR (AT91_CAST(AT91_REG *) 0x00000018) // (PMC_PCSR) Peripheral Clock Status Register
+#define PMC_MCKR (AT91_CAST(AT91_REG *) 0x00000030) // (PMC_MCKR) Master Clock Register
+#define PMC_PCKR (AT91_CAST(AT91_REG *) 0x00000040) // (PMC_PCKR) Programmable Clock Register
+#define PMC_IER (AT91_CAST(AT91_REG *) 0x00000060) // (PMC_IER) Interrupt Enable Register
+#define PMC_IDR (AT91_CAST(AT91_REG *) 0x00000064) // (PMC_IDR) Interrupt Disable Register
+#define PMC_SR (AT91_CAST(AT91_REG *) 0x00000068) // (PMC_SR) Status Register
+#define PMC_IMR (AT91_CAST(AT91_REG *) 0x0000006C) // (PMC_IMR) Interrupt Mask Register
+
+#endif
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
+#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock
+#define AT91C_PMC_UHP (0x1 << 6) // (PMC) USB Host Port Clock
+#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device clock enable
+#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3 (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
+// -------- PMC_PCER : (PMC Offset: 0x10) Peripheral Clock Enable Register --------
+#define AT91C_PMC_PIOA (0x1 << 2) // (PMC) PIOA clock enable
+#define AT91C_PMC_PIOB (0x1 << 3) // (PMC) PIOB clock enable
+#define AT91C_PMC_US0 (0x1 << 4) // (PMC) USART0 clock enable
+#define AT91C_PMC_US1 (0x1 << 5) // (PMC) USART1 clock enable
+#define AT91C_PMC_SPI0 (0x1 << 6) // (PMC) SPI0 clock enable
+#define AT91C_PMC_TC0 (0x1 << 7) // (PMC) Timer/Counter0 clock enable
+#define AT91C_PMC_TC1 (0x1 << 8) // (PMC) Timer/Counter1 clock enable
+#define AT91C_PMC_TC2 (0x1 << 9) // (PMC) Timer/Counter2 clock enable
+#define AT91C_PMC_ADC (0x1 << 11) // (PMC) ADC clock enable
+#define AT91C_PMC_MPP0 (0x1 << 12) // (PMC) MP APB peripheral 0 clock enable
+#define AT91C_PMC_MPP1 (0x1 << 13) // (PMC) MP APB peripheral 1 clock enable
+#define AT91C_PMC_MPP2 (0x1 << 14) // (PMC) MP APB peripheral 2 clock enable
+#define AT91C_PMC_MPP3 (0x1 << 15) // (PMC) MP APB peripheral 3 clock enable
+#define AT91C_PMC_MPP4 (0x1 << 16) // (PMC) MP APB peripheral 4 clock enable
+#define AT91C_PMC_MPP5 (0x1 << 17) // (PMC) MP APB peripheral 5 clock enable
+#define AT91C_PMC_MPP6 (0x1 << 18) // (PMC) MP APB peripheral 6 clock enable
+#define AT91C_PMC_MPP7 (0x1 << 19) // (PMC) MP APB peripheral 7 clock enable
+#define AT91C_PMC_MPP8 (0x1 << 20) // (PMC) MP APB peripheral 8 clock enable
+#define AT91C_PMC_MPP9 (0x1 << 21) // (PMC) MP APB peripheral 9 clock enable
+#define AT91C_PMC_MPP10 (0x1 << 22) // (PMC) MP APB peripheral 10 clock enable
+#define AT91C_PMC_MPP11 (0x1 << 23) // (PMC) MP APB peripheral 11 clock enable
+#define AT91C_PMC_MPP12 (0x1 << 24) // (PMC) MP APB peripheral 12 clock enable
+#define AT91C_PMC_MPP13 (0x1 << 25) // (PMC) MP APB peripheral 13 clock enable
+#define AT91C_PMC_MPMA (0x1 << 26) // (PMC) MP Master A clock enable
+#define AT91C_PMC_MPMB (0x1 << 27) // (PMC) MP Master B clock enable
+#define AT91C_PMC_MPMC (0x1 << 28) // (PMC) MP Master C clock enable
+#define AT91C_PMC_MPMD (0x1 << 29) // (PMC) MP Master D clock enable
+#define AT91C_PMC_IRQ0 (0x1 << 30) // (PMC) AIC IRQ0 clock enable
+#define AT91C_PMC_IRQ1 (0x1 << 31) // (PMC) AIC IRQ1 clock enable
+// -------- PMC_PCDR : (PMC Offset: 0x14) Peripheral Clock Disable Register --------
+// -------- PMC_PCSR : (PMC Offset: 0x18) Peripheral Clock Status Register --------
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
+// -------- CKGR_PLLAR : (PMC Offset: 0x28) PLL A Register --------
+// -------- CKGR_PLLBR : (PMC Offset: 0x2c) PLL B Register --------
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
+#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection
+#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected
+#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected
+#define AT91C_PMC_CSS_PLLA_CLK (0x2) // (PMC) Clock from PLL A is selected
+#define AT91C_PMC_CSS_PLLB_CLK (0x3) // (PMC) Clock from PLL B is selected
+#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler
+#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock
+#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2
+#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4
+#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8
+#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16
+#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32
+#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
+#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKA (0x1 << 1) // (PMC) PLL A Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCKB (0x1 << 2) // (PMC) PLL B Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) Master Clock Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
+#define AT91C_PMC_OSC_SEL (0x1 << 7) // (PMC) Slow clock oscillator selection
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Reset Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RSTC {
+ AT91_REG RSTC_RCR; // Reset Control Register
+ AT91_REG RSTC_RSR; // Reset Status Register
+ AT91_REG RSTC_RMR; // Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+#else
+#define RSTC_RCR (AT91_CAST(AT91_REG *) 0x00000000) // (RSTC_RCR) Reset Control Register
+#define RSTC_RSR (AT91_CAST(AT91_REG *) 0x00000004) // (RSTC_RSR) Reset Status Register
+#define RSTC_RMR (AT91_CAST(AT91_REG *) 0x00000008) // (RSTC_RMR) Reset Mode Register
+
+#endif
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
+#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
+#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status
+#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type
+#define AT91C_RSTC_RSTTYP_GENERAL (0x0 << 8) // (RSTC) General reset. Both VDDCORE and VDDBU rising.
+#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software.
+#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low.
+#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
+#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Shut Down Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SHDWC {
+ AT91_REG SHDWC_SHCR; // Shut Down Control Register
+ AT91_REG SHDWC_SHMR; // Shut Down Mode Register
+ AT91_REG SHDWC_SHSR; // Shut Down Status Register
+} AT91S_SHDWC, *AT91PS_SHDWC;
+#else
+#define SHDWC_SHCR (AT91_CAST(AT91_REG *) 0x00000000) // (SHDWC_SHCR) Shut Down Control Register
+#define SHDWC_SHMR (AT91_CAST(AT91_REG *) 0x00000004) // (SHDWC_SHMR) Shut Down Mode Register
+#define SHDWC_SHSR (AT91_CAST(AT91_REG *) 0x00000008) // (SHDWC_SHSR) Shut Down Status Register
+
+#endif
+// -------- SHDWC_SHCR : (SHDWC Offset: 0x0) Shut Down Control Register --------
+#define AT91C_SHDWC_SHDW (0x1 << 0) // (SHDWC) Processor Reset
+#define AT91C_SHDWC_KEY (0xFF << 24) // (SHDWC) Shut down KEY Password
+// -------- SHDWC_SHMR : (SHDWC Offset: 0x4) Shut Down Mode Register --------
+#define AT91C_SHDWC_WKMODE0 (0x3 << 0) // (SHDWC) Wake Up 0 Mode Selection
+#define AT91C_SHDWC_WKMODE0_NONE (0x0) // (SHDWC) None. No detection is performed on the wake up input.
+#define AT91C_SHDWC_WKMODE0_HIGH (0x1) // (SHDWC) Low to High Level.
+#define AT91C_SHDWC_WKMODE0_LOW (0x2) // (SHDWC) High to Low Level.
+#define AT91C_SHDWC_WKMODE0_ANYLEVEL (0x3) // (SHDWC) Any level change.
+#define AT91C_SHDWC_CPTWK0 (0xF << 4) // (SHDWC) Counter On Wake Up 0
+#define AT91C_SHDWC_RTTWKEN (0x1 << 16) // (SHDWC) Real Time Timer Wake Up Enable
+// -------- SHDWC_SHSR : (SHDWC Offset: 0x8) Shut Down Status Register --------
+#define AT91C_SHDWC_WAKEUP0 (0x1 << 0) // (SHDWC) Wake Up 0 Status
+#define AT91C_SHDWC_RTTWK (0x1 << 16) // (SHDWC) Real Time Timer wake Up
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_RTTC {
+ AT91_REG RTTC_RTMR; // Real-time Mode Register
+ AT91_REG RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG RTTC_RTVR; // Real-time Value Register
+ AT91_REG RTTC_RTSR; // Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+#else
+#define RTTC_RTMR (AT91_CAST(AT91_REG *) 0x00000000) // (RTTC_RTMR) Real-time Mode Register
+#define RTTC_RTAR (AT91_CAST(AT91_REG *) 0x00000004) // (RTTC_RTAR) Real-time Alarm Register
+#define RTTC_RTVR (AT91_CAST(AT91_REG *) 0x00000008) // (RTTC_RTVR) Real-time Value Register
+#define RTTC_RTSR (AT91_CAST(AT91_REG *) 0x0000000C) // (RTTC_RTSR) Real-time Status Register
+
+#endif
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
+#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
+#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
+#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
+#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_PITC {
+ AT91_REG PITC_PIMR; // Period Interval Mode Register
+ AT91_REG PITC_PISR; // Period Interval Status Register
+ AT91_REG PITC_PIVR; // Period Interval Value Register
+ AT91_REG PITC_PIIR; // Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+#else
+#define PITC_PIMR (AT91_CAST(AT91_REG *) 0x00000000) // (PITC_PIMR) Period Interval Mode Register
+#define PITC_PISR (AT91_CAST(AT91_REG *) 0x00000004) // (PITC_PISR) Period Interval Status Register
+#define PITC_PIVR (AT91_CAST(AT91_REG *) 0x00000008) // (PITC_PIVR) Period Interval Value Register
+#define PITC_PIIR (AT91_CAST(AT91_REG *) 0x0000000C) // (PITC_PIIR) Period Interval Image Register
+
+#endif
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
+#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
+#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
+#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_WDTC {
+ AT91_REG WDTC_WDCR; // Watchdog Control Register
+ AT91_REG WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG WDTC_WDSR; // Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+#else
+#define WDTC_WDCR (AT91_CAST(AT91_REG *) 0x00000000) // (WDTC_WDCR) Watchdog Control Register
+#define WDTC_WDMR (AT91_CAST(AT91_REG *) 0x00000004) // (WDTC_WDMR) Watchdog Mode Register
+#define WDTC_WDSR (AT91_CAST(AT91_REG *) 0x00000008) // (WDTC_WDSR) Watchdog Status Register
+
+#endif
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
+#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
+#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
+#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR USB Device Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_UDP {
+ AT91_REG UDP_NUM; // Frame Number Register
+ AT91_REG UDP_GLBSTATE; // Global State Register
+ AT91_REG UDP_FADDR; // Function Address Register
+ AT91_REG Reserved0[1]; //
+ AT91_REG UDP_IER; // Interrupt Enable Register
+ AT91_REG UDP_IDR; // Interrupt Disable Register
+ AT91_REG UDP_IMR; // Interrupt Mask Register
+ AT91_REG UDP_ISR; // Interrupt Status Register
+ AT91_REG UDP_ICR; // Interrupt Clear Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG UDP_RSTEP; // Reset Endpoint Register
+ AT91_REG Reserved2[1]; //
+ AT91_REG UDP_CSR[6]; // Endpoint Control and Status Register
+ AT91_REG Reserved3[2]; //
+ AT91_REG UDP_FDR[6]; // Endpoint FIFO Data Register
+ AT91_REG Reserved4[3]; //
+ AT91_REG UDP_TXVC; // Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+#else
+#define UDP_FRM_NUM (AT91_CAST(AT91_REG *) 0x00000000) // (UDP_FRM_NUM) Frame Number Register
+#define UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0x00000004) // (UDP_GLBSTATE) Global State Register
+#define UDP_FADDR (AT91_CAST(AT91_REG *) 0x00000008) // (UDP_FADDR) Function Address Register
+#define UDP_IER (AT91_CAST(AT91_REG *) 0x00000010) // (UDP_IER) Interrupt Enable Register
+#define UDP_IDR (AT91_CAST(AT91_REG *) 0x00000014) // (UDP_IDR) Interrupt Disable Register
+#define UDP_IMR (AT91_CAST(AT91_REG *) 0x00000018) // (UDP_IMR) Interrupt Mask Register
+#define UDP_ISR (AT91_CAST(AT91_REG *) 0x0000001C) // (UDP_ISR) Interrupt Status Register
+#define UDP_ICR (AT91_CAST(AT91_REG *) 0x00000020) // (UDP_ICR) Interrupt Clear Register
+#define UDP_RSTEP (AT91_CAST(AT91_REG *) 0x00000028) // (UDP_RSTEP) Reset Endpoint Register
+#define UDP_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (UDP_CSR) Endpoint Control and Status Register
+#define UDP_FDR (AT91_CAST(AT91_REG *) 0x00000050) // (UDP_FDR) Endpoint FIFO Data Register
+#define UDP_TXVC (AT91_CAST(AT91_REG *) 0x00000074) // (UDP_TXVC) Transceiver Control Register
+
+#endif
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
+#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
+#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured
+// The following are not supported by CAP7
+#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
+#define AT91C_UDP_FADD (0x7F << 0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
+#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4 (0x1 << 4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5 (0x1 << 5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
+#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
+#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4 (0x1 << 4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5 (0x1 << 5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
+#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_STALLSENT (0x1 << 3) // (UDP) Stall sent (Control, bulk, interrupt endpoints)
+#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type
+#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control
+#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT
+#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT
+#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT
+#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN
+#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN
+#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
+#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP)
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TC {
+ AT91_REG TC_CCR; // Channel Control Register
+ AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode)
+ AT91_REG Reserved0[2]; //
+ AT91_REG TC_CV; // Counter Value
+ AT91_REG TC_RA; // Register A
+ AT91_REG TC_RB; // Register B
+ AT91_REG TC_RC; // Register C
+ AT91_REG TC_SR; // Status Register
+ AT91_REG TC_IER; // Interrupt Enable Register
+ AT91_REG TC_IDR; // Interrupt Disable Register
+ AT91_REG TC_IMR; // Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+#else
+#define TC_CCR (AT91_CAST(AT91_REG *) 0x00000000) // (TC_CCR) Channel Control Register
+#define TC_CMR (AT91_CAST(AT91_REG *) 0x00000004) // (TC_CMR) Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV (AT91_CAST(AT91_REG *) 0x00000010) // (TC_CV) Counter Value
+#define TC_RA (AT91_CAST(AT91_REG *) 0x00000014) // (TC_RA) Register A
+#define TC_RB (AT91_CAST(AT91_REG *) 0x00000018) // (TC_RB) Register B
+#define TC_RC (AT91_CAST(AT91_REG *) 0x0000001C) // (TC_RC) Register C
+#define TC_SR (AT91_CAST(AT91_REG *) 0x00000020) // (TC_SR) Status Register
+#define TC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (TC_IER) Interrupt Enable Register
+#define TC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (TC_IDR) Interrupt Disable Register
+#define TC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (TC_IMR) Interrupt Mask Register
+
+#endif
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
+#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
+#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection
+#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0
+#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1
+#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert
+#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection
+#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal
+#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock
+#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection
+#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection
+#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None
+#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge
+#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge
+#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection
+#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection
+#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE (0x1 << 15) // (TC)
+#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none
+#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set
+#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear
+#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection
+#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None
+#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none
+#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set
+#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear
+#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection
+#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None
+#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA
+#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none
+#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set
+#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear
+#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none
+#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set
+#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear
+#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none
+#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set
+#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear
+#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none
+#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set
+#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear
+#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB
+#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none
+#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set
+#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear
+#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none
+#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set
+#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear
+#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
+#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun
+#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare
+#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare
+#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare
+#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading
+#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading
+#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Timer Counter Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_TCB {
+ AT91S_TC TCB_TC0; // TC Channel 0
+ AT91_REG Reserved0[4]; //
+ AT91S_TC TCB_TC1; // TC Channel 1
+ AT91_REG Reserved1[4]; //
+ AT91S_TC TCB_TC2; // TC Channel 2
+ AT91_REG Reserved2[4]; //
+ AT91_REG TCB_BCR; // TC Block Control Register
+ AT91_REG TCB_BMR; // TC Block Mode Register
+ AT91_REG Reserved3[9]; //
+ AT91_REG TCB_ADDRSIZE; // TC ADDRSIZE REGISTER
+ AT91_REG TCB_IPNAME1; // TC IPNAME1 REGISTER
+ AT91_REG TCB_IPNAME2; // TC IPNAME2 REGISTER
+ AT91_REG TCB_FEATURES; // TC FEATURES REGISTER
+ AT91_REG TCB_VER; // Version Register
+} AT91S_TCB, *AT91PS_TCB;
+#else
+#define TCB_BCR (AT91_CAST(AT91_REG *) 0x000000C0) // (TCB_BCR) TC Block Control Register
+#define TCB_BMR (AT91_CAST(AT91_REG *) 0x000000C4) // (TCB_BMR) TC Block Mode Register
+#define TC_ADDRSIZE (AT91_CAST(AT91_REG *) 0x000000EC) // (TC_ADDRSIZE) TC ADDRSIZE REGISTER
+#define TC_IPNAME1 (AT91_CAST(AT91_REG *) 0x000000F0) // (TC_IPNAME1) TC IPNAME1 REGISTER
+#define TC_IPNAME2 (AT91_CAST(AT91_REG *) 0x000000F4) // (TC_IPNAME2) TC IPNAME2 REGISTER
+#define TC_FEATURES (AT91_CAST(AT91_REG *) 0x000000F8) // (TC_FEATURES) TC FEATURES REGISTER
+#define TC_VER (AT91_CAST(AT91_REG *) 0x000000FC) // (TC_VER) Version Register
+
+#endif
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
+#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
+#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection
+#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0
+#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0
+#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection
+#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1
+#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1
+#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection
+#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2
+#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2
+#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Usart
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_USART {
+ AT91_REG US_CR; // Control Register
+ AT91_REG US_MR; // Mode Register
+ AT91_REG US_IER; // Interrupt Enable Register
+ AT91_REG US_IDR; // Interrupt Disable Register
+ AT91_REG US_IMR; // Interrupt Mask Register
+ AT91_REG US_CSR; // Channel Status Register
+ AT91_REG US_RHR; // Receiver Holding Register
+ AT91_REG US_THR; // Transmitter Holding Register
+ AT91_REG US_BRGR; // Baud Rate Generator Register
+ AT91_REG US_RTOR; // Receiver Time-out Register
+ AT91_REG US_TTGR; // Transmitter Time-guard Register
+ AT91_REG Reserved0[5]; //
+ AT91_REG US_FIDI; // FI_DI_Ratio Register
+ AT91_REG US_NER; // Nb Errors Register
+ AT91_REG Reserved1[1]; //
+ AT91_REG US_IF; // IRDA_FILTER Register
+ AT91_REG US_MAN; // Manchester Encoder Decoder Register
+ AT91_REG Reserved2[43]; //
+ AT91_REG US_RPR; // Receive Pointer Register
+ AT91_REG US_RCR; // Receive Counter Register
+ AT91_REG US_TPR; // Transmit Pointer Register
+ AT91_REG US_TCR; // Transmit Counter Register
+ AT91_REG US_RNPR; // Receive Next Pointer Register
+ AT91_REG US_RNCR; // Receive Next Counter Register
+ AT91_REG US_TNPR; // Transmit Next Pointer Register
+ AT91_REG US_TNCR; // Transmit Next Counter Register
+ AT91_REG US_PTCR; // PDC Transfer Control Register
+ AT91_REG US_PTSR; // PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+#else
+#define US_CR (AT91_CAST(AT91_REG *) 0x00000000) // (US_CR) Control Register
+#define US_MR (AT91_CAST(AT91_REG *) 0x00000004) // (US_MR) Mode Register
+#define US_IER (AT91_CAST(AT91_REG *) 0x00000008) // (US_IER) Interrupt Enable Register
+#define US_IDR (AT91_CAST(AT91_REG *) 0x0000000C) // (US_IDR) Interrupt Disable Register
+#define US_IMR (AT91_CAST(AT91_REG *) 0x00000010) // (US_IMR) Interrupt Mask Register
+#define US_CSR (AT91_CAST(AT91_REG *) 0x00000014) // (US_CSR) Channel Status Register
+#define US_RHR (AT91_CAST(AT91_REG *) 0x00000018) // (US_RHR) Receiver Holding Register
+#define US_THR (AT91_CAST(AT91_REG *) 0x0000001C) // (US_THR) Transmitter Holding Register
+#define US_BRGR (AT91_CAST(AT91_REG *) 0x00000020) // (US_BRGR) Baud Rate Generator Register
+#define US_RTOR (AT91_CAST(AT91_REG *) 0x00000024) // (US_RTOR) Receiver Time-out Register
+#define US_TTGR (AT91_CAST(AT91_REG *) 0x00000028) // (US_TTGR) Transmitter Time-guard Register
+#define US_FIDI (AT91_CAST(AT91_REG *) 0x00000040) // (US_FIDI) FI_DI_Ratio Register
+#define US_NER (AT91_CAST(AT91_REG *) 0x00000044) // (US_NER) Nb Errors Register
+#define US_IF (AT91_CAST(AT91_REG *) 0x0000004C) // (US_IF) IRDA_FILTER Register
+#define US_MAN (AT91_CAST(AT91_REG *) 0x00000050) // (US_MAN) Manchester Encoder Decoder Register
+
+#endif
+// -------- US_CR : (USART Offset: 0x0) Control Register --------
+#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break
+#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Mode Register --------
+#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode
+#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal
+#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485
+#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking
+#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem
+#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0
+#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1
+#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA
+#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock
+#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1
+#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM)
+#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK)
+#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits
+#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits
+#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits
+#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits
+#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit
+#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_VAR_SYNC (0x1 << 22) // (USART) Variable synchronization of command/data sync Start Frame Delimiter
+#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter
+#define AT91C_US_MANMODE (0x1 << 29) // (USART) Manchester Encoder/Decoder Enable
+#define AT91C_US_MODSYNC (0x1 << 30) // (USART) Manchester Synchronization mode
+#define AT91C_US_ONEBIT (0x1 << 31) // (USART) Start Frame Delimiter selector
+// -------- US_IER : (USART Offset: 0x8) Interrupt Enable Register --------
+#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag
+#define AT91C_US_MANE (0x1 << 20) // (USART) Manchester Error Interrupt
+// -------- US_IDR : (USART Offset: 0xc) Interrupt Disable Register --------
+// -------- US_IMR : (USART Offset: 0x10) Interrupt Mask Register --------
+// -------- US_CSR : (USART Offset: 0x14) Channel Status Register --------
+#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input
+#define AT91C_US_MANERR (0x1 << 24) // (USART) Manchester Error
+// -------- US_MAN : (USART Offset: 0x50) Manchester Encoder Decoder Register --------
+#define AT91C_US_TX_PL (0xF << 0) // (USART) Transmitter Preamble Length
+#define AT91C_US_TX_PP (0x3 << 8) // (USART) Transmitter Preamble Pattern
+#define AT91C_US_TX_PP_ALL_ONE (0x0 << 8) // (USART) ALL_ONE
+#define AT91C_US_TX_PP_ALL_ZERO (0x1 << 8) // (USART) ALL_ZERO
+#define AT91C_US_TX_PP_ZERO_ONE (0x2 << 8) // (USART) ZERO_ONE
+#define AT91C_US_TX_PP_ONE_ZERO (0x3 << 8) // (USART) ONE_ZERO
+#define AT91C_US_TX_MPOL (0x1 << 12) // (USART) Transmitter Manchester Polarity
+#define AT91C_US_RX_PL (0xF << 16) // (USART) Receiver Preamble Length
+#define AT91C_US_RX_PP (0x3 << 24) // (USART) Receiver Preamble Pattern detected
+#define AT91C_US_RX_PP_ALL_ONE (0x0 << 24) // (USART) ALL_ONE
+#define AT91C_US_RX_PP_ALL_ZERO (0x1 << 24) // (USART) ALL_ZERO
+#define AT91C_US_RX_PP_ZERO_ONE (0x2 << 24) // (USART) ZERO_ONE
+#define AT91C_US_RX_PP_ONE_ZERO (0x3 << 24) // (USART) ONE_ZERO
+#define AT91C_US_RX_MPOL (0x1 << 28) // (USART) Receiver Manchester Polarity
+#define AT91C_US_DRIFT (0x1 << 30) // (USART) Drift compensation
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Serial Parallel Interface
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SPI {
+ AT91_REG SPI_CR; // Control Register
+ AT91_REG SPI_MR; // Mode Register
+ AT91_REG SPI_RDR; // Receive Data Register
+ AT91_REG SPI_TDR; // Transmit Data Register
+ AT91_REG SPI_SR; // Status Register
+ AT91_REG SPI_IER; // Interrupt Enable Register
+ AT91_REG SPI_IDR; // Interrupt Disable Register
+ AT91_REG SPI_IMR; // Interrupt Mask Register
+ AT91_REG Reserved0[4]; //
+ AT91_REG SPI_CSR[4]; // Chip Select Register
+ AT91_REG Reserved1[48]; //
+ AT91_REG SPI_RPR; // Receive Pointer Register
+ AT91_REG SPI_RCR; // Receive Counter Register
+ AT91_REG SPI_TPR; // Transmit Pointer Register
+ AT91_REG SPI_TCR; // Transmit Counter Register
+ AT91_REG SPI_RNPR; // Receive Next Pointer Register
+ AT91_REG SPI_RNCR; // Receive Next Counter Register
+ AT91_REG SPI_TNPR; // Transmit Next Pointer Register
+ AT91_REG SPI_TNCR; // Transmit Next Counter Register
+ AT91_REG SPI_PTCR; // PDC Transfer Control Register
+ AT91_REG SPI_PTSR; // PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+#else
+#define SPI_CR (AT91_CAST(AT91_REG *) 0x00000000) // (SPI_CR) Control Register
+#define SPI_MR (AT91_CAST(AT91_REG *) 0x00000004) // (SPI_MR) Mode Register
+#define SPI_RDR (AT91_CAST(AT91_REG *) 0x00000008) // (SPI_RDR) Receive Data Register
+#define SPI_TDR (AT91_CAST(AT91_REG *) 0x0000000C) // (SPI_TDR) Transmit Data Register
+#define SPI_SR (AT91_CAST(AT91_REG *) 0x00000010) // (SPI_SR) Status Register
+#define SPI_IER (AT91_CAST(AT91_REG *) 0x00000014) // (SPI_IER) Interrupt Enable Register
+#define SPI_IDR (AT91_CAST(AT91_REG *) 0x00000018) // (SPI_IDR) Interrupt Disable Register
+#define SPI_IMR (AT91_CAST(AT91_REG *) 0x0000001C) // (SPI_IMR) Interrupt Mask Register
+#define SPI_CSR (AT91_CAST(AT91_REG *) 0x00000030) // (SPI_CSR) Chip Select Register
+
+#endif
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
+#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
+#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select
+#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select
+#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
+#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
+#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
+#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
+#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer
+#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer
+#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer
+#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer
+#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer
+#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer
+#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer
+#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer
+#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer
+#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR Analog to Digital Convertor
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_ADC {
+ AT91_REG ADC_CR; // ADC Control Register
+ AT91_REG ADC_MR; // ADC Mode Register
+ AT91_REG Reserved0[2]; //
+ AT91_REG ADC_CHER; // ADC Channel Enable Register
+ AT91_REG ADC_CHDR; // ADC Channel Disable Register
+ AT91_REG ADC_CHSR; // ADC Channel Status Register
+ AT91_REG ADC_SR; // ADC Status Register
+ AT91_REG ADC_LCDR; // ADC Last Converted Data Register
+ AT91_REG ADC_IER; // ADC Interrupt Enable Register
+ AT91_REG ADC_IDR; // ADC Interrupt Disable Register
+ AT91_REG ADC_IMR; // ADC Interrupt Mask Register
+ AT91_REG ADC_CDR0; // ADC Channel Data Register 0
+ AT91_REG ADC_CDR1; // ADC Channel Data Register 1
+ AT91_REG ADC_CDR2; // ADC Channel Data Register 2
+ AT91_REG ADC_CDR3; // ADC Channel Data Register 3
+ AT91_REG ADC_CDR4; // ADC Channel Data Register 4
+ AT91_REG ADC_CDR5; // ADC Channel Data Register 5
+ AT91_REG ADC_CDR6; // ADC Channel Data Register 6
+ AT91_REG ADC_CDR7; // ADC Channel Data Register 7
+ AT91_REG Reserved1[44]; //
+ AT91_REG ADC_RPR; // Receive Pointer Register
+ AT91_REG ADC_RCR; // Receive Counter Register
+ AT91_REG ADC_TPR; // Transmit Pointer Register
+ AT91_REG ADC_TCR; // Transmit Counter Register
+ AT91_REG ADC_RNPR; // Receive Next Pointer Register
+ AT91_REG ADC_RNCR; // Receive Next Counter Register
+ AT91_REG ADC_TNPR; // Transmit Next Pointer Register
+ AT91_REG ADC_TNCR; // Transmit Next Counter Register
+ AT91_REG ADC_PTCR; // PDC Transfer Control Register
+ AT91_REG ADC_PTSR; // PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+#else
+#define ADC_CR (AT91_CAST(AT91_REG *) 0x00000000) // (ADC_CR) ADC Control Register
+#define ADC_MR (AT91_CAST(AT91_REG *) 0x00000004) // (ADC_MR) ADC Mode Register
+#define ADC_CHER (AT91_CAST(AT91_REG *) 0x00000010) // (ADC_CHER) ADC Channel Enable Register
+#define ADC_CHDR (AT91_CAST(AT91_REG *) 0x00000014) // (ADC_CHDR) ADC Channel Disable Register
+#define ADC_CHSR (AT91_CAST(AT91_REG *) 0x00000018) // (ADC_CHSR) ADC Channel Status Register
+#define ADC_SR (AT91_CAST(AT91_REG *) 0x0000001C) // (ADC_SR) ADC Status Register
+#define ADC_LCDR (AT91_CAST(AT91_REG *) 0x00000020) // (ADC_LCDR) ADC Last Converted Data Register
+#define ADC_IER (AT91_CAST(AT91_REG *) 0x00000024) // (ADC_IER) ADC Interrupt Enable Register
+#define ADC_IDR (AT91_CAST(AT91_REG *) 0x00000028) // (ADC_IDR) ADC Interrupt Disable Register
+#define ADC_IMR (AT91_CAST(AT91_REG *) 0x0000002C) // (ADC_IMR) ADC Interrupt Mask Register
+#define ADC_CDR0 (AT91_CAST(AT91_REG *) 0x00000030) // (ADC_CDR0) ADC Channel Data Register 0
+#define ADC_CDR1 (AT91_CAST(AT91_REG *) 0x00000034) // (ADC_CDR1) ADC Channel Data Register 1
+#define ADC_CDR2 (AT91_CAST(AT91_REG *) 0x00000038) // (ADC_CDR2) ADC Channel Data Register 2
+#define ADC_CDR3 (AT91_CAST(AT91_REG *) 0x0000003C) // (ADC_CDR3) ADC Channel Data Register 3
+#define ADC_CDR4 (AT91_CAST(AT91_REG *) 0x00000040) // (ADC_CDR4) ADC Channel Data Register 4
+#define ADC_CDR5 (AT91_CAST(AT91_REG *) 0x00000044) // (ADC_CDR5) ADC Channel Data Register 5
+#define ADC_CDR6 (AT91_CAST(AT91_REG *) 0x00000048) // (ADC_CDR6) ADC Channel Data Register 6
+#define ADC_CDR7 (AT91_CAST(AT91_REG *) 0x0000004C) // (ADC_CDR7) ADC Channel Data Register 7
+
+#endif
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
+#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset
+#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
+#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable
+#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection
+#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution.
+#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution
+#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode
+#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time
+// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
+#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0
+#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1
+#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2
+#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3
+#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4
+#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5
+#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6
+#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7
+// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
+// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
+#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
+#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
+#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
+
+// *****************************************************************************
+// SOFTWARE API DEFINITION FOR System Peripherals
+// *****************************************************************************
+#ifndef __ASSEMBLY__
+typedef struct _AT91S_SYS {
+ AT91_REG SYS_SDRAMC_MR; // SDRAM Controller Mode Register
+ AT91_REG SYS_SDRAMC_TR; // SDRAM Controller Refresh Timer Register
+ AT91_REG SYS_SDRAMC_CR; // SDRAM Controller Configuration Register
+ AT91_REG SYS_SDRAMC_HSR; // SDRAM Controller High Speed Register
+ AT91_REG SYS_SDRAMC_LPR; // SDRAM Controller Low Power Register
+ AT91_REG SYS_SDRAMC_IER; // SDRAM Controller Interrupt Enable Register
+ AT91_REG SYS_SDRAMC_IDR; // SDRAM Controller Interrupt Disable Register
+ AT91_REG SYS_SDRAMC_IMR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SYS_SDRAMC_ISR; // SDRAM Controller Interrupt Mask Register
+ AT91_REG SYS_SDRAMC_MDR; // SDRAM Memory Device Register
+ AT91_REG Reserved0[118]; //
+ AT91_REG SYS_SMC_SETUP0; // Setup Register for CS 0
+ AT91_REG SYS_SMC_PULSE0; // Pulse Register for CS 0
+ AT91_REG SYS_SMC_CYCLE0; // Cycle Register for CS 0
+ AT91_REG SYS_SMC_CTRL0; // Control Register for CS 0
+ AT91_REG SYS_SMC_SETUP1; // Setup Register for CS 1
+ AT91_REG SYS_SMC_PULSE1; // Pulse Register for CS 1
+ AT91_REG SYS_SMC_CYCLE1; // Cycle Register for CS 1
+ AT91_REG SYS_SMC_CTRL1; // Control Register for CS 1
+ AT91_REG SYS_SMC_SETUP2; // Setup Register for CS 2
+ AT91_REG SYS_SMC_PULSE2; // Pulse Register for CS 2
+ AT91_REG SYS_SMC_CYCLE2; // Cycle Register for CS 2
+ AT91_REG SYS_SMC_CTRL2; // Control Register for CS 2
+ AT91_REG SYS_SMC_SETUP3; // Setup Register for CS 3
+ AT91_REG SYS_SMC_PULSE3; // Pulse Register for CS 3
+ AT91_REG SYS_SMC_CYCLE3; // Cycle Register for CS 3
+ AT91_REG SYS_SMC_CTRL3; // Control Register for CS 3
+ AT91_REG SYS_SMC_SETUP4; // Setup Register for CS 4
+ AT91_REG SYS_SMC_PULSE4; // Pulse Register for CS 4
+ AT91_REG SYS_SMC_CYCLE4; // Cycle Register for CS 4
+ AT91_REG SYS_SMC_CTRL4; // Control Register for CS 4
+ AT91_REG SYS_SMC_SETUP5; // Setup Register for CS 5
+ AT91_REG SYS_SMC_PULSE5; // Pulse Register for CS 5
+ AT91_REG SYS_SMC_CYCLE5; // Cycle Register for CS 5
+ AT91_REG SYS_SMC_CTRL5; // Control Register for CS 5
+ AT91_REG SYS_SMC_SETUP6; // Setup Register for CS 6
+ AT91_REG SYS_SMC_PULSE6; // Pulse Register for CS 6
+ AT91_REG SYS_SMC_CYCLE6; // Cycle Register for CS 6
+ AT91_REG SYS_SMC_CTRL6; // Control Register for CS 6
+ AT91_REG SYS_SMC_SETUP7; // Setup Register for CS 7
+ AT91_REG SYS_SMC_PULSE7; // Pulse Register for CS 7
+ AT91_REG SYS_SMC_CYCLE7; // Cycle Register for CS 7
+ AT91_REG SYS_SMC_CTRL7; // Control Register for CS 7
+ AT91_REG Reserved1[96]; //
+ AT91_REG SYS_MATRIX_MCFG[6]; // Master Configuration Register
+ AT91_REG Reserved2[10]; //
+ AT91_REG SYS_MATRIX_SCFG[10]; // Slave Configuration Register
+ AT91_REG Reserved3[6]; //
+ AT91S_MATRIX_PRS SYS_MATRIX_PRS[10]; // Slave Priority Registers
+ AT91_REG Reserved4[12]; //
+ AT91_REG SYS_MATRIX_MRCR; // Master Remp Control Register
+ AT91_REG Reserved5[11]; //
+ AT91_REG SYS_MATRIX_EBICSA; // EBI Chip Select Assignment Register
+ AT91_REG SYS_MATRIX_USBPCR; // USB Pad Pullup Control Register
+ AT91_REG Reserved6[50]; //
+ AT91_REG SYS_AIC_SMR[32]; // Source Mode Register
+ AT91_REG SYS_AIC_SVR[32]; // Source Vector Register
+ AT91_REG SYS_AIC_IVR; // IRQ Vector Register
+ AT91_REG SYS_AIC_FVR; // FIQ Vector Register
+ AT91_REG SYS_AIC_ISR; // Interrupt Status Register
+ AT91_REG SYS_AIC_IPR; // Interrupt Pending Register
+ AT91_REG SYS_AIC_IMR; // Interrupt Mask Register
+ AT91_REG SYS_AIC_CISR; // Core Interrupt Status Register
+ AT91_REG Reserved7[2]; //
+ AT91_REG SYS_AIC_IECR; // Interrupt Enable Command Register
+ AT91_REG SYS_AIC_IDCR; // Interrupt Disable Command Register
+ AT91_REG SYS_AIC_ICCR; // Interrupt Clear Command Register
+ AT91_REG SYS_AIC_ISCR; // Interrupt Set Command Register
+ AT91_REG SYS_AIC_EOICR; // End of Interrupt Command Register
+ AT91_REG SYS_AIC_SPU; // Spurious Vector Register
+ AT91_REG SYS_AIC_DCR; // Debug Control Register (Protect)
+ AT91_REG Reserved8[1]; //
+ AT91_REG SYS_AIC_FFER; // Fast Forcing Enable Register
+ AT91_REG SYS_AIC_FFDR; // Fast Forcing Disable Register
+ AT91_REG SYS_AIC_FFSR; // Fast Forcing Status Register
+ AT91_REG Reserved9[45]; //
+ AT91_REG SYS_DBGU_CR; // Control Register
+ AT91_REG SYS_DBGU_MR; // Mode Register
+ AT91_REG SYS_DBGU_IER; // Interrupt Enable Register
+ AT91_REG SYS_DBGU_IDR; // Interrupt Disable Register
+ AT91_REG SYS_DBGU_IMR; // Interrupt Mask Register
+ AT91_REG SYS_DBGU_CSR; // Channel Status Register
+ AT91_REG SYS_DBGU_RHR; // Receiver Holding Register
+ AT91_REG SYS_DBGU_THR; // Transmitter Holding Register
+ AT91_REG SYS_DBGU_BRGR; // Baud Rate Generator Register
+ AT91_REG Reserved10[7]; //
+ AT91_REG SYS_DBGU_CIDR; // Chip ID Register
+ AT91_REG SYS_DBGU_EXID; // Chip ID Extension Register
+ AT91_REG SYS_DBGU_FNTR; // Force NTRST Register
+ AT91_REG Reserved11[45]; //
+ AT91_REG SYS_DBGU_RPR; // Receive Pointer Register
+ AT91_REG SYS_DBGU_RCR; // Receive Counter Register
+ AT91_REG SYS_DBGU_TPR; // Transmit Pointer Register
+ AT91_REG SYS_DBGU_TCR; // Transmit Counter Register
+ AT91_REG SYS_DBGU_RNPR; // Receive Next Pointer Register
+ AT91_REG SYS_DBGU_RNCR; // Receive Next Counter Register
+ AT91_REG SYS_DBGU_TNPR; // Transmit Next Pointer Register
+ AT91_REG SYS_DBGU_TNCR; // Transmit Next Counter Register
+ AT91_REG SYS_DBGU_PTCR; // PDC Transfer Control Register
+ AT91_REG SYS_DBGU_PTSR; // PDC Transfer Status Register
+ AT91_REG Reserved12[54]; //
+ AT91_REG SYS_PIOA_PER; // PIO Enable Register
+ AT91_REG SYS_PIOA_PDR; // PIO Disable Register
+ AT91_REG SYS_PIOA_PSR; // PIO Status Register
+ AT91_REG Reserved13[1]; //
+ AT91_REG SYS_PIOA_OER; // Output Enable Register
+ AT91_REG SYS_PIOA_ODR; // Output Disable Registerr
+ AT91_REG SYS_PIOA_OSR; // Output Status Register
+ AT91_REG Reserved14[1]; //
+ AT91_REG SYS_PIOA_IFER; // Input Filter Enable Register
+ AT91_REG SYS_PIOA_IFDR; // Input Filter Disable Register
+ AT91_REG SYS_PIOA_IFSR; // Input Filter Status Register
+ AT91_REG Reserved15[1]; //
+ AT91_REG SYS_PIOA_SODR; // Set Output Data Register
+ AT91_REG SYS_PIOA_CODR; // Clear Output Data Register
+ AT91_REG SYS_PIOA_ODSR; // Output Data Status Register
+ AT91_REG SYS_PIOA_PDSR; // Pin Data Status Register
+ AT91_REG SYS_PIOA_IER; // Interrupt Enable Register
+ AT91_REG SYS_PIOA_IDR; // Interrupt Disable Register
+ AT91_REG SYS_PIOA_IMR; // Interrupt Mask Register
+ AT91_REG SYS_PIOA_ISR; // Interrupt Status Register
+ AT91_REG SYS_PIOA_MDER; // Multi-driver Enable Register
+ AT91_REG SYS_PIOA_MDDR; // Multi-driver Disable Register
+ AT91_REG SYS_PIOA_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved16[1]; //
+ AT91_REG SYS_PIOA_PPUDR; // Pull-up Disable Register
+ AT91_REG SYS_PIOA_PPUER; // Pull-up Enable Register
+ AT91_REG SYS_PIOA_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved17[1]; //
+ AT91_REG SYS_PIOA_ASR; // Select A Register
+ AT91_REG SYS_PIOA_BSR; // Select B Register
+ AT91_REG SYS_PIOA_ABSR; // AB Select Status Register
+ AT91_REG Reserved18[9]; //
+ AT91_REG SYS_PIOA_OWER; // Output Write Enable Register
+ AT91_REG SYS_PIOA_OWDR; // Output Write Disable Register
+ AT91_REG SYS_PIOA_OWSR; // Output Write Status Register
+ AT91_REG Reserved19[85]; //
+ AT91_REG SYS_PIOB_PER; // PIO Enable Register
+ AT91_REG SYS_PIOB_PDR; // PIO Disable Register
+ AT91_REG SYS_PIOB_PSR; // PIO Status Register
+ AT91_REG Reserved20[1]; //
+ AT91_REG SYS_PIOB_OER; // Output Enable Register
+ AT91_REG SYS_PIOB_ODR; // Output Disable Registerr
+ AT91_REG SYS_PIOB_OSR; // Output Status Register
+ AT91_REG Reserved21[1]; //
+ AT91_REG SYS_PIOB_IFER; // Input Filter Enable Register
+ AT91_REG SYS_PIOB_IFDR; // Input Filter Disable Register
+ AT91_REG SYS_PIOB_IFSR; // Input Filter Status Register
+ AT91_REG Reserved22[1]; //
+ AT91_REG SYS_PIOB_SODR; // Set Output Data Register
+ AT91_REG SYS_PIOB_CODR; // Clear Output Data Register
+ AT91_REG SYS_PIOB_ODSR; // Output Data Status Register
+ AT91_REG SYS_PIOB_PDSR; // Pin Data Status Register
+ AT91_REG SYS_PIOB_IER; // Interrupt Enable Register
+ AT91_REG SYS_PIOB_IDR; // Interrupt Disable Register
+ AT91_REG SYS_PIOB_IMR; // Interrupt Mask Register
+ AT91_REG SYS_PIOB_ISR; // Interrupt Status Register
+ AT91_REG SYS_PIOB_MDER; // Multi-driver Enable Register
+ AT91_REG SYS_PIOB_MDDR; // Multi-driver Disable Register
+ AT91_REG SYS_PIOB_MDSR; // Multi-driver Status Register
+ AT91_REG Reserved23[1]; //
+ AT91_REG SYS_PIOB_PPUDR; // Pull-up Disable Register
+ AT91_REG SYS_PIOB_PPUER; // Pull-up Enable Register
+ AT91_REG SYS_PIOB_PPUSR; // Pull-up Status Register
+ AT91_REG Reserved24[1]; //
+ AT91_REG SYS_PIOB_ASR; // Select A Register
+ AT91_REG SYS_PIOB_BSR; // Select B Register
+ AT91_REG SYS_PIOB_ABSR; // AB Select Status Register
+ AT91_REG Reserved25[9]; //
+ AT91_REG SYS_PIOB_OWER; // Output Write Enable Register
+ AT91_REG SYS_PIOB_OWDR; // Output Write Disable Register
+ AT91_REG SYS_PIOB_OWSR; // Output Write Status Register
+ AT91_REG Reserved26[341]; //
+ AT91_REG SYS_PMC_SCER; // System Clock Enable Register
+ AT91_REG SYS_PMC_SCDR; // System Clock Disable Register
+ AT91_REG SYS_PMC_SCSR; // System Clock Status Register
+ AT91_REG Reserved27[1]; //
+ AT91_REG SYS_PMC_PCER; // Peripheral Clock Enable Register
+ AT91_REG SYS_PMC_PCDR; // Peripheral Clock Disable Register
+ AT91_REG SYS_PMC_PCSR; // Peripheral Clock Status Register
+ AT91_REG Reserved28[1]; //
+ AT91_REG SYS_PMC_MOR; // Main Oscillator Register
+ AT91_REG SYS_PMC_MCFR; // Main Clock Frequency Register
+ AT91_REG SYS_PMC_PLLAR; // PLL A Register
+ AT91_REG SYS_PMC_PLLBR; // PLL B Register
+ AT91_REG SYS_PMC_MCKR; // Master Clock Register
+ AT91_REG Reserved29[3]; //
+ AT91_REG SYS_PMC_PCKR[8]; // Programmable Clock Register
+ AT91_REG SYS_PMC_IER; // Interrupt Enable Register
+ AT91_REG SYS_PMC_IDR; // Interrupt Disable Register
+ AT91_REG SYS_PMC_SR; // Status Register
+ AT91_REG SYS_PMC_IMR; // Interrupt Mask Register
+ AT91_REG Reserved30[36]; //
+ AT91_REG SYS_RSTC_RCR; // Reset Control Register
+ AT91_REG SYS_RSTC_RSR; // Reset Status Register
+ AT91_REG SYS_RSTC_RMR; // Reset Mode Register
+ AT91_REG Reserved31[1]; //
+ AT91_REG SYS_SHDWC_SHCR; // Shut Down Control Register
+ AT91_REG SYS_SHDWC_SHMR; // Shut Down Mode Register
+ AT91_REG SYS_SHDWC_SHSR; // Shut Down Status Register
+ AT91_REG Reserved32[1]; //
+ AT91_REG SYS_RTTC_RTMR; // Real-time Mode Register
+ AT91_REG SYS_RTTC_RTAR; // Real-time Alarm Register
+ AT91_REG SYS_RTTC_RTVR; // Real-time Value Register
+ AT91_REG SYS_RTTC_RTSR; // Real-time Status Register
+ AT91_REG SYS_PITC_PIMR; // Period Interval Mode Register
+ AT91_REG SYS_PITC_PISR; // Period Interval Status Register
+ AT91_REG SYS_PITC_PIVR; // Period Interval Value Register
+ AT91_REG SYS_PITC_PIIR; // Period Interval Image Register
+ AT91_REG SYS_WDTC_WDCR; // Watchdog Control Register
+ AT91_REG SYS_WDTC_WDMR; // Watchdog Mode Register
+ AT91_REG SYS_WDTC_WDSR; // Watchdog Status Register
+ AT91_REG Reserved33[1]; //
+ AT91_REG SYS_SYS_OSCMR; // 32K Oscillator Mode Register
+ AT91_REG Reserved34[3]; //
+ AT91_REG SYS_GPBR[4]; // General Purpose Register
+} AT91S_SYS, *AT91PS_SYS;
+#else
+#define OSCMR (AT91_CAST(AT91_REG *) 0x00001350) // (OSCMR) 32K Oscillator Mode Register
+#define GPBR (AT91_CAST(AT91_REG *) 0x00001360) // (GPBR) General Purpose Register
+
+#endif
+// -------- OSCMR : (SYS Offset: 0x1350) Slow Clock Selection Register --------
+#define AT91C_OSC32K_RC_EN (0x1 << 0) // (SYS) Enable Internal RC Oscillator
+#define AT91C_OSC32K_XT_EN (0x1 << 1) // (SYS) Enable External Oscillator
+#define AT91C_OSC32K_SEL (0x1 << 3) // (SYS) OSC Selection
+// -------- GPBR : (SYS Offset: 0x1360) GPBR General Purpose Register --------
+#define AT91C_GPBR_GPRV (0x0 << 0) // (SYS) General Purpose Register Value
+
+// *****************************************************************************
+// REGISTER ADDRESS DEFINITION FOR AT91CAP7
+// *****************************************************************************
+// ========== Register definition for SDRAMC peripheral ==========
+#define AT91C_SDRAMC_MR (AT91_CAST(AT91_REG *) 0xFFFFEA00) // (SDRAMC) SDRAM Controller Mode Register
+#define AT91C_SDRAMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFEA1C) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_LPR (AT91_CAST(AT91_REG *) 0xFFFFEA10) // (SDRAMC) SDRAM Controller Low Power Register
+#define AT91C_SDRAMC_ISR (AT91_CAST(AT91_REG *) 0xFFFFEA20) // (SDRAMC) SDRAM Controller Interrupt Mask Register
+#define AT91C_SDRAMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFEA18) // (SDRAMC) SDRAM Controller Interrupt Disable Register
+#define AT91C_SDRAMC_CR (AT91_CAST(AT91_REG *) 0xFFFFEA08) // (SDRAMC) SDRAM Controller Configuration Register
+#define AT91C_SDRAMC_TR (AT91_CAST(AT91_REG *) 0xFFFFEA04) // (SDRAMC) SDRAM Controller Refresh Timer Register
+#define AT91C_SDRAMC_MDR (AT91_CAST(AT91_REG *) 0xFFFFEA24) // (SDRAMC) SDRAM Memory Device Register
+#define AT91C_SDRAMC_HSR (AT91_CAST(AT91_REG *) 0xFFFFEA0C) // (SDRAMC) SDRAM Controller High Speed Register
+#define AT91C_SDRAMC_IER (AT91_CAST(AT91_REG *) 0xFFFFEA14) // (SDRAMC) SDRAM Controller Interrupt Enable Register
+// ========== Register definition for SMC peripheral ==========
+#define AT91C_SMC_CTRL1 (AT91_CAST(AT91_REG *) 0xFFFFEC1C) // (SMC) Control Register for CS 1
+#define AT91C_SMC_PULSE7 (AT91_CAST(AT91_REG *) 0xFFFFEC74) // (SMC) Pulse Register for CS 7
+#define AT91C_SMC_PULSE6 (AT91_CAST(AT91_REG *) 0xFFFFEC64) // (SMC) Pulse Register for CS 6
+#define AT91C_SMC_SETUP4 (AT91_CAST(AT91_REG *) 0xFFFFEC40) // (SMC) Setup Register for CS 4
+#define AT91C_SMC_PULSE3 (AT91_CAST(AT91_REG *) 0xFFFFEC34) // (SMC) Pulse Register for CS 3
+#define AT91C_SMC_CYCLE5 (AT91_CAST(AT91_REG *) 0xFFFFEC58) // (SMC) Cycle Register for CS 5
+#define AT91C_SMC_CYCLE2 (AT91_CAST(AT91_REG *) 0xFFFFEC28) // (SMC) Cycle Register for CS 2
+#define AT91C_SMC_CTRL2 (AT91_CAST(AT91_REG *) 0xFFFFEC2C) // (SMC) Control Register for CS 2
+#define AT91C_SMC_CTRL0 (AT91_CAST(AT91_REG *) 0xFFFFEC0C) // (SMC) Control Register for CS 0
+#define AT91C_SMC_PULSE5 (AT91_CAST(AT91_REG *) 0xFFFFEC54) // (SMC) Pulse Register for CS 5
+#define AT91C_SMC_PULSE1 (AT91_CAST(AT91_REG *) 0xFFFFEC14) // (SMC) Pulse Register for CS 1
+#define AT91C_SMC_PULSE0 (AT91_CAST(AT91_REG *) 0xFFFFEC04) // (SMC) Pulse Register for CS 0
+#define AT91C_SMC_CYCLE7 (AT91_CAST(AT91_REG *) 0xFFFFEC78) // (SMC) Cycle Register for CS 7
+#define AT91C_SMC_CTRL4 (AT91_CAST(AT91_REG *) 0xFFFFEC4C) // (SMC) Control Register for CS 4
+#define AT91C_SMC_CTRL3 (AT91_CAST(AT91_REG *) 0xFFFFEC3C) // (SMC) Control Register for CS 3
+#define AT91C_SMC_SETUP7 (AT91_CAST(AT91_REG *) 0xFFFFEC70) // (SMC) Setup Register for CS 7
+#define AT91C_SMC_CTRL7 (AT91_CAST(AT91_REG *) 0xFFFFEC7C) // (SMC) Control Register for CS 7
+#define AT91C_SMC_SETUP1 (AT91_CAST(AT91_REG *) 0xFFFFEC10) // (SMC) Setup Register for CS 1
+#define AT91C_SMC_CYCLE0 (AT91_CAST(AT91_REG *) 0xFFFFEC08) // (SMC) Cycle Register for CS 0
+#define AT91C_SMC_CTRL5 (AT91_CAST(AT91_REG *) 0xFFFFEC5C) // (SMC) Control Register for CS 5
+#define AT91C_SMC_CYCLE1 (AT91_CAST(AT91_REG *) 0xFFFFEC18) // (SMC) Cycle Register for CS 1
+#define AT91C_SMC_CTRL6 (AT91_CAST(AT91_REG *) 0xFFFFEC6C) // (SMC) Control Register for CS 6
+#define AT91C_SMC_SETUP0 (AT91_CAST(AT91_REG *) 0xFFFFEC00) // (SMC) Setup Register for CS 0
+#define AT91C_SMC_PULSE4 (AT91_CAST(AT91_REG *) 0xFFFFEC44) // (SMC) Pulse Register for CS 4
+#define AT91C_SMC_SETUP5 (AT91_CAST(AT91_REG *) 0xFFFFEC50) // (SMC) Setup Register for CS 5
+#define AT91C_SMC_SETUP2 (AT91_CAST(AT91_REG *) 0xFFFFEC20) // (SMC) Setup Register for CS 2
+#define AT91C_SMC_CYCLE3 (AT91_CAST(AT91_REG *) 0xFFFFEC38) // (SMC) Cycle Register for CS 3
+#define AT91C_SMC_CYCLE6 (AT91_CAST(AT91_REG *) 0xFFFFEC68) // (SMC) Cycle Register for CS 6
+#define AT91C_SMC_SETUP6 (AT91_CAST(AT91_REG *) 0xFFFFEC60) // (SMC) Setup Register for CS 6
+#define AT91C_SMC_CYCLE4 (AT91_CAST(AT91_REG *) 0xFFFFEC48) // (SMC) Cycle Register for CS 4
+#define AT91C_SMC_PULSE2 (AT91_CAST(AT91_REG *) 0xFFFFEC24) // (SMC) Pulse Register for CS 2
+#define AT91C_SMC_SETUP3 (AT91_CAST(AT91_REG *) 0xFFFFEC30) // (SMC) Setup Register for CS 3
+// ========== Register definition for MATRIX_PRS peripheral ==========
+#define AT91C_MATRIX_PRS_PRBS (AT91_CAST(AT91_REG *) 0xFFFFEE84) // (MATRIX_PRS) Slave Priority Registers B for Slave
+#define AT91C_MATRIX_PRS_PRAS (AT91_CAST(AT91_REG *) 0xFFFFEE80) // (MATRIX_PRS) Slave Priority Registers A for Slave
+// ========== Register definition for MATRIX peripheral ==========
+#define AT91C_MATRIX_MCFG (AT91_CAST(AT91_REG *) 0xFFFFEE00) // (MATRIX) Master Configuration Register
+#define AT91C_MATRIX_EBICSA (AT91_CAST(AT91_REG *) 0xFFFFEF30) // (MATRIX) EBI Chip Select Assignment Register
+#define AT91C_MATRIX_USBPCR (AT91_CAST(AT91_REG *) 0xFFFFEF34) // (MATRIX) USB Pad Pullup Control Register
+#define AT91C_MATRIX_MRCR (AT91_CAST(AT91_REG *) 0xFFFFEF00) // (MATRIX) Master Remp Control Register
+#define AT91C_MATRIX_SCFG (AT91_CAST(AT91_REG *) 0xFFFFEE40) // (MATRIX) Slave Configuration Register
+// ========== Register definition for PDC_DBGU peripheral ==========
+#define AT91C_DBGU_TCR (AT91_CAST(AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR (AT91_CAST(AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR (AT91_CAST(AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR (AT91_CAST(AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR (AT91_CAST(AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR (AT91_CAST(AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR (AT91_CAST(AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR (AT91_CAST(AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR (AT91_CAST(AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR (AT91_CAST(AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ==========
+#define AT91C_DBGU_EXID (AT91_CAST(AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR (AT91_CAST(AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR (AT91_CAST(AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR (AT91_CAST(AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR (AT91_CAST(AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR (AT91_CAST(AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR (AT91_CAST(AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR (AT91_CAST(AT91_REG *) 0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR (AT91_CAST(AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR (AT91_CAST(AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR (AT91_CAST(AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER (AT91_CAST(AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for AIC peripheral ==========
+#define AT91C_AIC_IVR (AT91_CAST(AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR (AT91_CAST(AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR (AT91_CAST(AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR (AT91_CAST(AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR (AT91_CAST(AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR (AT91_CAST(AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR (AT91_CAST(AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR (AT91_CAST(AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR (AT91_CAST(AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR (AT91_CAST(AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR (AT91_CAST(AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER (AT91_CAST(AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR (AT91_CAST(AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR (AT91_CAST(AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR (AT91_CAST(AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR (AT91_CAST(AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR (AT91_CAST(AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU (AT91_CAST(AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PIOA peripheral ==========
+#define AT91C_PIOA_ODR (AT91_CAST(AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR (AT91_CAST(AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR (AT91_CAST(AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER (AT91_CAST(AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR (AT91_CAST(AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER (AT91_CAST(AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR (AT91_CAST(AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR (AT91_CAST(AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER (AT91_CAST(AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER (AT91_CAST(AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR (AT91_CAST(AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR (AT91_CAST(AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR (AT91_CAST(AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER (AT91_CAST(AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR (AT91_CAST(AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER (AT91_CAST(AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR (AT91_CAST(AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ==========
+#define AT91C_PIOB_OWDR (AT91_CAST(AT91_REG *) 0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER (AT91_CAST(AT91_REG *) 0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR (AT91_CAST(AT91_REG *) 0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR (AT91_CAST(AT91_REG *) 0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR (AT91_CAST(AT91_REG *) 0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR (AT91_CAST(AT91_REG *) 0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR (AT91_CAST(AT91_REG *) 0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER (AT91_CAST(AT91_REG *) 0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR (AT91_CAST(AT91_REG *) 0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER (AT91_CAST(AT91_REG *) 0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR (AT91_CAST(AT91_REG *) 0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR (AT91_CAST(AT91_REG *) 0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR (AT91_CAST(AT91_REG *) 0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR (AT91_CAST(AT91_REG *) 0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR (AT91_CAST(AT91_REG *) 0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR (AT91_CAST(AT91_REG *) 0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR (AT91_CAST(AT91_REG *) 0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR (AT91_CAST(AT91_REG *) 0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER (AT91_CAST(AT91_REG *) 0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR (AT91_CAST(AT91_REG *) 0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR (AT91_CAST(AT91_REG *) 0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR (AT91_CAST(AT91_REG *) 0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR (AT91_CAST(AT91_REG *) 0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR (AT91_CAST(AT91_REG *) 0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER (AT91_CAST(AT91_REG *) 0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR (AT91_CAST(AT91_REG *) 0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR (AT91_CAST(AT91_REG *) 0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER (AT91_CAST(AT91_REG *) 0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER (AT91_CAST(AT91_REG *) 0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ==========
+#define AT91C_CKGR_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL B Register
+#define AT91C_CKGR_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register
+#define AT91C_CKGR_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (CKGR) PLL A Register
+// ========== Register definition for PMC peripheral ==========
+#define AT91C_PMC_PCER (AT91_CAST(AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR (AT91_CAST(AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR (AT91_CAST(AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_PLLAR (AT91_CAST(AT91_REG *) 0xFFFFFC28) // (PMC) PLL A Register
+#define AT91C_PMC_PCDR (AT91_CAST(AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR (AT91_CAST(AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_MCFR (AT91_CAST(AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register
+#define AT91C_PMC_IMR (AT91_CAST(AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER (AT91_CAST(AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MOR (AT91_CAST(AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_IDR (AT91_CAST(AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PLLBR (AT91_CAST(AT91_REG *) 0xFFFFFC2C) // (PMC) PLL B Register
+#define AT91C_PMC_SCDR (AT91_CAST(AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCSR (AT91_CAST(AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_SCER (AT91_CAST(AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_SR (AT91_CAST(AT91_REG *) 0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ==========
+#define AT91C_RSTC_RCR (AT91_CAST(AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR (AT91_CAST(AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR (AT91_CAST(AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for SHDWC peripheral ==========
+#define AT91C_SHDWC_SHSR (AT91_CAST(AT91_REG *) 0xFFFFFD18) // (SHDWC) Shut Down Status Register
+#define AT91C_SHDWC_SHMR (AT91_CAST(AT91_REG *) 0xFFFFFD14) // (SHDWC) Shut Down Mode Register
+#define AT91C_SHDWC_SHCR (AT91_CAST(AT91_REG *) 0xFFFFFD10) // (SHDWC) Shut Down Control Register
+// ========== Register definition for RTTC peripheral ==========
+#define AT91C_RTTC_RTSR (AT91_CAST(AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR (AT91_CAST(AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR (AT91_CAST(AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR (AT91_CAST(AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ==========
+#define AT91C_PITC_PIVR (AT91_CAST(AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR (AT91_CAST(AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR (AT91_CAST(AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR (AT91_CAST(AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ==========
+#define AT91C_WDTC_WDCR (AT91_CAST(AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR (AT91_CAST(AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR (AT91_CAST(AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for UDP peripheral ==========
+#define AT91C_UDP_GLBSTATE (AT91_CAST(AT91_REG *) 0xFFFA4004) // (UDP) Global State Register
+#define AT91C_UDP_FDR (AT91_CAST(AT91_REG *) 0xFFFA4050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_RSTEP (AT91_CAST(AT91_REG *) 0xFFFA4028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_FADDR (AT91_CAST(AT91_REG *) 0xFFFA4008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM (AT91_CAST(AT91_REG *) 0xFFFA4000) // (UDP) Frame Number Register
+#define AT91C_UDP_IDR (AT91_CAST(AT91_REG *) 0xFFFA4014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_IMR (AT91_CAST(AT91_REG *) 0xFFFA4018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_CSR (AT91_CAST(AT91_REG *) 0xFFFA4030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IER (AT91_CAST(AT91_REG *) 0xFFFA4010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_ICR (AT91_CAST(AT91_REG *) 0xFFFA4020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_TXVC (AT91_CAST(AT91_REG *) 0xFFFA4074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_ISR (AT91_CAST(AT91_REG *) 0xFFFA401C) // (UDP) Interrupt Status Register
+// ========== Register definition for TC0 peripheral ==========
+#define AT91C_TC0_SR (AT91_CAST(AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC (AT91_CAST(AT91_REG *) 0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB (AT91_CAST(AT91_REG *) 0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR (AT91_CAST(AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR (AT91_CAST(AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER (AT91_CAST(AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA (AT91_CAST(AT91_REG *) 0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR (AT91_CAST(AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV (AT91_CAST(AT91_REG *) 0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR (AT91_CAST(AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ==========
+#define AT91C_TC1_RB (AT91_CAST(AT91_REG *) 0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR (AT91_CAST(AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER (AT91_CAST(AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR (AT91_CAST(AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR (AT91_CAST(AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR (AT91_CAST(AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA (AT91_CAST(AT91_REG *) 0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC (AT91_CAST(AT91_REG *) 0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR (AT91_CAST(AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV (AT91_CAST(AT91_REG *) 0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ==========
+#define AT91C_TC2_CMR (AT91_CAST(AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR (AT91_CAST(AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV (AT91_CAST(AT91_REG *) 0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA (AT91_CAST(AT91_REG *) 0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB (AT91_CAST(AT91_REG *) 0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR (AT91_CAST(AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR (AT91_CAST(AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC (AT91_CAST(AT91_REG *) 0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER (AT91_CAST(AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR (AT91_CAST(AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ==========
+#define AT91C_TCB_ADDRSIZE (AT91_CAST(AT91_REG *) 0xFFFA00EC) // (TCB) TC ADDRSIZE REGISTER
+#define AT91C_TCB_BMR (AT91_CAST(AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_VER (AT91_CAST(AT91_REG *) 0xFFFA00FC) // (TCB) Version Register
+#define AT91C_TCB_FEATURES (AT91_CAST(AT91_REG *) 0xFFFA00F8) // (TCB) TC FEATURES REGISTER
+#define AT91C_TCB_IPNAME1 (AT91_CAST(AT91_REG *) 0xFFFA00F0) // (TCB) TC IPNAME1 REGISTER
+#define AT91C_TCB_BCR (AT91_CAST(AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register
+#define AT91C_TCB_IPNAME2 (AT91_CAST(AT91_REG *) 0xFFFA00F4) // (TCB) TC IPNAME2 REGISTER
+// ========== Register definition for PDC_US0 peripheral ==========
+#define AT91C_US0_TCR (AT91_CAST(AT91_REG *) 0xFFFB010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR (AT91_CAST(AT91_REG *) 0xFFFB0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_RNCR (AT91_CAST(AT91_REG *) 0xFFFB0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_PTSR (AT91_CAST(AT91_REG *) 0xFFFB0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR (AT91_CAST(AT91_REG *) 0xFFFB011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNPR (AT91_CAST(AT91_REG *) 0xFFFB0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_RCR (AT91_CAST(AT91_REG *) 0xFFFB0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_TPR (AT91_CAST(AT91_REG *) 0xFFFB0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_TNPR (AT91_CAST(AT91_REG *) 0xFFFB0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RPR (AT91_CAST(AT91_REG *) 0xFFFB0100) // (PDC_US0) Receive Pointer Register
+// ========== Register definition for US0 peripheral ==========
+#define AT91C_US0_RHR (AT91_CAST(AT91_REG *) 0xFFFB0018) // (US0) Receiver Holding Register
+#define AT91C_US0_NER (AT91_CAST(AT91_REG *) 0xFFFB0044) // (US0) Nb Errors Register
+#define AT91C_US0_IER (AT91_CAST(AT91_REG *) 0xFFFB0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_CR (AT91_CAST(AT91_REG *) 0xFFFB0000) // (US0) Control Register
+#define AT91C_US0_MAN (AT91_CAST(AT91_REG *) 0xFFFB0050) // (US0) Manchester Encoder Decoder Register
+#define AT91C_US0_THR (AT91_CAST(AT91_REG *) 0xFFFB001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_CSR (AT91_CAST(AT91_REG *) 0xFFFB0014) // (US0) Channel Status Register
+#define AT91C_US0_BRGR (AT91_CAST(AT91_REG *) 0xFFFB0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RTOR (AT91_CAST(AT91_REG *) 0xFFFB0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_TTGR (AT91_CAST(AT91_REG *) 0xFFFB0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_IDR (AT91_CAST(AT91_REG *) 0xFFFB000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_MR (AT91_CAST(AT91_REG *) 0xFFFB0004) // (US0) Mode Register
+#define AT91C_US0_IF (AT91_CAST(AT91_REG *) 0xFFFB004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_FIDI (AT91_CAST(AT91_REG *) 0xFFFB0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_IMR (AT91_CAST(AT91_REG *) 0xFFFB0010) // (US0) Interrupt Mask Register
+// ========== Register definition for PDC_US1 peripheral ==========
+#define AT91C_US1_PTCR (AT91_CAST(AT91_REG *) 0xFFFB4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_RCR (AT91_CAST(AT91_REG *) 0xFFFB4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RPR (AT91_CAST(AT91_REG *) 0xFFFB4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_PTSR (AT91_CAST(AT91_REG *) 0xFFFB4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TPR (AT91_CAST(AT91_REG *) 0xFFFB4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_TCR (AT91_CAST(AT91_REG *) 0xFFFB410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RNPR (AT91_CAST(AT91_REG *) 0xFFFB4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TNCR (AT91_CAST(AT91_REG *) 0xFFFB411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR (AT91_CAST(AT91_REG *) 0xFFFB4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TNPR (AT91_CAST(AT91_REG *) 0xFFFB4118) // (PDC_US1) Transmit Next Pointer Register
+// ========== Register definition for US1 peripheral ==========
+#define AT91C_US1_THR (AT91_CAST(AT91_REG *) 0xFFFB401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR (AT91_CAST(AT91_REG *) 0xFFFB4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_BRGR (AT91_CAST(AT91_REG *) 0xFFFB4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IDR (AT91_CAST(AT91_REG *) 0xFFFB400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_MR (AT91_CAST(AT91_REG *) 0xFFFB4004) // (US1) Mode Register
+#define AT91C_US1_RTOR (AT91_CAST(AT91_REG *) 0xFFFB4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_MAN (AT91_CAST(AT91_REG *) 0xFFFB4050) // (US1) Manchester Encoder Decoder Register
+#define AT91C_US1_CR (AT91_CAST(AT91_REG *) 0xFFFB4000) // (US1) Control Register
+#define AT91C_US1_IMR (AT91_CAST(AT91_REG *) 0xFFFB4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI (AT91_CAST(AT91_REG *) 0xFFFB4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_RHR (AT91_CAST(AT91_REG *) 0xFFFB4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IER (AT91_CAST(AT91_REG *) 0xFFFB4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CSR (AT91_CAST(AT91_REG *) 0xFFFB4014) // (US1) Channel Status Register
+#define AT91C_US1_IF (AT91_CAST(AT91_REG *) 0xFFFB404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER (AT91_CAST(AT91_REG *) 0xFFFB4044) // (US1) Nb Errors Register
+// ========== Register definition for PDC_SPI peripheral ==========
+#define AT91C_SPI_PTSR (AT91_CAST(AT91_REG *) 0xFFFAC124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_RPR (AT91_CAST(AT91_REG *) 0xFFFAC100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_RNCR (AT91_CAST(AT91_REG *) 0xFFFAC114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_RCR (AT91_CAST(AT91_REG *) 0xFFFAC104) // (PDC_SPI) Receive Counter Register
+#define AT91C_SPI_PTCR (AT91_CAST(AT91_REG *) 0xFFFAC120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TPR (AT91_CAST(AT91_REG *) 0xFFFAC108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RNPR (AT91_CAST(AT91_REG *) 0xFFFAC110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TNPR (AT91_CAST(AT91_REG *) 0xFFFAC118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_TCR (AT91_CAST(AT91_REG *) 0xFFFAC10C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_TNCR (AT91_CAST(AT91_REG *) 0xFFFAC11C) // (PDC_SPI) Transmit Next Counter Register
+// ========== Register definition for SPI peripheral ==========
+#define AT91C_SPI_IER (AT91_CAST(AT91_REG *) 0xFFFAC014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_RDR (AT91_CAST(AT91_REG *) 0xFFFAC008) // (SPI) Receive Data Register
+#define AT91C_SPI_IMR (AT91_CAST(AT91_REG *) 0xFFFAC01C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_SR (AT91_CAST(AT91_REG *) 0xFFFAC010) // (SPI) Status Register
+#define AT91C_SPI_TDR (AT91_CAST(AT91_REG *) 0xFFFAC00C) // (SPI) Transmit Data Register
+#define AT91C_SPI_CSR (AT91_CAST(AT91_REG *) 0xFFFAC030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR (AT91_CAST(AT91_REG *) 0xFFFAC018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_MR (AT91_CAST(AT91_REG *) 0xFFFAC004) // (SPI) Mode Register
+#define AT91C_SPI_CR (AT91_CAST(AT91_REG *) 0xFFFAC000) // (SPI) Control Register
+// ========== Register definition for PDC_ADC peripheral ==========
+#define AT91C_ADC_RNCR (AT91_CAST(AT91_REG *) 0xFFFA8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR (AT91_CAST(AT91_REG *) 0xFFFA810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR (AT91_CAST(AT91_REG *) 0xFFFA8104) // (PDC_ADC) Receive Counter Register
+#define AT91C_ADC_TNPR (AT91_CAST(AT91_REG *) 0xFFFA8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR (AT91_CAST(AT91_REG *) 0xFFFA8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RPR (AT91_CAST(AT91_REG *) 0xFFFA8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TNCR (AT91_CAST(AT91_REG *) 0xFFFA811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_TPR (AT91_CAST(AT91_REG *) 0xFFFA8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_PTSR (AT91_CAST(AT91_REG *) 0xFFFA8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR (AT91_CAST(AT91_REG *) 0xFFFA8120) // (PDC_ADC) PDC Transfer Control Register
+// ========== Register definition for ADC peripheral ==========
+#define AT91C_ADC_IDR (AT91_CAST(AT91_REG *) 0xFFFA8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CDR0 (AT91_CAST(AT91_REG *) 0xFFFA8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CHDR (AT91_CAST(AT91_REG *) 0xFFFA8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_CDR6 (AT91_CAST(AT91_REG *) 0xFFFA8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CDR1 (AT91_CAST(AT91_REG *) 0xFFFA8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_MR (AT91_CAST(AT91_REG *) 0xFFFA8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CHER (AT91_CAST(AT91_REG *) 0xFFFA8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CDR2 (AT91_CAST(AT91_REG *) 0xFFFA8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_IMR (AT91_CAST(AT91_REG *) 0xFFFA802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR3 (AT91_CAST(AT91_REG *) 0xFFFA803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_IER (AT91_CAST(AT91_REG *) 0xFFFA8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHSR (AT91_CAST(AT91_REG *) 0xFFFA8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_CDR5 (AT91_CAST(AT91_REG *) 0xFFFA8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CDR7 (AT91_CAST(AT91_REG *) 0xFFFA804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CR (AT91_CAST(AT91_REG *) 0xFFFA8000) // (ADC) ADC Control Register
+#define AT91C_ADC_SR (AT91_CAST(AT91_REG *) 0xFFFA801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4 (AT91_CAST(AT91_REG *) 0xFFFA8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_LCDR (AT91_CAST(AT91_REG *) 0xFFFA8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for SYS peripheral ==========
+#define AT91C_SYS_SYS_OSCMR (AT91_CAST(AT91_REG *) 0xFFFFFD50) // (SYS) 32K Oscillator Mode Register
+#define AT91C_SYS_GPBR (AT91_CAST(AT91_REG *) 0xFFFFFD60) // (SYS) General Purpose Register
+
+// *****************************************************************************
+// PIO DEFINITIONS FOR AT91CAP7
+// *****************************************************************************
+#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0
+#define AT91C_PA0_FIQ (AT91C_PIO_PA0) //
+#define AT91C_PA0_DRXD (AT91C_PIO_PA0) //
+#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1
+#define AT91C_PA1_EBI_NWAIT (AT91C_PIO_PA1) //
+#define AT91C_PA1_DTXD (AT91C_PIO_PA1) //
+#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_IRQ0 (AT91C_PIO_PA10) //
+#define AT91C_PA10_SPI_NPCS0 (AT91C_PIO_PA10) //
+#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_IRQ1 (AT91C_PIO_PA11) //
+#define AT91C_PA11_SPI_NPCS1 (AT91C_PIO_PA11) //
+#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_EBI_NCS5_CFCS1 (AT91C_PIO_PA12) //
+#define AT91C_PA12_SPI_NPCS2 (AT91C_PIO_PA12) //
+#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_EBI_CFCE2 (AT91C_PIO_PA13) //
+#define AT91C_PA13_SPI_NPCS3 (AT91C_PIO_PA13) //
+#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_EBI_A23 (AT91C_PIO_PA14) //
+#define AT91C_PA14_PCK0 (AT91C_PIO_PA14) //
+#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_EBI_A24 (AT91C_PIO_PA15) //
+#define AT91C_PA15_PCK1 (AT91C_PIO_PA15) //
+#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_EBI_D16 (AT91C_PIO_PA16) //
+#define AT91C_PA16_PCK2 (AT91C_PIO_PA16) //
+#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_EBI_D17 (AT91C_PIO_PA17) //
+#define AT91C_PA17_PCK3 (AT91C_PIO_PA17) //
+#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_EBI_D18 (AT91C_PIO_PA18) //
+#define AT91C_PA18_SCK1 (AT91C_PIO_PA18) //
+#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_EBI_D19 (AT91C_PIO_PA19) //
+#define AT91C_PA19_RTS1 (AT91C_PIO_PA19) //
+#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2
+#define AT91C_PA2_EBI_NCS4_CFCS0 (AT91C_PIO_PA2) //
+#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) //
+#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_EBI_D20 (AT91C_PIO_PA20) //
+#define AT91C_PA20_CTS1 (AT91C_PIO_PA20) //
+#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_EBI_D21 (AT91C_PIO_PA21) //
+#define AT91C_PA21_TXD1 (AT91C_PIO_PA21) //
+#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_EBI_D22 (AT91C_PIO_PA22) //
+#define AT91C_PA22_RXD1 (AT91C_PIO_PA22) //
+#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_EBI_D23 (AT91C_PIO_PA23) //
+#define AT91C_PA23_TCLK0 (AT91C_PIO_PA23) //
+#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_EBI_D24 (AT91C_PIO_PA24) //
+#define AT91C_PA24_TCLK1 (AT91C_PIO_PA24) //
+#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_EBI_D25 (AT91C_PIO_PA25) //
+#define AT91C_PA25_TCLK2 (AT91C_PIO_PA25) //
+#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_EBI_D26 (AT91C_PIO_PA26) //
+#define AT91C_PA26_TIOA0 (AT91C_PIO_PA26) //
+#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_EBI_D27 (AT91C_PIO_PA27) //
+#define AT91C_PA27_TIOB0 (AT91C_PIO_PA27) //
+#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_EBI_D28 (AT91C_PIO_PA28) //
+#define AT91C_PA28_TIOA1 (AT91C_PIO_PA28) //
+#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_EBI_D29 (AT91C_PIO_PA29) //
+#define AT91C_PA29_TIOB1 (AT91C_PIO_PA29) //
+#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3
+#define AT91C_PA3_EBI_CFCE1 (AT91C_PIO_PA3) //
+#define AT91C_PA3_RTS0 (AT91C_PIO_PA3) //
+#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_EBI_D30 (AT91C_PIO_PA30) //
+#define AT91C_PA30_TIOA2 (AT91C_PIO_PA30) //
+#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_EBI_D31 (AT91C_PIO_PA31) //
+#define AT91C_PA31_TIOB2 (AT91C_PIO_PA31) //
+#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4
+#define AT91C_PA4_EBI_A25_CFRNW (AT91C_PIO_PA4) //
+#define AT91C_PA4_CTS0 (AT91C_PIO_PA4) //
+#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5
+#define AT91C_PA5_EBI_NANDOE (AT91C_PIO_PA5) //
+#define AT91C_PA5_TXD0 (AT91C_PIO_PA5) //
+#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6
+#define AT91C_PA6_EBI_NANDWE (AT91C_PIO_PA6) //
+#define AT91C_PA6_RXD0 (AT91C_PIO_PA6) //
+#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7
+#define AT91C_PA7_EBI_NCS6 (AT91C_PIO_PA7) //
+#define AT91C_PA7_SPI_MISO (AT91C_PIO_PA7) //
+#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8
+#define AT91C_PA8_EBI_NCS7 (AT91C_PIO_PA8) //
+#define AT91C_PA8_SPI_MOSI (AT91C_PIO_PA8) //
+#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9
+#define AT91C_PA9_ADCTRIG (AT91C_PIO_PA9) //
+#define AT91C_PA9_SPI_SPCK (AT91C_PIO_PA9) //
+
+// *****************************************************************************
+// PERIPHERAL ID DEFINITIONS FOR AT91CAP7
+// *****************************************************************************
+#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS ( 1) // System Controller
+#define AT91C_ID_PIOA ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB ( 3) // Parallel IO Controller B
+#define AT91C_ID_US0 ( 4) // USART 0
+#define AT91C_ID_US1 ( 5) // USART 1
+#define AT91C_ID_SPI ( 6) // Serial Peripheral Interface
+#define AT91C_ID_TC0 ( 7) // Timer Counter 0
+#define AT91C_ID_TC1 ( 8) // Timer Counter 1
+#define AT91C_ID_TC2 ( 9) // Timer Counter 2
+#define AT91C_ID_UDP (10) // USB Device Port
+#define AT91C_ID_ADC (11) // ADC Controller
+#define AT91C_ID_MPP0 (12) // MP Block Peripheral 0
+#define AT91C_ID_MPP1 (13) // MP Block Peripheral 1
+#define AT91C_ID_MPP2 (14) // MP Block Peripheral 2
+#define AT91C_ID_MPP3 (15) // MP Block Peripheral 3
+#define AT91C_ID_MPP4 (16) // MP Block Peripheral 4
+#define AT91C_ID_MPP5 (17) // MP Block Peripheral 5
+#define AT91C_ID_MPP6 (18) // MP Block Peripheral 6
+#define AT91C_ID_MPP7 (19) // MP Block Peripheral 7
+#define AT91C_ID_MPP8 (20) // MP Block Peripheral 8
+#define AT91C_ID_MPP9 (21) // MP Block Peripheral 9
+#define AT91C_ID_MPP10 (22) // MP Block Peripheral 10
+#define AT91C_ID_MPP11 (23) // MP Block Peripheral 11
+#define AT91C_ID_MPP12 (24) // MP Block Peripheral 12
+#define AT91C_ID_MPP13 (25) // MP Block Peripheral 13
+#define AT91C_ID_MPMA (26) // MP Block Master A
+#define AT91C_ID_MPMB (27) // MP Block Master B
+#define AT91C_ID_MPMC (28) // MP Block Master C
+#define AT91C_ID_MPMD (29) // MP Block Master D
+#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1)
+#define AT91C_ALL_INT (0xFFFFFFFF) // ALL VALID INTERRUPTS
+
+// *****************************************************************************
+// BASE ADDRESS DEFINITIONS FOR AT91CAP7
+// *****************************************************************************
+#define AT91C_BASE_SDRAMC (AT91_CAST(AT91PS_SDRAMC) 0xFFFFEA00) // (SDRAMC) Base Address
+#define AT91C_BASE_SMC (AT91_CAST(AT91PS_SMC) 0xFFFFEC00) // (SMC) Base Address
+#define AT91C_BASE_MATRIX_PRS (AT91_CAST(AT91PS_MATRIX_PRS) 0xFFFFEE80) // (MATRIX_PRS) Base Address
+#define AT91C_BASE_MATRIX (AT91_CAST(AT91PS_MATRIX) 0xFFFFEE00) // (MATRIX) Base Address
+#define AT91C_BASE_PDC_DBGU (AT91_CAST(AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU (AT91_CAST(AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_AIC (AT91_CAST(AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PIOA (AT91_CAST(AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB (AT91_CAST(AT91PS_PIO) 0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR (AT91_CAST(AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC (AT91_CAST(AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC (AT91_CAST(AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_SHDWC (AT91_CAST(AT91PS_SHDWC) 0xFFFFFD10) // (SHDWC) Base Address
+#define AT91C_BASE_RTTC (AT91_CAST(AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC (AT91_CAST(AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC (AT91_CAST(AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_UDP (AT91_CAST(AT91PS_UDP) 0xFFFA4000) // (UDP) Base Address
+#define AT91C_BASE_TC0 (AT91_CAST(AT91PS_TC) 0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1 (AT91_CAST(AT91PS_TC) 0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2 (AT91_CAST(AT91PS_TC) 0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB (AT91_CAST(AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PDC_US0 (AT91_CAST(AT91PS_PDC) 0xFFFB0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0 (AT91_CAST(AT91PS_USART) 0xFFFB0000) // (US0) Base Address
+#define AT91C_BASE_PDC_US1 (AT91_CAST(AT91PS_PDC) 0xFFFB4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1 (AT91_CAST(AT91PS_USART) 0xFFFB4000) // (US1) Base Address
+#define AT91C_BASE_PDC_SPI (AT91_CAST(AT91PS_PDC) 0xFFFAC100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI (AT91_CAST(AT91PS_SPI) 0xFFFAC000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC (AT91_CAST(AT91PS_PDC) 0xFFFA8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC (AT91_CAST(AT91PS_ADC) 0xFFFA8000) // (ADC) Base Address
+#define AT91C_BASE_SYS (AT91_CAST(AT91PS_SYS) 0xFFFFEA00) // (SYS) Base Address
+
+// *****************************************************************************
+// MEMORY MAPPING DEFINITIONS FOR AT91CAP7
+// *****************************************************************************
+// IRAM
+#define AT91C_IRAM (0x001F0000) // 160-KBytes FAST SRAM base address
+#define AT91C_IRAM_SIZE (0x00028000) // 160-KBytes FAST SRAM size in byte (160 Kbytes)
+// IRAM_MIN
+#define AT91C_IRAM_MIN (0x001F0000) // Minimum Internal RAM base address
+#define AT91C_IRAM_MIN_SIZE (0x00028000) // Minimum Internal RAM size in byte (160 Kbytes)
+// IROM
+#define AT91C_IROM (0x00400000) // Internal ROM base address
+#define AT91C_IROM_SIZE (0x00040000) // Internal ROM size in byte (256 Kbytes)
+// EBI_CS0
+#define AT91C_EBI_CS0 (0x10000000) // EBI Chip Select 0 base address
+#define AT91C_EBI_CS0_SIZE (0x10000000) // EBI Chip Select 0 size in byte (262144 Kbytes)
+// EBI_CS1
+#define AT91C_EBI_CS1 (0x20000000) // EBI Chip Select 1 base address
+#define AT91C_EBI_CS1_SIZE (0x10000000) // EBI Chip Select 1 size in byte (262144 Kbytes)
+// EBI_SDRAM
+#define AT91C_EBI_SDRAM (0x20000000) // SDRAM on EBI Chip Select 2 base address
+#define AT91C_EBI_SDRAM_SIZE (0x10000000) // SDRAM on EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS2
+#define AT91C_EBI_CS2 (0x30000000) // EBI Chip Select 2 base address
+#define AT91C_EBI_CS2_SIZE (0x10000000) // EBI Chip Select 2 size in byte (262144 Kbytes)
+// EBI_CS3
+#define AT91C_EBI_CS3 (0x40000000) // EBI Chip Select 3 base address
+#define AT91C_EBI_CS3_SIZE (0x10000000) // EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_SM
+#define AT91C_EBI_SM (0x40000000) // SmartMedia on EBI Chip Select 3 base address
+#define AT91C_EBI_SM_SIZE (0x10000000) // SmartMedia on EBI Chip Select 3 size in byte (262144 Kbytes)
+// EBI_CS4
+#define AT91C_EBI_CS4 (0x50000000) // EBI Chip Select 4 base address
+#define AT91C_EBI_CS4_SIZE (0x10000000) // EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CF0
+#define AT91C_EBI_CF0 (0x50000000) // CompactFlash 0 on EBI Chip Select 4 base address
+#define AT91C_EBI_CF0_SIZE (0x10000000) // CompactFlash 0 on EBI Chip Select 4 size in byte (262144 Kbytes)
+// EBI_CS5
+#define AT91C_EBI_CS5 (0x60000000) // EBI Chip Select 5 base address
+#define AT91C_EBI_CS5_SIZE (0x10000000) // EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CF1
+#define AT91C_EBI_CF1 (0x60000000) // CompactFlash 1 on EBI Chip Select 5 base address
+#define AT91C_EBI_CF1_SIZE (0x10000000) // CompactFlash 1 on EBI Chip Select 5 size in byte (262144 Kbytes)
+// EBI_CS6
+#define AT91C_EBI_CS6 (0x70000000) // EBI Chip Select 6 base address
+#define AT91C_EBI_CS6_SIZE (0x10000000) // EBI Chip Select 6 size in byte (262144 Kbytes)
+// EBI_CS7
+#define AT91C_EBI_CS7 (0x60000000) // EBI Chip Select 7 base address
+#define AT91C_EBI_CS7_SIZE (0x10000000) // EBI Chip Select 7 size in byte (262144 Kbytes)
+
+#endif
diff --git a/boards/at91cap7-stk/at91cap7/chip.h b/boards/at91cap7-stk/at91cap7/chip.h new file mode 100644 index 0000000..ff0c909 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/chip.h @@ -0,0 +1,108 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \unit
+/// !Purpose
+///
+/// Definition of AT91CAP7 characteristics and features
+///
+/// !Usage
+/// -# For ARM core feature, see "AT91CAP7 - ARM core features".
+/// -# For IP features, see "AT91CAP7 - IP features".
+/// -# For misc, see "AT91CAP7 - Misc".
+//------------------------------------------------------------------------------
+
+#ifndef CHIP_H
+#define CHIP_H
+
+//------------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// \page "AT91CAP7 - ARM core features"
+/// This page lists several characteristics related to the ARM core
+///
+
+//ARM core features
+
+/// ARM core definition.
+#define arm7tdmi
+
+/// family definition.
+//#define at91cap7 (already defined)
+
+//------------------------------------------------------------------------------
+/// \page "AT91CAP7 - IP features"
+/// This page lists several characteristics related to the embedded IP
+///
+
+//IP FEATURES
+
+/// Indicates chip has an UDP Full Speed.
+#define CHIP_USB_UDP
+
+/// Indicates chip has an internal pull-up set by matrix.
+#define CHIP_USB_PULLUP_MATRIX
+
+/// Number of USB endpoints
+#define CHIP_USB_NUMENDPOINTS 6
+
+/// Endpoints max paxcket size
+#define CHIP_USB_ENDPOINTS_MAXPACKETSIZE(i) \
+ ((i == 0) ? 8 : \
+ ((i == 1) ? 64 : \
+ ((i == 2) ? 64 : \
+ ((i == 3) ? 64 : \
+ ((i == 4) ? 256 : \
+ ((i == 5) ? 256 : 0 ))))))
+
+/// Endpoints Number of Bank
+#define CHIP_USB_ENDPOINTS_BANKS(i) \
+ ((i == 0) ? 1 : \
+ ((i == 1) ? 2 : \
+ ((i == 2) ? 2 : \
+ ((i == 3) ? 1 : \
+ ((i == 4) ? 2 : \
+ ((i == 5) ? 2 : 0 ))))))
+
+//------------------------------------------------------------------------------
+/// \page "AT91CAP7 - Misc "
+/// This page lists misc features
+///
+
+//Misc
+
+#endif //#ifndef CHIP_H
+
diff --git a/boards/at91cap7-stk/at91cap7/chip.mak b/boards/at91cap7-stk/at91cap7/chip.mak new file mode 100644 index 0000000..0fc410d --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/chip.mak @@ -0,0 +1,32 @@ +# ----------------------------------------------------------------------------
+# ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2008, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# Defines which are the specific available IP for the chip AT91CAP7
+CHIP_CORE = arm7tdmi
+CHIP_IP_UDP = USB_UDP
+
diff --git a/boards/at91cap7-stk/at91cap7/sdram.icf b/boards/at91cap7-stk/at91cap7/sdram.icf new file mode 100644 index 0000000..5a11434 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sdram.icf @@ -0,0 +1,48 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+/*-Memory Regions-*/
+
+define symbol __ICFEDIT_region_SDRAM_start__ = 0x20000000;
+define symbol __ICFEDIT_region_SDRAM_end__ = 0x23FFFFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x1f0000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x217fff;
+
+/*-Sizes-*/
+define symbol __ICFEDIT_size_startup__ = 0x100;
+define symbol __ICFEDIT_size_vectors__ = 0x100;
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+
+/*-Exports-*/
+export symbol __ICFEDIT_region_SDRAM_start__;
+export symbol __ICFEDIT_region_SDRAM_end__;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+define region STA_region = mem:[from __ICFEDIT_region_SDRAM_start__ size __ICFEDIT_size_startup__];
+define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__+__ICFEDIT_size_startup__ to __ICFEDIT_region_SDRAM_end__];
+
+define block CSTACK with alignment = 4, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 4, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 4, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP with alignment = 4, size = __ICFEDIT_size_heap__ { };
+
+initialize by copy { section .vectors };
+do not initialize { section .noinit };
+
+place in STA_region { section .cstartup };
+place in VEC_region { section .vectors };
+place in SDRAM_region { readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP };
diff --git a/boards/at91cap7-stk/at91cap7/sdram.lds b/boards/at91cap7-stk/at91cap7/sdram.lds new file mode 100644 index 0000000..3b5ab57 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sdram.lds @@ -0,0 +1,89 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support - ROUSSET -
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2007, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaiimer below.
+ *
+ * - Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the disclaimer below in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in external SDRAM on the AT91CAP7
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x1f0000, LENGTH = 0x28000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ . = ALIGN(4);
+ _efixed = .;
+ } >sdram
+
+ .relocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ *(.vectors);
+ *(.ramfunc)
+ *(.data)
+ . = ALIGN(4);
+ _erelocate = .;
+ } >sram
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ _ezero = .;
+ } >sram
+
+ .zero (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ _ezero = .;
+ } >sdram
+
+ _sstack = 0x24000000;
+}
+end = .;
+
+
diff --git a/boards/at91cap7-stk/at91cap7/sdram_samba.lds b/boards/at91cap7-stk/at91cap7/sdram_samba.lds new file mode 100644 index 0000000..d656a87 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sdram_samba.lds @@ -0,0 +1,87 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in external SDRAM on the AT91CAP7
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x1f0000, LENGTH = 0x28000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed :
+ {
+ . = ALIGN(4);
+ _sfixed = .;
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.data)
+ *(.CP15_*)
+ . = ALIGN(4);
+ _efixed = .;
+ } >sdram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ *(.vectors);
+ . = ALIGN(4);
+ _epostrelocate = .;
+ } >sram
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sdram
+
+ _sstack = 0x218000;
+}
+end = .;
+
diff --git a/boards/at91cap7-stk/at91cap7/sram.icf b/boards/at91cap7-stk/at91cap7/sram.icf new file mode 100644 index 0000000..65cb5b8 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sram.icf @@ -0,0 +1,38 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
+
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_RAM_start__ = 0x001f0000;
+define symbol __ICFEDIT_region_RAM_end__ = 0x00217fff;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_vectors__ = 0x100;
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_svcstack__ = 0x60;
+define symbol __ICFEDIT_size_irqstack__ = 0x60;
+define symbol __ICFEDIT_size_heap__ = 0x0;
+
+/*-Exports-*/
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+export symbol __ICFEDIT_size_vectors__;
+export symbol __ICFEDIT_size_cstack__;
+export symbol __ICFEDIT_size_svcstack__;
+export symbol __ICFEDIT_size_irqstack__;
+export symbol __ICFEDIT_size_heap__;
+
+/**** End of ICF editor section. ###ICF###*/
+
+define memory mem with size = 4G;
+define region VEC_region = mem:[from __ICFEDIT_region_RAM_start__ size __ICFEDIT_size_vectors__];
+define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__+__ICFEDIT_size_vectors__ to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK with alignment = 4, size = __ICFEDIT_size_cstack__ { };
+define block SVC_STACK with alignment = 4, size = __ICFEDIT_size_svcstack__ { };
+define block IRQ_STACK with alignment = 4, size = __ICFEDIT_size_irqstack__ { };
+define block HEAP with alignment = 4, size = __ICFEDIT_size_heap__ { };
+
+do not initialize { section .noinit };
+
+place in VEC_region { section .vectors };
+place in RAM_region { section .cstartup, readonly, readwrite, block IRQ_STACK, block SVC_STACK, block CSTACK, block HEAP};
diff --git a/boards/at91cap7-stk/at91cap7/sram.lds b/boards/at91cap7-stk/at91cap7/sram.lds new file mode 100644 index 0000000..4fb6504 --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sram.lds @@ -0,0 +1,80 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in internal SRAM on the AT91SAM7S512.
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ sram (W!RX) : ORIGIN = 0x1f0000, LENGTH = 0x28000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+
+ {
+ . = ALIGN(4);
+ .fixed :
+ {
+ _sfixed = .;
+ *(.vectors)
+ *(.ramfunc)
+ *(.text*)
+ *(.rodata*)
+ *(.glue_7)
+ *(.glue_7t)
+ *(.data)
+ . = ALIGN(4);
+ _efixed = .;
+ } >sram
+
+ .relocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _srelocate = .;
+ . = ALIGN(4);
+ _erelocate = .;
+ }
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sram
+
+
+ _sstack = 0x218000;
+}
+end = .;
diff --git a/boards/at91cap7-stk/at91cap7/sram_samba.lds b/boards/at91cap7-stk/at91cap7/sram_samba.lds new file mode 100644 index 0000000..3cb28ec --- /dev/null +++ b/boards/at91cap7-stk/at91cap7/sram_samba.lds @@ -0,0 +1,97 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+/*------------------------------------------------------------------------------
+ * Linker script for running in internal SRAM on the AT91CAP7
+ *----------------------------------------------------------------------------*/
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(entry)
+
+MEMORY
+{
+ romcodesram (W!RX) : ORIGIN = 0x1f0000, LENGTH = 0x1000
+ sram (W!RX) : ORIGIN = 0x1f1000, LENGTH = 0x27000
+ sdram (W!RX) : ORIGIN = 0x20000000, LENGTH = 0x4000000
+}
+
+SECTIONS
+{
+ .fixed0 :
+ {
+ . = ALIGN(4);
+ _sfixed0 = .;
+ *(.vectors)
+ *(.text*)
+ *(.CP15_*)
+ *(.glue_7)
+ *(.glue_7t)
+ . = ALIGN(4);
+ _efixed0 = .;
+ _efixed = .;
+ } >sram
+
+ .fixed1 :
+ {
+ . = ALIGN(4);
+ _sfixed1 = .;
+ *(.rodata*)
+ *(.data)
+ . = ALIGN(4);
+ _efixed1 = .;
+ } >sram
+
+ .prerelocate : AT (_efixed)
+ {
+ . = ALIGN(4);
+ _sprerelocate = .;
+ . = ALIGN(4);
+ _eprerelocate = .;
+ }
+
+ .postrelocate : AT (_efixed + SIZEOF(.prerelocate))
+ {
+ . = ALIGN(4);
+ _spostrelocate = .;
+ . = ALIGN(4);
+ _epostrelocate = .;
+ }
+
+ .bss (NOLOAD) : {
+ _szero = .;
+ *(.bss)
+ . = ALIGN(4);
+ _ezero = .;
+ } >sram
+
+ _sstack = 0x218000;
+}
+end = .;
+
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