diff options
Diffstat (limited to 'drivers/macb')
| -rw-r--r-- | drivers/macb/macb.c | 569 | ||||
| -rw-r--r-- | drivers/macb/macb.dir | 42 | ||||
| -rw-r--r-- | drivers/macb/macb.h | 106 | ||||
| -rw-r--r-- | drivers/macb/mii.h | 178 |
4 files changed, 895 insertions, 0 deletions
diff --git a/drivers/macb/macb.c b/drivers/macb/macb.c new file mode 100644 index 0000000..0f387dd --- /dev/null +++ b/drivers/macb/macb.c @@ -0,0 +1,569 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+// drivers/macb/macb.c
+
+//-----------------------------------------------------------------------------
+// Headers
+//-----------------------------------------------------------------------------
+#include "macb.h"
+#include "mii.h"
+#include <pio/pio.h>
+#include <rstc/rstc.h>
+#include <emac/emac.h>
+#include <utility/trace.h>
+#include <utility/assert.h>
+
+//-----------------------------------------------------------------------------
+// Definitions
+//-----------------------------------------------------------------------------
+
+/// Default max retry count
+#define MACB_RETRY_MAX 1000000
+
+//-----------------------------------------------------------------------------
+/// Dump all the useful registers
+/// \param pMacb Pointer to the MACB instance
+//-----------------------------------------------------------------------------
+static void MACB_DumpRegisters(Macb *pMacb)
+{
+ unsigned char phyAddress;
+ unsigned int retryMax;
+ unsigned int value;
+
+ TRACE_INFO("MACB_DumpRegisters\n\r");
+ ASSERT(pMacb, "F: MACB_DumpRegisters\n\r");
+
+ EMAC_EnableMdio();
+ phyAddress = pMacb->phyAddress;
+ retryMax = pMacb->retryMax;
+
+ TRACE_INFO("MII MACB @%d) Registers:\n\r", phyAddress);
+
+ EMAC_ReadPhy(phyAddress, MII_BMCR, &value, retryMax);
+ TRACE_INFO(" _BMCR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_BMSR, &value, retryMax);
+ TRACE_INFO(" _BMSR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_ANAR, &value, retryMax);
+ TRACE_INFO(" _ANAR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_ANLPAR, &value, retryMax);
+ TRACE_INFO(" _ANLPAR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_ANER, &value, retryMax);
+ TRACE_INFO(" _ANER : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_DSCR, &value, retryMax);
+ TRACE_INFO(" _DSCR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_DSCSR, &value, retryMax);
+ TRACE_INFO(" _DSCSR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_10BTCSR, &value, retryMax);
+ TRACE_INFO(" _10BTCSR: 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_PWDOR, &value, retryMax);
+ TRACE_INFO(" _PWDOR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_CONFIGR, &value, retryMax);
+ TRACE_INFO(" _CONFIGR: 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_MDINTR, &value, retryMax);
+ TRACE_INFO(" _MDINTR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_RECR, &value, retryMax);
+ TRACE_INFO(" _RECR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_DISCR, &value, retryMax);
+ TRACE_INFO(" _DISCR : 0x%X\n\r", value);
+ EMAC_ReadPhy(phyAddress, MII_RLSR, &value, retryMax);
+ TRACE_INFO(" _RLSR : 0x%X\n\r", value);
+
+ EMAC_DisableMdio();
+}
+
+//-----------------------------------------------------------------------------
+/// Find a valid PHY Address ( from 0 to 31 ).
+/// Check BMSR register ( not 0 nor 0xFFFF )
+/// Return 0xFF when no valid PHY Address found.
+/// \param pMacb Pointer to the MACB instance
+//-----------------------------------------------------------------------------
+static unsigned char MACB_FindValidPhy(Macb *pMacb)
+{
+ unsigned int retryMax;
+ unsigned int value=0;
+ unsigned char rc;
+ unsigned char phyAddress;
+ unsigned char cnt;
+
+ TRACE_DEBUG("MACB_FindValidPhy\n\r");
+ ASSERT(pMacb, "F: MACB_FindValidPhy\n\r");
+
+ EMAC_EnableMdio();
+ phyAddress = pMacb->phyAddress;
+ retryMax = pMacb->retryMax;
+
+ // Check current phyAddress
+ rc = phyAddress;
+ if( EMAC_ReadPhy(phyAddress, MII_PHYID1, &value, retryMax) == 0 ) {
+ TRACE_ERROR("MACB PROBLEM\n\r");
+ }
+ TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
+
+ // Find another one
+ if (value != MII_OUI_MSB) {
+
+ rc = 0xFF;
+ for(cnt = 0; cnt < 32; cnt ++) {
+
+ phyAddress = (phyAddress + 1) & 0x1F;
+ if( EMAC_ReadPhy(phyAddress, MII_PHYID1, &value, retryMax) == 0 ) {
+ TRACE_ERROR("MACB PROBLEM\n\r");
+ }
+ TRACE_DEBUG("_PHYID1 : 0x%X, addr: %d\n\r", value, phyAddress);
+ if (value == MII_OUI_MSB) {
+
+ rc = phyAddress;
+ break;
+ }
+ }
+ }
+
+ EMAC_DisableMdio();
+ if (rc != 0xFF) {
+
+ TRACE_INFO("** Valid PHY Found: %d\n\r", rc);
+ EMAC_ReadPhy(phyAddress, MII_DSCSR, &value, retryMax);
+ TRACE_DEBUG("_DSCSR : 0x%X, addr: %d\n\r", value, phyAddress);
+
+ }
+ return rc;
+}
+
+
+//-----------------------------------------------------------------------------
+// Exported functions
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// Setup the maximum timeout count of the driver.
+/// \param pMacb Pointer to the MACB instance
+/// \param toMax Timeout maxmum count.
+//-----------------------------------------------------------------------------
+void MACB_SetupTimeout(Macb *pMacb, unsigned int toMax)
+{
+ ASSERT(pMacb, "-F- MACB_SetupTimeout\n\r");
+
+ pMacb->retryMax = toMax;
+}
+
+//-----------------------------------------------------------------------------
+/// Initialize the MACB instance
+/// \param pMacb Pointer to the MACB instance
+/// \param pEmac Pointer to the Emac instance for the MACB
+/// \param phyAddress The PHY address used to access the PHY
+/// ( pre-defined by pin status on PHY reset )
+//-----------------------------------------------------------------------------
+void MACB_Init(Macb *pMacb, unsigned char phyAddress)
+{
+ ASSERT(pMacb , "-F- MACB_Init\n\r");
+
+ pMacb->phyAddress = phyAddress;
+
+ // Initialize timeout by default
+ pMacb->retryMax = MACB_RETRY_MAX;
+}
+
+
+//-----------------------------------------------------------------------------
+/// Issue a SW reset to reset all registers of the PHY
+/// Return 1 if successfully, 0 if timeout.
+/// \param pMacb Pointer to the MACB instance
+//-----------------------------------------------------------------------------
+static unsigned char MACB_ResetPhy(Macb *pMacb)
+{
+ unsigned int retryMax;
+ unsigned int bmcr = MII_RESET;
+ unsigned char phyAddress;
+ unsigned int timeout = 10;
+ unsigned char ret = 1;
+
+ ASSERT(pMacb, "-F- MACB_ResetPhy");
+ TRACE_INFO(" MACB_ResetPhy\n\r");
+
+ phyAddress = pMacb->phyAddress;
+ retryMax = pMacb->retryMax;
+
+ EMAC_EnableMdio();
+ bmcr = MII_RESET;
+ EMAC_WritePhy(phyAddress, MII_BMCR, bmcr, retryMax);
+
+ do {
+ EMAC_ReadPhy(phyAddress, MII_BMCR, &bmcr, retryMax);
+ timeout--;
+ } while ((bmcr & MII_RESET) && timeout);
+
+ EMAC_DisableMdio();
+
+ if (!timeout) {
+ ret = 0;
+ }
+
+ return( ret );
+}
+
+//-----------------------------------------------------------------------------
+/// Do a HW initialize to the PHY ( via RSTC ) and setup clocks & PIOs
+/// This should be called only once to initialize the PHY pre-settings.
+/// The PHY address is reset status of CRS,RXD[3:0] (the emacPins' pullups).
+/// The COL pin is used to select MII mode on reset (pulled up for Reduced MII)
+/// The RXDV pin is used to select test mode on reset (pulled up for test mode)
+/// The above pins should be predefined for corresponding settings in resetPins
+/// The EMAC peripheral pins are configured after the reset done.
+/// Return 1 if RESET OK, 0 if timeout.
+/// \param pMacb Pointer to the MACB instance
+/// \param mck Main clock setting to initialize clock
+/// \param resetPins Pointer to list of PIOs to configure before HW RESET
+/// (for PHY power on reset configuration latch)
+/// \param nbResetPins Number of PIO items that should be configured
+/// \param emacPins Pointer to list of PIOs for the EMAC interface
+/// \param nbEmacPins Number of PIO items that should be configured
+//-----------------------------------------------------------------------------
+
+unsigned char MACB_InitPhy(Macb *pMacb,
+ unsigned int mck,
+ const Pin *pResetPins,
+ unsigned int nbResetPins,
+ const Pin *pEmacPins,
+ unsigned int nbEmacPins)
+{
+ unsigned char rc = 1;
+ unsigned char phy;
+ volatile unsigned int i;
+
+ ASSERT(pMacb, "-F- MACB_InitPhy\n\r");
+
+ // Perform RESET
+ TRACE_DEBUG("RESET PHY\n\r");
+
+ if (pResetPins) {
+
+ // Configure PINS
+ PIO_Configure(pResetPins, nbResetPins);
+
+#if !defined(BOARD_EMAC_RESET)
+ // Execute reset
+ RSTC_SetExtResetLength(MACB_RESET_LENGTH);
+ RSTC_ExtReset();
+ // Get NRST level
+ printf("NRST level %d\n\r", RSTC_GetNrstLevel());
+ // Wait for end hardware reset
+ while (!RSTC_GetNrstLevel());
+#else
+ int i=0;
+ const Pin nrstPin = BOARD_EMAC_RESET;
+ PIO_Configure(&nrstPin, 1);
+ for(i=0;i<100000;i++) {
+ PIO_Clear(&nrstPin);
+ }
+ PIO_Set(&nrstPin);
+#endif
+ }
+
+ // Configure EMAC runtime pins
+ if (rc) {
+
+ PIO_Configure(pEmacPins, nbEmacPins);
+ rc = EMAC_SetMdcClock( mck );
+ if (!rc) {
+
+ TRACE_ERROR("No Valid MDC clock\n\r");
+ return 0;
+ }
+
+ // Check PHY Address
+ phy = MACB_FindValidPhy(pMacb);
+ if (phy == 0xFF) {
+
+ TRACE_ERROR("PHY Access fail\n\r");
+ return 0;
+ }
+ if(phy != pMacb->phyAddress) {
+
+ pMacb->phyAddress = phy;
+
+ MACB_ResetPhy(pMacb);
+
+ }
+
+ }
+ else {
+
+ TRACE_ERROR("PHY Reset Timeout\n\r");
+ }
+
+ return rc;
+}
+
+//-----------------------------------------------------------------------------
+/// Issue a Auto Negotiation of the PHY
+/// Return 1 if successfully, 0 if timeout.
+/// \param pMacb Pointer to the MACB instance
+//-----------------------------------------------------------------------------
+unsigned char MACB_AutoNegotiate(Macb *pMacb)
+{
+ unsigned int retryMax;
+ unsigned int value;
+ unsigned int phyAnar;
+ unsigned int phyAnalpar;
+ unsigned int retryCount= 0;
+ unsigned char phyAddress;
+ unsigned char rc = 1;
+
+ ASSERT(pMacb, "-F- MACB_AutoNegotiate\n\r");
+ phyAddress = pMacb->phyAddress;
+ retryMax = pMacb->retryMax;
+
+ EMAC_EnableMdio();
+
+ if (!EMAC_ReadPhy(phyAddress, MII_PHYID1, &value, retryMax)) {
+ TRACE_ERROR("Pb EMAC_ReadPhy Id1\n\r");
+ rc = 0;
+ goto AutoNegotiateExit;
+ }
+ TRACE_DEBUG("ReadPhy Id1 0x%X, addresse: %d\n\r", value, phyAddress);
+ if (!EMAC_ReadPhy(phyAddress, MII_PHYID2, &phyAnar, retryMax)) {
+ TRACE_ERROR("Pb EMAC_ReadPhy Id2\n\r");
+ rc = 0;
+ goto AutoNegotiateExit;
+ }
+ TRACE_DEBUG("ReadPhy Id2 0x%X\n\r", phyAnar);
+
+ if( ( value == MII_OUI_MSB )
+ && ( ((phyAnar>>10)&MII_LSB_MASK) == MII_OUI_LSB ) ) {
+
+ TRACE_DEBUG("Vendor Number Model = 0x%X\n\r", ((phyAnar>>4)&0x3F));
+ TRACE_DEBUG("Model Revision Number = 0x%X\n\r", (phyAnar&0x7));
+ }
+ else {
+ TRACE_ERROR("Problem OUI value\n\r");
+ }
+
+ // Setup control register
+ rc = EMAC_ReadPhy(phyAddress, MII_BMCR, &value, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ value &= ~MII_AUTONEG; // Remove autonegotiation enable
+ value &= ~(MII_LOOPBACK|MII_POWER_DOWN);
+ value |= MII_ISOLATE; // Electrically isolate PHY
+ rc = EMAC_WritePhy(phyAddress, MII_BMCR, value, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ // Set the Auto_negotiation Advertisement Register
+ // MII advertising for Next page
+ // 100BaseTxFD and HD, 10BaseTFD and HD, IEEE 802.3
+ phyAnar = MII_TX_FDX | MII_TX_HDX |
+ MII_10_FDX | MII_10_HDX | MII_AN_IEEE_802_3;
+ rc = EMAC_WritePhy(phyAddress, MII_ANAR, phyAnar, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ // Read & modify control register
+ rc = EMAC_ReadPhy(phyAddress, MII_BMCR, &value, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ value |= MII_SPEED_SELECT | MII_AUTONEG | MII_DUPLEX_MODE;
+ rc = EMAC_WritePhy(phyAddress, MII_BMCR, value, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ // Restart Auto_negotiation
+ value |= MII_RESTART_AUTONEG;
+ value &= ~MII_ISOLATE;
+ rc = EMAC_WritePhy(phyAddress, MII_BMCR, value, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+ TRACE_DEBUG(" _BMCR: 0x%X\n\r", value);
+
+ // Check AutoNegotiate complete
+ while (1) {
+
+ rc = EMAC_ReadPhy(phyAddress, MII_BMSR, &value, retryMax);
+ if (rc == 0) {
+
+ TRACE_ERROR("rc==0\n\r");
+ goto AutoNegotiateExit;
+ }
+ // Done successfully
+ if (value & MII_AUTONEG_COMP) {
+
+ TRACE_INFO("AutoNegotiate complete\n\r");
+ break;
+ }
+ // Timeout check
+ if (retryMax) {
+
+ if (++ retryCount >= retryMax) {
+
+ MACB_DumpRegisters(pMacb);
+ TRACE_ERROR("TimeOut\n\r");
+ rc = 0;
+ goto AutoNegotiateExit;
+ }
+ }
+ }
+
+ // Get the AutoNeg Link partner base page
+ rc = EMAC_ReadPhy(phyAddress, MII_ANLPAR, &phyAnalpar, retryMax);
+ if (rc == 0) {
+
+ goto AutoNegotiateExit;
+ }
+
+ // Setup the EMAC link speed
+ if ((phyAnar & phyAnalpar) & MII_TX_FDX) {
+
+ // set MII for 100BaseTX and Full Duplex
+ EMAC_SetLinkSpeed(1, 1);
+ }
+ else if ((phyAnar & phyAnalpar) & MII_10_FDX) {
+
+ // set MII for 10BaseT and Full Duplex
+ EMAC_SetLinkSpeed(0, 1);
+ }
+ else if ((phyAnar & phyAnalpar) & MII_TX_HDX) {
+
+ // set MII for 100BaseTX and half Duplex
+ EMAC_SetLinkSpeed(1, 0);
+ }
+ else if ((phyAnar & phyAnalpar) & MII_10_HDX) {
+
+ // set MII for 10BaseT and half Duplex
+ EMAC_SetLinkSpeed(0, 0);
+ }
+
+ // Setup EMAC mode
+#if (BOARD_EMAC_MODE_RMII != 1)
+ EMAC_EnableMII();
+#else
+ EMAC_EnableRMII();
+#endif
+
+AutoNegotiateExit:
+ EMAC_DisableMdio();
+ return rc;
+}
+
+//-----------------------------------------------------------------------------
+/// Get the Link & speed settings, and automatically setup the EMAC with the
+/// settings.
+/// Return 1 if link found, 0 if no ethernet link.
+/// \param pMacb Pointer to the MACB instance
+/// \param applySetting Apply the settings to EMAC interface
+//-----------------------------------------------------------------------------
+unsigned char MACB_GetLinkSpeed(Macb *pMacb, unsigned char applySetting)
+{
+ unsigned int retryMax;
+ unsigned int stat1;
+ unsigned int stat2;
+ unsigned char phyAddress;
+ unsigned char rc = 1;
+
+ TRACE_DEBUG("MACB_GetLinkSpeed\n\r");
+ ASSERT(pMacb, "-F- MACB_GetLinkSpeed\n\r");
+
+ EMAC_EnableMdio();
+ phyAddress = pMacb->phyAddress;
+ retryMax = pMacb->retryMax;
+
+ rc = EMAC_ReadPhy(phyAddress, MII_BMSR, &stat1, retryMax);
+ if (rc == 0) {
+
+ goto GetLinkSpeedExit;
+ }
+
+ if ((stat1 & MII_LINK_STATUS) == 0) {
+
+ TRACE_ERROR("Pb: LinkStat: 0x%x\n\r", stat1);
+
+ rc = 0;
+ goto GetLinkSpeedExit;
+ }
+
+ if (applySetting == 0) {
+
+ TRACE_ERROR("Pb: applySetting: 0x%x\n\r", applySetting);
+ goto GetLinkSpeedExit;
+ }
+
+ // Re-configure Link speed
+ rc = EMAC_ReadPhy(phyAddress, MII_DSCSR, &stat2, retryMax);
+ if (rc == 0) {
+
+ TRACE_ERROR("Pb: rc: 0x%x\n\r", rc);
+ goto GetLinkSpeedExit;
+ }
+
+ if ((stat1 & MII_100BASE_TX_FD) && (stat2 & MII_100FDX)) {
+
+ // set Emac for 100BaseTX and Full Duplex
+ EMAC_SetLinkSpeed(1, 1);
+ }
+
+ if ((stat1 & MII_10BASE_T_FD) && (stat2 & MII_10FDX)) {
+
+ // set MII for 10BaseT and Full Duplex
+ EMAC_SetLinkSpeed(0, 1);
+ }
+
+ if ((stat1 & MII_100BASE_T4_HD) && (stat2 & MII_100HDX)) {
+
+ // set MII for 100BaseTX and Half Duplex
+ EMAC_SetLinkSpeed(1, 0);
+ }
+
+ if ((stat1 & MII_10BASE_T_HD) && (stat2 & MII_10HDX)) {
+
+ // set MII for 10BaseT and Half Duplex
+ EMAC_SetLinkSpeed(0, 0);
+ }
+
+ // Start the EMAC transfers
+ TRACE_DEBUG("MACB_GetLinkSpeed passed\n\r");
+
+GetLinkSpeedExit:
+ EMAC_DisableMdio();
+ return rc;
+}
+
diff --git a/drivers/macb/macb.dir b/drivers/macb/macb.dir new file mode 100644 index 0000000..708cf7f --- /dev/null +++ b/drivers/macb/macb.dir @@ -0,0 +1,42 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//------------------------------------------------------------------------------
+/// \dir
+/// !Purpose
+///
+/// Definition of methods and structures for using PHY DM9161
+///
+/// !Usage
+///
+//-----------------------------------------------------------------------------
+///
+///
+//------------------------------------------------------------------------------
+
diff --git a/drivers/macb/macb.h b/drivers/macb/macb.h new file mode 100644 index 0000000..13741a3 --- /dev/null +++ b/drivers/macb/macb.h @@ -0,0 +1,106 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//-----------------------------------------------------------------------------
+/// \unit
+///
+/// !Purpose
+///
+/// Implementation of MACB driver
+///
+/// !Contents
+///
+/// Please refer to the list of functions in the #Overview# tab of this unit
+/// for more detailed information.
+//-----------------------------------------------------------------------------
+
+
+// drivers/macb/macb.h
+
+#ifndef _MACB_H
+#define _MACB_H
+
+//-----------------------------------------------------------------------------
+// Headers
+//-----------------------------------------------------------------------------
+#include <pio/pio.h>
+
+//-----------------------------------------------------------------------------
+// Definitions
+//-----------------------------------------------------------------------------
+
+/// The reset length setting for external reset configuration
+#define MACB_RESET_LENGTH 0xD
+
+//-----------------------------------------------------------------------------
+// Types
+//-----------------------------------------------------------------------------
+
+/// The DM9161 instance
+typedef struct _Macb {
+
+ /// The retry & timeout settings
+ unsigned int retryMax;
+
+ /// PHY address ( pre-defined by pins on reset )
+ unsigned char phyAddress;
+
+} Macb, *pMacb;
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+
+extern void MACB_SetupTimeout(Macb *pMacb, unsigned int toMax);
+
+extern void MACB_Init(Macb *pMacb, unsigned char phyAddress);
+
+extern unsigned char MACB_InitPhy(Macb *pMacb,
+ unsigned int mck,
+ const Pin *pResetPins,
+ unsigned int nbResetPins,
+ const Pin *pEmacPins,
+ unsigned int nbEmacPins);
+
+extern unsigned char MACB_AutoNegotiate(Macb *pMacb);
+
+extern unsigned char MACB_GetLinkSpeed(Macb *pMacb,
+ unsigned char applySettings);
+
+extern unsigned char MACB_Send(Macb *pMacb,
+ void *pBuffer,
+ unsigned int size);
+
+extern unsigned int MACB_Poll(Macb *pMacb,
+ unsigned char *pBuffer,
+ unsigned int size);
+
+
+#endif // #ifndef _MACB_H
+
diff --git a/drivers/macb/mii.h b/drivers/macb/mii.h new file mode 100644 index 0000000..e1deda2 --- /dev/null +++ b/drivers/macb/mii.h @@ -0,0 +1,178 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+#ifndef _MII_DEFINE_H
+#define _MII_DEFINE_H
+
+
+//-----------------------------------------------------------------------------
+/// Definitions
+//-----------------------------------------------------------------------------
+
+#define MII_BMCR 0 // Basic Mode Control Register
+#define MII_BMSR 1 // Basic Mode Status Register
+#define MII_PHYID1 2 // PHY Idendifier Register 1
+#define MII_PHYID2 3 // PHY Idendifier Register 2
+#define MII_ANAR 4 // Auto_Negotiation Advertisement Register
+#define MII_ANLPAR 5 // Auto_negotiation Link Partner Ability Register
+#define MII_ANER 6 // Auto-negotiation Expansion Register
+#define MII_DSCR 16 // Specified Configuration Register
+#define MII_DSCSR 17 // Specified Configuration and Status Register
+#define MII_10BTCSR 18 // 10BASE-T Configuration and Satus Register
+#define MII_PWDOR 19 // Power Down Control Register
+#define MII_CONFIGR 20 // Specified config Register
+#define MII_MDINTR 21 // Specified Interrupt Register
+#define MII_RECR 22 // Specified Receive Error Counter Register
+#define MII_DISCR 23 // Specified Disconnect Counter Register
+#define MII_RLSR 24 // Hardware Reset Latch State Register
+
+// Basic Mode Control Register (BMCR)
+// Bit definitions: MII_BMCR
+#define MII_RESET (1 << 15) // 1= Software Reset; 0=Normal Operation
+#define MII_LOOPBACK (1 << 14) // 1=loopback Enabled; 0=Normal Operation
+#define MII_SPEED_SELECT (1 << 13) // 1=100Mbps; 0=10Mbps
+#define MII_AUTONEG (1 << 12) // Auto-negotiation Enable
+#define MII_POWER_DOWN (1 << 11) // 1=Power down 0=Normal operation
+#define MII_ISOLATE (1 << 10) // 1 = Isolates 0 = Normal operation
+#define MII_RESTART_AUTONEG (1 << 9) // 1 = Restart auto-negotiation 0 = Normal operation
+#define MII_DUPLEX_MODE (1 << 8) // 1 = Full duplex operation 0 = Normal operation
+#define MII_COLLISION_TEST (1 << 7) // 1 = Collision test enabled 0 = Normal operation
+// Reserved 6 to 0 // Read as 0, ignore on write
+
+// Basic Mode Status Register (BMSR)
+// Bit definitions: MII_BMSR
+#define MII_100BASE_T4 (1 << 15) // 100BASE-T4 Capable
+#define MII_100BASE_TX_FD (1 << 14) // 100BASE-TX Full Duplex Capable
+#define MII_100BASE_T4_HD (1 << 13) // 100BASE-TX Half Duplex Capable
+#define MII_10BASE_T_FD (1 << 12) // 10BASE-T Full Duplex Capable
+#define MII_10BASE_T_HD (1 << 11) // 10BASE-T Half Duplex Capable
+// Reserved 10 to 7 // Read as 0, ignore on write
+#define MII_MF_PREAMB_SUPPR (1 << 6) // MII Frame Preamble Suppression
+#define MII_AUTONEG_COMP (1 << 5) // Auto-negotiation Complete
+#define MII_REMOTE_FAULT (1 << 4) // Remote Fault
+#define MII_AUTONEG_ABILITY (1 << 3) // Auto Configuration Ability
+#define MII_LINK_STATUS (1 << 2) // Link Status
+#define MII_JABBER_DETECT (1 << 1) // Jabber Detect
+#define MII_EXTEND_CAPAB (1 << 0) // Extended Capability
+
+// PHY ID Identifier Register
+// definitions: MII_PHYID1
+#define MII_LSB_MASK 0x3F
+
+#if defined(BOARD_EMAC_PHY_COMP_DM9161)
+#define MII_OUI_MSB 0x0181
+#define MII_OUI_LSB 0x2E
+//#define MII_PHYID1_OUI 0x606E // OUI: Organizationally Unique Identifier
+//#define MII_ID 0x0181b8a0
+#elif defined(BOARD_EMAC_PHY_COMP_LAN8700)
+#define MII_OUI_MSB 0x0007
+#define MII_OUI_LSB 0x30
+#else
+#error no PHY Ethernet component defined !
+#endif
+
+// Auto-negotiation Advertisement Register (ANAR)
+// Auto-negotiation Link Partner Ability Register (ANLPAR)
+// Bit definitions: MII_ANAR, MII_ANLPAR
+#define MII_NP (1 << 15) // Next page Indication
+#define MII_ACK (1 << 14) // Acknowledge
+#define MII_RF (1 << 13) // Remote Fault
+// Reserved 12 to 11 // Write as 0, ignore on read
+#define MII_FCS (1 << 10) // Flow Control Support
+#define MII_T4 (1 << 9) // 100BASE-T4 Support
+#define MII_TX_FDX (1 << 8) // 100BASE-TX Full Duplex Support
+#define MII_TX_HDX (1 << 7) // 100BASE-TX Support
+#define MII_10_FDX (1 << 6) // 10BASE-T Full Duplex Support
+#define MII_10_HDX (1 << 5) // 10BASE-T Support
+// Selector 4 to 0 // Protocol Selection Bits
+#define MII_AN_IEEE_802_3 0x0001
+
+// Auto-negotiation Expansion Register (ANER)
+// Bit definitions: MII_ANER
+// Reserved 15 to 5 // Read as 0, ignore on write
+#define MII_PDF (1 << 4) // Local Device Parallel Detection Fault
+#define MII_LP_NP_ABLE (1 << 3) // Link Partner Next Page Able
+#define MII_NP_ABLE (1 << 2) // Local Device Next Page Able
+#define MII_PAGE_RX (1 << 1) // New Page Received
+#define MII_LP_AN_ABLE (1 << 0) // Link Partner Auto-negotiation Able
+
+// Specified Configuration Register (DSCR)
+// Bit definitions: MII_DSCR
+#define MII_BP4B5B (1 << 15) // Bypass 4B5B Encoding and 5B4B Decoding
+#define MII_BP_SCR (1 << 14) // Bypass Scrambler/Descrambler Function
+#define MII_BP_ALIGN (1 << 13) // Bypass Symbol Alignment Function
+#define MII_BP_ADPOK (1 << 12) // BYPASS ADPOK
+#define MII_REPEATER (1 << 11) // Repeater/Node Mode
+#define MII_TX (1 << 10) // 100BASE-TX Mode Control
+#define MII_FEF (1 << 9) // Far end Fault enable
+#define MII_RMII_ENABLE (1 << 8) // Reduced MII Enable
+#define MII_F_LINK_100 (1 << 7) // Force Good Link in 100Mbps
+#define MII_SPLED_CTL (1 << 6) // Speed LED Disable
+#define MII_COLLED_CTL (1 << 5) // Collision LED Enable
+#define MII_RPDCTR_EN (1 << 4) // Reduced Power Down Control Enable
+#define MII_SM_RST (1 << 3) // Reset State Machine
+#define MII_MFP_SC (1 << 2) // MF Preamble Suppression Control
+#define MII_SLEEP (1 << 1) // Sleep Mode
+#define MII_RLOUT (1 << 0) // Remote Loopout Control
+
+// Specified Configuration and Status Register (DSCSR)
+// Bit definitions: MII_DSCSR
+#define MII_100FDX (1 << 15) // 100M Full Duplex Operation Mode
+#define MII_100HDX (1 << 14) // 100M Half Duplex Operation Mode
+#define MII_10FDX (1 << 13) // 10M Full Duplex Operation Mode
+#define MII_10HDX (1 << 12) // 10M Half Duplex Operation Mode
+
+// 10BASE-T Configuration/Status (10BTCSR)
+// Bit definitions: MII_10BTCSR
+// Reserved 18 to 15 // Read as 0, ignore on write
+#define MII_LP_EN (1 << 14) // Link Pulse Enable
+#define MII_HBE (1 << 13) // Heartbeat Enable
+#define MII_SQUELCH (1 << 12) // Squelch Enable
+#define MII_JABEN (1 << 11) // Jabber Enable
+#define MII_10BT_SER (1 << 10) // 10BASE-T GPSI Mode
+// Reserved 9 to 1 // Read as 0, ignore on write
+#define MII_POLR (1 << 0) // Polarity Reversed
+
+// Specified Interrupt Register
+// Bit definitions: MII_MDINTR
+#define MII_INTR_PEND (1 << 15) // Interrupt Pending
+// Reserved 14 to 12 // Reserved
+#define MII_FDX_MASK (1 << 11) // Full-duplex Interrupt Mask
+#define MII_SPD_MASK (1 << 10) // Speed Interrupt Mask
+#define MII_LINK_MASK (1 << 9) // Link Interrupt Mask
+#define MII_INTR_MASK (1 << 8) // Master Interrupt Mask
+// Reserved 7 to 5 // Reserved
+#define MII_FDX_CHANGE (1 << 4) // Duplex Status Change Interrupt
+#define MII_SPD_CHANGE (1 << 3) // Speed Status Change Interrupt
+#define MII_LINK_CHANGE (1 << 2) // Link Status Change Interrupt
+// Reserved 1 // Reserved
+#define MII_INTR_STATUS (1 << 0) // Interrupt Status
+
+#endif // #ifndef _MII_DEFINE_H
+
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