diff options
| author | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-07-04 14:56:03 +0000 |
|---|---|---|
| committer | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-07-04 14:56:03 +0000 |
| commit | 8aaa856c2e79a0da0c7b92fd172e5b2c56ee477e (patch) | |
| tree | 42419e3d13a315fc6152d46fa6320d1856b5a23d | |
| parent | f1202753ecf6ff301f36f14f7fce5e345d4eb142 (diff) | |
commit lots of cleanup
git-svn-id: https://svn.openpcd.org:2342/trunk@5 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
21 files changed, 2500 insertions, 193 deletions
diff --git a/openpcd/firmware/compil/SrcIAR/Board.h b/openpcd/firmware/compil/SrcIAR/Board.h new file mode 100644 index 0000000..95e15e0 --- /dev/null +++ b/openpcd/firmware/compil/SrcIAR/Board.h @@ -0,0 +1,89 @@ +/*----------------------------------------------------------------------------
+* ATMEL Microcontroller Software Support - ROUSSET -
+*----------------------------------------------------------------------------
+* The software is delivered "AS IS" without warranty or condition of any
+* kind, either express, implied or statutory. This includes without
+* limitation any warranty or condition with respect to merchantability or
+* fitness for any particular purpose, or against the infringements of
+* intellectual property rights of others.
+*----------------------------------------------------------------------------
+* File Name : Board.h
+* Object : AT91SAM7S Evaluation Board Features Definition File.
+*
+* Creation : JPP 16/Jun/2004
+*----------------------------------------------------------------------------
+*/
+#ifndef Board_h
+#define Board_h
+
+#include "include/AT91SAM7S64.h"
+#define __inline inline
+#include "include/lib_AT91SAM7S64.h"
+
+#define true -1
+#define false 0
+
+/*-------------------------------*/
+/* SAM7Board Memories Definition */
+/*-------------------------------*/
+// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
+
+#define INT_SARM 0x00200000
+#define INT_SARM_REMAP 0x00000000
+
+#define INT_FLASH 0x00000000
+#define INT_FLASH_REMAP 0x01000000
+
+#define FLASH_PAGE_NB 512
+#define FLASH_PAGE_SIZE 128
+
+/*-----------------*/
+/* Leds Definition */
+/*-----------------*/
+/* PIO Flash PA PB PIN */
+#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */
+#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */
+#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */
+#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */
+#define NB_LEB 4
+
+#define LED_MASK (LED1|LED2|LED3|LED4)
+
+/*-------------------------*/
+/* Push Buttons Definition */
+/*-------------------------*/
+/* PIO Flash PA PB PIN */
+#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */
+#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */
+#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */
+#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */
+#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
+
+
+#define SW1 (1<<19) // PA19
+#define SW2 (1<<20) // PA20
+#define SW3 (1<<15) // PA15
+#define SW4 (1<<14) // PA14
+
+/*------------------*/
+/* USART Definition */
+/*------------------*/
+/* SUB-D 9 points J3 DBGU*/
+#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
+#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
+#define AT91C_DBGU_BAUD 115200 // Baud rate
+
+#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
+#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
+#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
+#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
+
+/*--------------*/
+/* Master Clock */
+/*--------------*/
+
+#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
+#define MCK 47923200 // MCK (PLLRC div by 2)
+#define MCKKHz (MCK/1000) //
+
+#endif /* Board_h */
diff --git a/openpcd/firmware/compil/SrcIAR/Cstartup.s79 b/openpcd/firmware/compil/SrcIAR/Cstartup.s79 new file mode 100644 index 0000000..18236de --- /dev/null +++ b/openpcd/firmware/compil/SrcIAR/Cstartup.s79 @@ -0,0 +1,281 @@ +;------------------------------------------------------------------------------
+;- ATMEL Microcontroller Software Support - ROUSSET -
+;------------------------------------------------------------------------------
+; The software is delivered "AS IS" without warranty or condition of any
+; kind, either express, implied or statutory. This includes without
+; limitation any warranty or condition with respect to merchantability or
+; fitness for any particular purpose, or against the infringements of
+; intellectual property rights of others.
+;-----------------------------------------------------------------------------
+;- File source : Cstartup.s79
+;- Object : Generic CStartup for IAR No Use REMAP
+;- Compilation flag : None
+;-
+;- 1.0 15/Jun/04 JPP : Creation
+;- 1.1 01/Apr/05 JPP : save SPSR
+;------------------------------------------------------------------------------
+
+#include "AT91SAM7S64_inc.h"
+
+;------------------------------------------------------------------------------
+;- Area Definition
+;------------------------------------------------------------------------------
+
+;---------------------------------------------------------------
+; ?RESET
+; Reset Vector.
+; Normally, segment INTVEC is linked at address 0.
+; For debugging purposes, INTVEC may be placed at other
+; addresses.
+; A debugger that honors the entry point will start the
+; program in a normal way even if INTVEC is not at address 0.
+;-------------------------------------------------------------
+
+ PROGRAM ?RESET
+ RSEG INTRAMSTART_REMAP
+ RSEG INTRAMEND_REMAP
+
+ RSEG ICODE:CODE:ROOT(2)
+ CODE32 ; Always ARM mode after reset
+ org 0
+reset
+;------------------------------------------------------------------------------
+;- Exception vectors
+;--------------------
+;- These vectors can be read at address 0 or at RAM address
+;- They ABSOLUTELY requires to be in relative addresssing mode in order to
+;- guarantee a valid jump. For the moment, all are just looping.
+;- If an exception occurs before remap, this would result in an infinite loop.
+;- To ensure if a exeption occurs before start application to infinite loop.
+;------------------------------------------------------------------------------
+
+ B InitReset ; 0x00 Reset handler
+undefvec:
+ B undefvec ; 0x04 Undefined Instruction
+swivec:
+ B swivec ; 0x08 Software Interrupt
+pabtvec:
+ B pabtvec ; 0x0C Prefetch Abort
+dabtvec:
+ B dabtvec ; 0x10 Data Abort
+rsvdvec:
+ B rsvdvec ; 0x14 reserved
+irqvec:
+ B IRQ_Handler_Entry ; 0x18 IRQ
+fiqvec: ; 0x1c FIQ
+;------------------------------------------------------------------------------
+;- Function : FIQ_Handler_Entry
+;- Treatments : FIQ Controller Interrupt Handler.
+;- Called Functions : AIC_FVR[interrupt]
+;------------------------------------------------------------------------------
+
+FIQ_Handler_Entry:
+
+;- Switch in SVC/User Mode to allow User Stack access for C code
+; because the FIQ is not yet acknowledged
+
+;- Save and r0 in FIQ_Register
+ mov r9,r0
+ ldr r0 , [r8, #AIC_FVR]
+ msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
+;- Save scratch/used registers and LR in User Stack
+ stmfd sp!, { r1-r3, r12, lr}
+
+;- Branch to the routine pointed by the AIC_FVR
+ mov r14, pc
+ bx r0
+
+;- Restore scratch/used registers and LR from User Stack
+ ldmia sp!, { r1-r3, r12, lr}
+
+;- Leave Interrupts disabled and switch back in FIQ mode
+ msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
+
+;- Restore the R0 ARM_MODE_SVC register
+ mov r0,r9
+
+;- Restore the Program Counter using the LR_fiq directly in the PC
+ subs pc,lr,#4
+
+
+InitReset:
+;------------------------------------------------------------------------------
+;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
+;------------------------------------------------------------------------------
+ EXTERN AT91F_LowLevelInit
+
+#define __iramend SFB(INTRAMEND_REMAP)
+
+;- minumum C initialization
+;- call AT91F_LowLevelInit( void)
+
+ ldr r13,=__iramend ; temporary stack in internal RAM
+;--Call Low level init function in ABSOLUTE through the Interworking
+ ldr r0,=AT91F_LowLevelInit
+ mov lr, pc
+ bx r0
+
+;------------------------------------------------------------------------------
+;- Stack Sizes Definition
+;------------------------
+;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
+;- the vectoring. This assume that the IRQ management.
+;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
+;- Fast Interrupt not requires stack If in your application it required you must
+;- be definehere.
+;- The System stack size is not defined and is limited by the free internal
+;- SRAM.
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;- Top of Stack Definition
+;-------------------------
+;- Interrupt and Supervisor Stack are located at the top of internal memory in
+;- order to speed the exception handling context saving and restoring.
+;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
+;------------------------------------------------------------------------------
+
+IRQ_STACK_SIZE EQU (3*8*4) ; 3 words per interrupt priority level
+
+ARM_MODE_FIQ EQU 0x11
+ARM_MODE_IRQ EQU 0x12
+ARM_MODE_SVC EQU 0x13
+
+I_BIT EQU 0x80
+F_BIT EQU 0x40
+
+;------------------------------------------------------------------------------
+;- Setup the stack for each mode
+;-------------------------------
+ ldr r0, =__iramend
+
+;- Set up Fast Interrupt Mode and set FIQ Mode Stack
+ msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
+;- Init the FIQ register
+ ldr r8, =AT91C_BASE_AIC
+
+;- Set up Interrupt Mode and set IRQ Mode Stack
+ msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
+ mov r13, r0 ; Init stack IRQ
+ sub r0, r0, #IRQ_STACK_SIZE
+
+;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
+ msr CPSR_c, #ARM_MODE_SVC
+ mov r13, r0
+
+
+;---------------------------------------------------------------
+; ?CSTARTUP
+;---------------------------------------------------------------
+ EXTERN __segment_init
+ EXTERN main
+; Initialize segments.
+; __segment_init is assumed to use
+; instruction set and to be reachable by BL from the ICODE segment
+; (it is safest to link them in segment ICODE).
+ ldr r0,=__segment_init
+ mov lr, pc
+ bx r0
+
+ PUBLIC __main
+?jump_to_main:
+ ldr lr,=?call_exit
+ ldr r0,=main
+__main:
+ bx r0
+
+;------------------------------------------------------------------------------
+;- Loop for ever
+;---------------
+;- End of application. Normally, never occur.
+;- Could jump on Software Reset ( B 0x0 ).
+;------------------------------------------------------------------------------
+?call_exit:
+End
+ b End
+
+
+;------------------------------------------------------------------------------
+;- Manage exception
+;---------------
+;- This module The exception must be ensure in ARM mode
+;------------------------------------------------------------------------------
+;------------------------------------------------------------------------------
+;- Function : IRQ_Handler_Entry
+;- Treatments : IRQ Controller Interrupt Handler.
+;- Called Functions : AIC_IVR[interrupt]
+;------------------------------------------------------------------------------
+IRQ_Handler_Entry:
+
+;- Manage Exception Entry
+;- Adjust and save LR_irq in IRQ stack
+ sub lr, lr, #4
+ stmfd sp!, {lr}
+
+;- Save SPSR need to be saved for nested interrupt
+ mrs r14, SPSR
+ stmfd sp!, {r14}
+
+;- Save and r0 in IRQ stack
+ stmfd sp!, {r0}
+
+;- Write in the IVR to support Protect Mode
+;- No effect in Normal Mode
+;- De-assert the NIRQ and clear the source in Protect Mode
+ ldr r14, =AT91C_BASE_AIC
+ ldr r0 , [r14, #AIC_IVR]
+ str r14, [r14, #AIC_IVR]
+
+;- Enable Interrupt and Switch in Supervisor Mode
+ msr CPSR_c, #ARM_MODE_SVC
+
+;- Save scratch/used registers and LR in User Stack
+ stmfd sp!, { r1-r3, r12, r14}
+
+;- Branch to the routine pointed by the AIC_IVR
+ mov r14, pc
+ bx r0
+
+;- Restore scratch/used registers and LR from User Stack
+ ldmia sp!, { r1-r3, r12, r14}
+
+;- Disable Interrupt and switch back in IRQ mode
+ msr CPSR_c, #I_BIT | ARM_MODE_IRQ
+
+;- Mark the End of Interrupt on the AIC
+ ldr r14, =AT91C_BASE_AIC
+ str r14, [r14, #AIC_EOICR]
+
+;- Restore R0
+ ldmia sp!, {r0}
+
+;- Restore SPSR_irq and r0 from IRQ stack
+ ldmia sp!, {r14}
+ msr SPSR_cxsf, r14
+
+;- Restore adjusted LR_irq from IRQ stack directly in the PC
+ ldmia sp!, {pc}^
+
+;---------------------------------------------------------------
+; ?EXEPTION_VECTOR
+; This module is only linked if needed for closing files.
+;---------------------------------------------------------------
+ PUBLIC AT91F_Default_FIQ_handler
+ PUBLIC AT91F_Default_IRQ_handler
+ PUBLIC AT91F_Spurious_handler
+
+ CODE32 ; Always ARM mode after exeption
+
+AT91F_Default_FIQ_handler
+ b AT91F_Default_FIQ_handler
+
+AT91F_Default_IRQ_handler
+ b AT91F_Default_IRQ_handler
+
+AT91F_Spurious_handler
+ b AT91F_Spurious_handler
+
+ ENDMOD
+
+ END
+
diff --git a/openpcd/firmware/compil/SrcIAR/Cstartup_SAM7.c b/openpcd/firmware/compil/SrcIAR/Cstartup_SAM7.c new file mode 100644 index 0000000..a000b03 --- /dev/null +++ b/openpcd/firmware/compil/SrcIAR/Cstartup_SAM7.c @@ -0,0 +1,85 @@ +//*----------------------------------------------------------------------------
+//* ATMEL Microcontroller Software Support - ROUSSET -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name : Cstartup_SAM7.c
+//* Object : Low level initializations written in C for Tools
+//* Creation : 12/Jun/04
+//* 1.2 28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL
+//* 1.3 21/Mar/05 JPP : Change PLL Wait time
+//* 1.4 21/Aug/05 JPP : Change MC_FMR Setting
+//* 1.5 29/Aug/05 JPP : Change PLL error
+//*----------------------------------------------------------------------------
+
+// Include the board file description
+#include "Board.h"
+
+// The following functions must be write in ARM mode this function called directly
+// by exception vector
+extern void AT91F_Spurious_handler(void);
+extern void AT91F_Default_IRQ_handler(void);
+extern void AT91F_Default_FIQ_handler(void);
+
+//*----------------------------------------------------------------------------
+//* \fn AT91F_LowLevelInit
+//* \brief This function performs very low level HW initialization
+//* this function can be use a Stack, depending the compilation
+//* optimization mode
+//*----------------------------------------------------------------------------
+void AT91F_LowLevelInit( void)
+{
+ int i;
+ AT91PS_PMC pPMC = AT91C_BASE_PMC;
+ //* Set Flash Waite sate
+ // Single Cycle Access at Up to 30 MHz, or 40
+ AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS ;
+
+ //* Watchdog Disable
+ AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+
+ //* Set MCK at 47 923 200
+ // 1 Enabling the Main Oscillator:
+ // SCK = 1/32768 = 30.51 uSecond
+ // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
+ pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
+ // Wait the startup time
+ while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
+ // 2 Checking the Main Oscillator Frequency (Optional)
+ // 3 Setting PLL and divider:
+ // - div by 14 Fin = 1.3165 =(18,432 / 14)
+ // - Mul 72+1: Fout = 96.1097 =(3,6864 *73)
+ // for 96 MHz the erroe is 0.11%
+ // Field out NOT USED = 0
+ // PLLCOUNT pll startup time estimate at : 0.844 ms
+ // PLLCOUNT 28 = 0.000844 /(1/32768)
+ pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14 ) |
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+ (AT91C_CKGR_MUL & (72<<16)));
+
+
+ // Wait the startup time
+ while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+ // 4. Selection of Master Clock and Processor Clock
+ // select the PLL clock divided by 2
+ pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+ pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+ while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
+
+ // Set up the default interrupts handler vectors
+ AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
+ for (i=1;i < 31; i++)
+ {
+ AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
+ }
+ AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
+
+}
+
diff --git a/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-RAM.ld b/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-RAM.ld new file mode 100644 index 0000000..2b6ba81 --- /dev/null +++ b/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-RAM.ld @@ -0,0 +1,146 @@ +/*---------------------------------------------------------------------------*/ +/*- ATMEL Microcontroller Software Support - ROUSSET - */ +/*---------------------------------------------------------------------------*/ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/*---------------------------------------------------------------------------*/ +/*- File source : GCC_RAM.ld */ +/*- Object : Linker Script File for RAM Workspace */ +/*- Compilation flag : None */ +/*- */ +/*- 1.0 20/Oct/04 JPP : Creation */ +/*---------------------------------------------------------------------------*/ + + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +/* +// <h> Memory Configuration +// <h> Code (Read Only) +// <o> Start <0x0-0xFFFFFFFF> +// <o1> Size <0x0-0xFFFFFFFF> +// </h> +// <h> Data (Read/Write) +// <o2> Start <0x0-0xFFFFFFFF> +// <o3> Size <0x0-0xFFFFFFFF> +// </h> +// <h> Top of Stack (Read/Write) +// <o4> STACK <0x0-0xFFFFFFFF> +// </h> +// </h> +*/ + +/* Memory Definitions */ + +MEMORY +{ + CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x00003000 + DATA (rw) : ORIGIN = 0x00003000, LENGTH = 0x00001000 + STACK (rw) : ORIGIN = 0x00004000,LENGTH = 0x00000000 +} + + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + . = 0x0000000; + .text : { *cstartup.o (.text) }>CODE =0 + .text : + { + *(.text) /* remaining code */ + + *(.glue_7t) *(.glue_7) + + } >CODE =0 + + . = ALIGN(4); + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata) + } >CODE + + . = ALIGN(4); + + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + _data = . ; + *(.data) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + _edata = . ; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = . ; + __bss_start__ = . ; + *(.bss) + *(COMMON) + } + . = ALIGN(4); + __bss_end__ = . ; + __bss_end__ = . ; + _end = .; + . = ALIGN(4); + .int_data : + { + *(.internal_ram_top) + }> STACK + + PROVIDE (end = .); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + +} diff --git a/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-ROM.ld b/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-ROM.ld new file mode 100644 index 0000000..10d89a9 --- /dev/null +++ b/openpcd/firmware/compil/SrcWinARM/AT91SAM7S64-ROM.ld @@ -0,0 +1,148 @@ +/*---------------------------------------------------------------------------*/ +/*- ATMEL Microcontroller Software Support - ROUSSET - */ +/*---------------------------------------------------------------------------*/ +/* The software is delivered "AS IS" without warranty or condition of any */ +/* kind, either express, implied or statutory. This includes without */ +/* limitation any warranty or condition with respect to merchantability or */ +/* fitness for any particular purpose, or against the infringements of */ +/* intellectual property rights of others. */ +/*---------------------------------------------------------------------------*/ +/*- File source : GCC_FLASH.ld */ +/*- Object : Linker Script File for Flash Workspace */ +/*- Compilation flag : None */ +/*- */ +/*- 1.0 20/Oct/04 JPP : Creation */ +/*---------------------------------------------------------------------------*/ + +/* slightly modified for the WinARM example - M.Thomas (not Atmel) */ + +/* +//*** <<< Use Configuration Wizard in Context Menu >>> *** +*/ + + +/* +// <h> Memory Configuration +// <h> Code (Read Only) +// <o> Start <0x0-0xFFFFFFFF> +// <o1> Size <0x0-0xFFFFFFFF> +// </h> +// <h> Data (Read/Write) +// <o2> Start <0x0-0xFFFFFFFF> +// <o3> Size <0x0-0xFFFFFFFF> +// </h> +// <h> Top of Stack (Read/Write) +// <o4> STACK <0x0-0xFFFFFFFF> +// </h> +// </h> +*/ + +/* Memory Definitions */ + +/* mt change code origin from 0x00000000 */ +MEMORY +{ + CODE (rx) : ORIGIN = 0x00100000, LENGTH = 0x00010000 + DATA (rw) : ORIGIN = 0x00200000, LENGTH = 0x00004000 + STACK (rw) : ORIGIN = 0x00204000,LENGTH = 0x00000000 +} + + +/* Section Definitions */ + +SECTIONS +{ + /* first section is .text which is used for code */ + . = 0x0000000; + .text : { *cstartup.o (.text) }>CODE =0 + .text : + { + *(.text) /* remaining code */ + + *(.glue_7t) *(.glue_7) + + } >CODE =0 + + . = ALIGN(4); + + /* .rodata section which is used for read-only data (constants) */ + + .rodata : + { + *(.rodata) + } >CODE + + . = ALIGN(4); + + _etext = . ; + PROVIDE (etext = .); + + /* .data section which is used for initialized data */ + + .data : AT (_etext) + { + _data = . ; + *(.data) + SORT(CONSTRUCTORS) + } >DATA + . = ALIGN(4); + + _edata = . ; + PROVIDE (edata = .); + + /* .bss section which is used for uninitialized data */ + + .bss : + { + __bss_start = . ; + __bss_start__ = . ; + *(.bss) + *(COMMON) + } + . = ALIGN(4); + __bss_end__ = . ; + __bss_end__ = . ; + _end = .; + . = ALIGN(4); + .int_data : + { + *(.internal_ram_top) + }> STACK + + PROVIDE (end = .); + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + +} diff --git a/openpcd/firmware/compil/SrcWinARM/Board.h b/openpcd/firmware/compil/SrcWinARM/Board.h new file mode 100644 index 0000000..45e752f --- /dev/null +++ b/openpcd/firmware/compil/SrcWinARM/Board.h @@ -0,0 +1,88 @@ +/*---------------------------------------------------------------------------- +* ATMEL Microcontroller Software Support - ROUSSET - +*---------------------------------------------------------------------------- +* The software is delivered "AS IS" without warranty or condition of any +* kind, either express, implied or statutory. This includes without +* limitation any warranty or condition with respect to merchantability or +* fitness for any particular purpose, or against the infringements of +* intellectual property rights of others. +*---------------------------------------------------------------------------- +* File Name : Board.h +* Object : AT91SAM7S Evaluation Board Features Definition File. +* +* Creation : JPP 16/Jun/2004 +*---------------------------------------------------------------------------- +*/ +#ifndef Board_h +#define Board_h + +#include <include/AT91SAM7S64.h> +#define __inline static inline +#include <include/lib_AT91SAM7S64.h> + +#define true -1 +#define false 0 + +/*-------------------------------*/ +/* SAM7Board Memories Definition */ +/*-------------------------------*/ +// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash + +#define INT_SARM 0x00200000 +#define INT_SARM_REMAP 0x00000000 + +#define INT_FLASH 0x00000000 +#define INT_FLASH_REMAP 0x01000000 + +#define FLASH_PAGE_NB 512 +#define FLASH_PAGE_SIZE 128 + +/*-----------------*/ +/* Leds Definition */ +/*-----------------*/ +/* PIO Flash PA PB PIN */ +#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */ +#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */ +#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */ +#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */ +#define NB_LEB 4 + +#define LED_MASK (LED1|LED2|LED3|LED4) + +/*-------------------------*/ +/* Push Buttons Definition */ +/*-------------------------*/ +/* PIO Flash PA PB PIN */ +#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */ +#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */ +#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */ +#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */ +#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK) + +#define SW1 (1<<19) // PA19 +#define SW2 (1<<20) // PA20 +#define SW3 (1<<15) // PA15 +#define SW4 (1<<14) // PA14 + +/*------------------*/ +/* USART Definition */ +/*------------------*/ +/* SUB-D 9 points J3 DBGU*/ +#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */ +#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */ +#define AT91C_DBGU_BAUD 115200 // Baud rate + +#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */ +#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */ +#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */ +#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */ + +/*--------------*/ +/* Master Clock */ +/*--------------*/ + +#define EXT_OC 18432000 // Exetrnal ocilator MAINCK +#define MCK 47923200 // MCK (PLLRC div by 2) +#define MCKKHz (MCK/1000) // + +#endif /* Board_h */ diff --git a/openpcd/firmware/compil/SrcWinARM/Cstartup.S b/openpcd/firmware/compil/SrcWinARM/Cstartup.S new file mode 100644 index 0000000..d13dbd8 --- /dev/null +++ b/openpcd/firmware/compil/SrcWinARM/Cstartup.S @@ -0,0 +1,298 @@ +/*------------------------------------------------------------------------------ +//*- ATMEL Microcontroller Software Support - ROUSSET - +//*------------------------------------------------------------------------------ +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*----------------------------------------------------------------------------- +//*- File source : Cstartup.s +//*- Object : Generic CStartup for KEIL and GCC No Use REMAP +//*- Compilation flag : None +//*- +//*- 1.0 18/Oct/04 JPP : Creation +//*- 1.1 21/Feb/05 JPP : Set Interrupt +//*- 1.1 01/Apr/05 JPP : save SPSR +//*-----------------------------------------------------------------------------*/ + + .equ IRQ_Stack_Size, 0x00000060 + +/* #include "AT91SAM7S64_inc.h" */ + + .equ AIC_IVR, (256) + .equ AIC_FVR, (260) + .equ AIC_EOICR, (304) + .equ AT91C_BASE_AIC, (0xFFFFF000) + +#;------------------------------------------------------------------------------ +#;- Section Definition +#;----------------- +#;- Section +#;- .internal_ram_top Top_Stack: used by the cstartup for vector initalisation +#;- management defined by ld and affect from ldscript +#;------------------------------------------------------------------------------ + .section .internal_ram_top + .code 32 + .align 0 + .global Top_Stack +Top_Stack: + +/*------------------------------------------------------------------------------ +*- Area Definition +*------------------------------------------------------------------------------ +* .text is used instead of .section .text so it works with arm-aout too. */ + .section .reset + .text + .global _startup + .func _startup +_startup: +reset: +/*------------------------------------------------------------------------------ +//*- Exception vectors +//*-------------------- +//*- These vectors can be read at address 0 or at RAM address +//*- They ABSOLUTELY requires to be in relative addresssing mode in order to +//*- guarantee a valid jump. For the moment, all are just looping. +//*- If an exception occurs before remap, this would result in an infinite loop. +//*- To ensure if a exeption occurs before start application to infinite loop. +//*------------------------------------------------------------------------------*/ + + B InitReset /* 0x00 Reset handler */ +undefvec: + B undefvec /* 0x04 Undefined Instruction */ +swivec: + B swivec /* 0x08 Software Interrupt */ +pabtvec: + B pabtvec /* 0x0C Prefetch Abort */ +dabtvec: + B dabtvec /* 0x10 Data Abort */ +rsvdvec: + B rsvdvec /* 0x14 reserved */ +irqvec: + B IRQ_Handler_Entry /* 0x18 IRQ */ +fiqvec: /* 0x1c FIQ */ +/*------------------------------------------------------------------------------ +//*- Function : FIQ_Handler_Entry +//*- Treatments : FIQ Controller Interrupt Handler. +//*- Called Functions : AIC_FVR[interrupt] +//*------------------------------------------------------------------------------*/ + +FIQ_Handler_Entry: + +/*- Switch in SVC/User Mode to allow User Stack access for C code */ +/* because the FIQ is not yet acknowledged*/ + +/*- Save and r0 in FIQ_Register */ + mov r9,r0 + ldr r0 , [r8, #AIC_FVR] + msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC + +/*- Save scratch/used registers and LR in User Stack */ + stmfd sp!, { r1-r3, r12, lr} + +/*- Branch to the routine pointed by the AIC_FVR */ + mov r14, pc + bx r0 + +/*- Restore scratch/used registers and LR from User Stack */ + ldmia sp!, { r1-r3, r12, lr} + +/*- Leave Interrupts disabled and switch back in FIQ mode */ + msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ + +/*- Restore the R0 ARM_MODE_SVC register */ + mov r0,r9 + +/*- Restore the Program Counter using the LR_fiq directly in the PC */ + subs pc,lr,#4 + .align 0 +.RAM_TOP: + .word Top_Stack + +InitReset: +/*------------------------------------------------------------------------------ +/*- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit +/*------------------------------------------------------------------------------*/ + .extern AT91F_LowLevelInit +/*- minumum C initialization */ +/*- call AT91F_LowLevelInit( void) */ + + ldr r13,.RAM_TOP /* temporary stack in internal RAM */ +/*--Call Low level init function in ABSOLUTE through the Interworking */ + ldr r0,=AT91F_LowLevelInit + mov lr, pc + bx r0 +/*------------------------------------------------------------------------------ +//*- Stack Sizes Definition +//*------------------------ +//*- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using +//*- the vectoring. This assume that the IRQ management. +//*- The Interrupt Stack must be adjusted depending on the interrupt handlers. +//*- Fast Interrupt not requires stack If in your application it required you must +//*- be definehere. +//*- The System stack size is not defined and is limited by the free internal +//*- SRAM. +//*------------------------------------------------------------------------------*/ + +/*------------------------------------------------------------------------------ +//*- Top of Stack Definition +//*------------------------- +//*- Interrupt and Supervisor Stack are located at the top of internal memory in +//*- order to speed the exception handling context saving and restoring. +//*- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory. +//*------------------------------------------------------------------------------*/ + + .EQU IRQ_STACK_SIZE, (3*8*4) + .EQU ARM_MODE_FIQ, 0x11 + .EQU ARM_MODE_IRQ, 0x12 + .EQU ARM_MODE_SVC, 0x13 + + .EQU I_BIT, 0x80 + .EQU F_BIT, 0x40 + +/*------------------------------------------------------------------------------ +//*- Setup the stack for each mode +//*-------------------------------*/ + mov r0,r13 + +/*- Set up Fast Interrupt Mode and set FIQ Mode Stack*/ + msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT +/*- Init the FIQ register*/ + ldr r8, =AT91C_BASE_AIC + +/*- Set up Interrupt Mode and set IRQ Mode Stack*/ + msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT + mov r13, r0 /* Init stack IRQ */ + sub r0, r0, #IRQ_Stack_Size +/*- Set up Supervisor Mode and set Supervisor Mode Stack*/ + msr CPSR_c, #ARM_MODE_SVC + mov r13, r0 /* Init stack Sup */ + +/*- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack*/ + +# Relocate .data section (Copy from ROM to RAM) + LDR R1, =_etext + LDR R2, =_data + LDR R3, =_edata +LoopRel: CMP R2, R3 + LDRLO R0, [R1], #4 + STRLO R0, [R2], #4 + BLO LoopRel + +# Clear .bss section (Zero init) + MOV R0, #0 + LDR R1, =__bss_start__ + LDR R2, =__bss_end__ +LoopZI: CMP R1, R2 + STRLO R0, [R1], #4 + BLO LoopZI + + ldr lr,=exit + ldr r0,=main + bx r0 + + .size _startup, . - _startup + .endfunc + +/* "exit" dummy added by mthomas to avoid sbrk write read etc. needed + by the newlib default "exit" */ + .global exit + .func exit +exit: + b . + .size exit, . - exit + .endfunc + +/*------------------------------------------------------------------------------ +//*- Manage exception +//*--------------- +//*- This module The exception must be ensure in ARM mode +//*------------------------------------------------------------------------------ +//*------------------------------------------------------------------------------ +//*- Function : IRQ_Handler_Entry +//*- Treatments : IRQ Controller Interrupt Handler. +//*- Called Functions : AIC_IVR[interrupt] +//*------------------------------------------------------------------------------*/ + .global IRQ_Handler_Entry + .func IRQ_Handler_Entry + +IRQ_Handler_Entry: + +/*- Manage Exception Entry */ +/*- Adjust and save LR_irq in IRQ stack */ + sub lr, lr, #4 + stmfd sp!, {lr} + +/*- Save SPSR need to be saved for nested interrupt */ + mrs r14, SPSR + stmfd sp!, {r14} + +/*- Save and r0 in IRQ stack */ + stmfd sp!, {r0} + +/*- Write in the IVR to support Protect Mode */ +/*- No effect in Normal Mode */ +/*- De-assert the NIRQ and clear the source in Protect Mode */ + ldr r14, =AT91C_BASE_AIC + ldr r0 , [r14, #AIC_IVR] + str r14, [r14, #AIC_IVR] + +/*- Enable Interrupt and Switch in Supervisor Mode */ + msr CPSR_c, #ARM_MODE_SVC + +/*- Save scratch/used registers and LR in User Stack */ + stmfd sp!, { r1-r3, r12, r14} + +/*- Branch to the routine pointed by the AIC_IVR */ + mov r14, pc + bx r0 +/*- Restore scratch/used registers and LR from User Stack*/ + ldmia sp!, { r1-r3, r12, r14} + +/*- Disable Interrupt and switch back in IRQ mode */ + msr CPSR_c, #I_BIT | ARM_MODE_IRQ + +/*- Mark the End of Interrupt on the AIC */ + ldr r14, =AT91C_BASE_AIC + str r14, [r14, #AIC_EOICR] + +/*- Restore SPSR_irq and r0 from IRQ stack */ + ldmia sp!, {r0} + +/*- Restore SPSR_irq and r0 from IRQ stack */ + ldmia sp!, {r14} + msr SPSR_cxsf, r14 + +/*- Restore adjusted LR_irq from IRQ stack directly in the PC */ + ldmia sp!, {pc}^ + + .size IRQ_Handler_Entry, . - IRQ_Handler_Entry + .endfunc +/*--------------------------------------------------------------- +//* ?EXEPTION_VECTOR +//* This module is only linked if needed for closing files. +//*---------------------------------------------------------------*/ + .global AT91F_Default_FIQ_handler + .func AT91F_Default_FIQ_handler +AT91F_Default_FIQ_handler: + b AT91F_Default_FIQ_handler + .size AT91F_Default_FIQ_handler, . - AT91F_Default_FIQ_handler + .endfunc + + .global AT91F_Default_IRQ_handler + .func AT91F_Default_IRQ_handler +AT91F_Default_IRQ_handler: + b AT91F_Default_IRQ_handler + .size AT91F_Default_IRQ_handler, . - AT91F_Default_IRQ_handler + .endfunc + + .global AT91F_Spurious_handler + .func AT91F_Spurious_handler +AT91F_Spurious_handler: + b AT91F_Spurious_handler + .size AT91F_Spurious_handler, . - AT91F_Spurious_handler + .endfunc + + .end + diff --git a/openpcd/firmware/compil/SrcWinARM/Cstartup_SAM7.c b/openpcd/firmware/compil/SrcWinARM/Cstartup_SAM7.c new file mode 100644 index 0000000..16fda01 --- /dev/null +++ b/openpcd/firmware/compil/SrcWinARM/Cstartup_SAM7.c @@ -0,0 +1,84 @@ +//*---------------------------------------------------------------------------- +//* ATMEL Microcontroller Software Support - ROUSSET - +//*---------------------------------------------------------------------------- +//* The software is delivered "AS IS" without warranty or condition of any +//* kind, either express, implied or statutory. This includes without +//* limitation any warranty or condition with respect to merchantability or +//* fitness for any particular purpose, or against the infringements of +//* intellectual property rights of others. +//*---------------------------------------------------------------------------- +//* File Name : Cstartup_SAM7.c +//* Object : Low level initializations written in C for Tools +//* Creation : 12/Jun/04 +//* 1.2 28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL +//* 1.3 21/Mar/05 JPP : Change PLL Wait time +//* 1.4 21/Aug/05 JPP : Change MC_FMR Setting +//* 1.5 29/Aug/05 JPP : Change PLL error +//*---------------------------------------------------------------------------- + +// Include the board file description +#include "Board.h" + +// The following functions must be write in ARM mode this function called directly +// by exception vector +extern void AT91F_Spurious_handler(void); +extern void AT91F_Default_IRQ_handler(void); +extern void AT91F_Default_FIQ_handler(void); + +//*---------------------------------------------------------------------------- +//* \fn AT91F_LowLevelInit +//* \brief This function performs very low level HW initialization +//* this function can be use a Stack, depending the compilation +//* optimization mode +//*---------------------------------------------------------------------------- +void AT91F_LowLevelInit(void) +{ + int i; + AT91PS_PMC pPMC = AT91C_BASE_PMC; + //* Set Flash Waite sate + // Single Cycle Access at Up to 30 MHz, or 40 + AT91C_BASE_MC->MC_FMR = AT91C_MC_FWS_1FWS; + + //* Watchdog Disable + AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; + + //* Set MCK at 47 923 200 + // 1 Enabling the Main Oscillator: + // SCK = 1/32768 = 30.51 uSecond + // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms + //// mt pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN )); + pPMC->PMC_MOR = + ((AT91C_CKGR_OSCOUNT & (0x06 << 8)) | AT91C_CKGR_MOSCEN); + // Wait the startup time + while (!(pPMC->PMC_SR & AT91C_PMC_MOSCS)) ; + // 2 Checking the Main Oscillator Frequency (Optional) + // 3 Setting PLL and divider: + // - div by 14 Fin = 1.3165 =(18,432 / 14) + // - Mul 72+1: Fout = 96.1097 =(3,6864 *73) + // for 96 MHz the erroe is 0.11% + // Field out NOT USED = 0 + // PLLCOUNT pll startup time estimate at : 0.844 ms + // PLLCOUNT 28 = 0.000844 /(1/32768) + pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 14) | + (AT91C_CKGR_PLLCOUNT & (28 << 8)) | + (AT91C_CKGR_MUL & (72 << 16))); + + // Wait the startup time + while (!(pPMC->PMC_SR & AT91C_PMC_LOCK)) ; + while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)) ; + // 4. Selection of Master Clock and Processor Clock + // select the PLL clock divided by 2 + pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2; + while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)) ; + + pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK; + while (!(pPMC->PMC_SR & AT91C_PMC_MCKRDY)) ; + + // Set up the default interrupts handler vectors + AT91C_BASE_AIC->AIC_SVR[0] = (int)AT91F_Default_FIQ_handler; + for (i = 1; i < 31; i++) { + AT91C_BASE_AIC->AIC_SVR[i] = (int)AT91F_Default_IRQ_handler; + } + AT91C_BASE_AIC->AIC_SPU = (int)AT91F_Spurious_handler; + +} diff --git a/openpcd/firmware/compil/resource/SAM7.mac b/openpcd/firmware/compil/resource/SAM7.mac new file mode 100644 index 0000000..077061c --- /dev/null +++ b/openpcd/firmware/compil/resource/SAM7.mac @@ -0,0 +1,187 @@ +// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: SAM7.mac
+//
+// 1.0 08/Mar/04 JPP : Creation
+// 1.1 23/Mar/05 JPP : Change Variable name
+//
+// $Revision: 1.1 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+
+execUserPreload()
+{
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
+ CheckRemap();
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+ __mac_i =__readMemory32(0xFFFFF240,"Memory");
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
+ __mac_i =__readMemory32(0xFFFFF244,"Memory");
+ __message " ---------------------------------------- Extention 0x",__mac_i:%X;
+//* Get the chip status
+
+//* Init AIC
+ AIC();
+//* Watchdog Disable
+ Watchdog();
+
+}
+
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+ __message "------------------------------- Watchdog Disable ----------------------------------------";
+}
+
+
+//-----------------------------------------------------------------------------
+// Check Remap
+//-------------
+//-----------------------------------------------------------------------------
+CheckRemap()
+{
+//* Read the value at 0x0
+ __mac_i =__readMemory32(0x00000000,"Memory");
+ __mac_i =__mac_i+1;
+ __writeMemory32(__mac_i,0x00,"Memory");
+ __mac_pt =__readMemory32(0x00000000,"Memory");
+
+ if (__mac_i == __mac_pt)
+ {
+ __message "------------------------------- The Remap is done ----------------------------------------";
+//* Toggel RESET The remap
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+
+ } else {
+ __message "------------------------------- The Remap is NOT -----------------------------------------";
+ }
+
+}
+
+
+execUserSetup()
+{
+ ini();
+ __message "-------------------------------Set PC ----------------------------------------";
+ __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+ __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+ __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock Peripheral Clock Disable Register
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+ __readMemory32(0xFFFA0020,"Memory");
+ __readMemory32(0xFFFA0060,"Memory");
+ __readMemory32(0xFFFA00A0,"Memory");
+
+ for (__mac_i=0;__mac_i < 8; __mac_i++)
+ {
+ // AT91C_BASE_AIC->AIC_EOICR
+ __mac_pt = __readMemory32(0xFFFFF130,"Memory");
+
+ }
+ __message "------------------------------- AIC 2 INIT ---------------------------------------------";
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X;
+__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
+__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X;
+__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X;
+__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X;
+__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X;
+__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X;
+__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X;
+
+__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X;
+
+}
+
diff --git a/openpcd/firmware/compil/resource/SAM7_RAM.mac b/openpcd/firmware/compil/resource/SAM7_RAM.mac new file mode 100644 index 0000000..7837c87 --- /dev/null +++ b/openpcd/firmware/compil/resource/SAM7_RAM.mac @@ -0,0 +1,227 @@ +// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: SAM7_RAM.mac
+//
+// 1.0 08/Mar/05 JPP : Creation
+// 1.1 23/Mar/05 JPP : Change Variable name
+//
+// $Revision: 1.1 $
+//
+// ---------------------------------------------------------
+
+__var __mac_i;
+__var __mac_pt;
+__var __mac_mem;
+execUserReset()
+{
+ CheckNoRemap();
+ ini();
+ AIC();
+ __message "-------------------------------Set PC Reset ----------------------------------";
+ __writeMemory32(0x00000000,0xB4,"Register");
+}
+
+execUserPreload()
+{
+//* __message "-------------------------------Set CPSR ----------------------------------";
+ __writeMemory32(0xD3,0x98,"Register");
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+ PllSetting();
+ //* Init AIC
+ AIC();
+
+//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
+ CheckNoRemap();
+//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
+ __mac_i=__readMemory32(0xFFFFF240,"Memory");
+ __message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
+ __mac_i=__readMemory32(0xFFFFF244,"Memory");
+ __message " ---------------------------------------- Extention 0x",__mac_i:%X;
+ __mac_i=__readMemory32(0xFFFFFF6C,"Memory");
+ __message " ---------------------------------------- Flash Version 0x",__mac_i:%X;
+
+//* Watchdog Disable
+ Watchdog();
+//* RG();
+}
+//-----------------------------------------------------------------------------
+// PllSetting
+//-------------------------------
+// Set PLL
+//-----------------------------------------------------------------------------
+PllSetting()
+{
+// -1- Enabling the Main Oscillator:
+//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
+//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
+//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
+
+//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
+// AT91C_CKGR_MOSCEN )); //0x0000 0001
+__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
+
+// -2- Wait
+// -3- Setting PLL and divider:
+// - div by 5 Fin = 3,6864 =(18,432 / 5)
+// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
+// for 96 MHz the erroe is 0.16%
+// Field out NOT USED = 0
+// PLLCOUNT pll startup time esrtimate at : 0.844 ms
+// PLLCOUNT 28 = 0.000844 /(1/32768)
+// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
+// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
+// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
+__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
+// -2- Wait
+// -5- Selection of Master Clock and Processor Clock
+// select the PLL clock divided by 2
+// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
+// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
+__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
+
+
+ __message "------------------------------- PLL Enable ----------------------------------------";
+}
+
+//-----------------------------------------------------------------------------
+// Watchdog
+//-------------------------------
+// Normally, the Watchdog is enable at the reset for load it's preferable to
+// Disable.
+//-----------------------------------------------------------------------------
+Watchdog()
+{
+//* Watchdog Disable
+// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
+ __writeMemory32(0x00008000,0xFFFFFD44,"Memory");
+ __message "------------------------------- Watchdog Disable ----------------------------------------";
+}
+
+CheckNoRemap()
+{
+//* Read the value at 0x0
+ __mac_i =__readMemory32(0x00000000,"Memory");
+ __mac_mem = __mac_i;
+ __mac_i=__mac_i+1;
+ __writeMemory32(__mac_i,0x00,"Memory");
+ __mac_pt=__readMemory32(0x00000000,"Memory");
+
+ if (__mac_i == __mac_pt)
+ {
+ __message "------------------------------- The Remap is done ----------------------------------------";
+ __writeMemory32( __mac_mem,0x00000000,"Memory");
+
+ } else {
+ __message "------------------------------- The Remap is NOT -----------------------------------------";
+//* Toggel RESET The remap
+ __writeMemory32(0x00000001,0xFFFFFF00,"Memory");
+ }
+
+}
+
+//-----------------------------------------------------------------------------
+// Reset the Interrupt Controller
+//-------------------------------
+// Normally, the code is executed only if a reset has been actually performed.
+// So, the AIC initialization resumes at setting up the default vectors.
+//-----------------------------------------------------------------------------
+AIC()
+{
+// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
+ __writeMemory32(0xffffffff,0xFFFFF124,"Memory");
+ __writeMemory32(0xffffffff,0xFFFFF128,"Memory");
+// disable peripheral clock Peripheral Clock Disable Register
+ __writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
+
+// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
+// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
+// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
+ __readMemory32(0xFFFA0020,"Memory");
+ __readMemory32(0xFFFA0060,"Memory");
+ __readMemory32(0xFFFA00A0,"Memory");
+ for (__mac_i=0;__mac_i < 8; __mac_i++)
+ {
+ // AT91C_BASE_AIC->AIC_EOICR
+ __mac_pt = __readMemory32(0xFFFFF130,"Memory");
+
+ }
+ __message "------------------------------- AIC 2 INIT ---------------------------------------------";
+}
+
+ini()
+{
+__writeMemory32(0x0,0x00,"Register");
+__writeMemory32(0x0,0x04,"Register");
+__writeMemory32(0x0,0x08,"Register");
+__writeMemory32(0x0,0x0C,"Register");
+__writeMemory32(0x0,0x10,"Register");
+__writeMemory32(0x0,0x14,"Register");
+__writeMemory32(0x0,0x18,"Register");
+__writeMemory32(0x0,0x1C,"Register");
+__writeMemory32(0x0,0x20,"Register");
+__writeMemory32(0x0,0x24,"Register");
+__writeMemory32(0x0,0x28,"Register");
+__writeMemory32(0x0,0x2C,"Register");
+__writeMemory32(0x0,0x30,"Register");
+__writeMemory32(0x0,0x34,"Register");
+__writeMemory32(0x0,0x38,"Register");
+
+// Set CPSR
+__writeMemory32(0x0D3,0x98,"Register");
+
+
+}
+
+RG()
+{
+
+__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X;
+__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X;
+__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
+__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X;
+__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X;
+__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X;
+__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X;
+__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X;
+__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X;
+
+__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X;
+
+}
+
diff --git a/openpcd/firmware/compil/resource/at91SAM7S64_16KRAM.xcl b/openpcd/firmware/compil/resource/at91SAM7S64_16KRAM.xcl new file mode 100644 index 0000000..3685bc5 --- /dev/null +++ b/openpcd/firmware/compil/resource/at91SAM7S64_16KRAM.xcl @@ -0,0 +1,137 @@ +// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: at91SAM7S64_16KRAM.xlc
+//
+// 1.1 16/Jun/04 JPP : Creation for 4.11A
+// 1.2 08/Feb/05 JPP : Add CODE_I for __ramfuc
+// $Revision: 1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage: xlink -f lnkarm <your_object_file(s)>
+// -s <program start label> <C/C++ runtime library>
+//
+// $Revision: 1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S64 Memory mapping
+// No remap
+// ROMSTART
+// Start address 0x0000 0000
+// Size 64 Kbo 0x0001 0000
+// RAMSTART
+// Start address 0x0020 0000
+// Size 16 Kbo 0x0000 4000
+// Remap done
+// RAMSTART
+// Start address 0x0000 0000
+// Size 16 Kbo 0x0000 4000
+// ROMSTART
+// Start address 0x0010 0000
+// Size 64 Kbo 0x0001 0000
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 16 K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00000000
+-Z(CONST)INTRAMEND_REMAP=00003FFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 64 K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0000FFFF
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+-DRAMSTART=00000000
+-DRAMEND=00003FFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes,
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for
+-QCODE_I=CODE_ID
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+-D_CSTACK_SIZE=(100*4)
+-D_IRQ_STACK_SIZE=(3*8*4)
+
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+// "-yn": Suppress DWARF debug output
+// "-yp": Multiple ELF program sections
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf
diff --git a/openpcd/firmware/compil/resource/at91SAM7S64_NoRemap.xcl b/openpcd/firmware/compil/resource/at91SAM7S64_NoRemap.xcl new file mode 100644 index 0000000..754cb14 --- /dev/null +++ b/openpcd/firmware/compil/resource/at91SAM7S64_NoRemap.xcl @@ -0,0 +1,139 @@ +// ---------------------------------------------------------
+// ATMEL Microcontroller Software Support - ROUSSET -
+// ---------------------------------------------------------
+// The software is delivered "AS IS" without warranty or
+// condition of any kind, either express, implied or
+// statutory. This includes without limitation any warranty
+// or condition with respect to merchantability or fitness
+// for any particular purpose, or against the infringements of
+// intellectual property rights of others.
+// ---------------------------------------------------------
+// File: at91SAM7S64_NoRemap.xlc
+//
+// 1.1 16/Jun/04 JPP : Creation for 4.11A
+// 1.2 08/Feb/05 JPP : Add CODE_I for __ramfuc
+//
+// $Revision: 1.1 $
+//
+// ---------------------------------------------------------
+
+//*************************************************************************
+// XLINK command file template for EWARM/ICCARM
+//
+// Usage: xlink -f lnkarm <your_object_file(s)>
+// -s <program start label> <C/C++ runtime library>
+//
+// $Revision: 1.1 $
+//*************************************************************************
+
+//************************************************
+// Inform the linker about the CPU family used.
+// AT91SAM7S64 Memory mapping
+// No remap
+// ROMSTART
+// Start address 0x0000 0000
+// Size 64 Kbo 0x0001 0000
+// RAMSTART
+// Start address 0x0020 0000
+// Size 16 Kbo 0x0000 4000
+// Remap done
+// RAMSTART
+// Start address 0x0000 0000
+// Size 16 Kbo 0x0000 4000
+// ROMSTART
+// Start address 0x0010 0000
+// Size 64 Kbo 0x0001 0000
+
+//************************************************
+-carm
+
+//*************************************************************************
+// Internal Ram segments mapped AFTER REMAP 16 K.
+//*************************************************************************
+// Use these addresses for the .
+-Z(CONST)INTRAMSTART_REMAP=00200000
+-Z(CONST)INTRAMEND_REMAP=00203FFF
+
+//*************************************************************************
+// Read-only segments mapped to Flash 64 K.
+//*************************************************************************
+-DROMSTART=00000000
+-DROMEND=0000FFFF
+//*************************************************************************
+// Read/write segments mapped to RAM.
+//*************************************************************************
+-DRAMSTART=00200000
+-DRAMEND=002003FFF
+
+//************************************************
+// Address range for reset and exception
+// vectors (INTVEC).
+// The vector area is 32 bytes,
+// an additional 32 bytes is allocated for the
+// constant table used by ldr PC in cstartup.s79.
+//************************************************
+-Z(CODE)INTVEC=00-3F
+
+//************************************************
+// Startup code and exception routines (ICODE).
+//************************************************
+-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
+-Z(CODE)SWITAB=ROMSTART-ROMEND
+
+//************************************************
+// Code segments may be placed anywhere.
+//************************************************
+-Z(CODE)CODE=ROMSTART-ROMEND
+
+//************************************************
+// Various constants and initializers.
+//************************************************
+-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
+-Z(CONST)CHECKSUM=ROMSTART-ROMEND
+
+
+//************************************************
+// Data segments.
+//************************************************
+-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
+
+//************************************************
+// __ramfunc code copied to and executed from RAM.
+//************************************************
+-Z(DATA)CODE_I=RAMSTART-RAMEND
+-Z(CONST)CODE_ID=ROMSTART-ROMEND // Initializer for
+-QCODE_I=CODE_ID
+
+//************************************************
+// ICCARM produces code for __ramfunc functions in
+// CODE_I segments. The -Q XLINK command line
+// option redirects XLINK to emit the code in the
+// debug information associated with the CODE_I
+// segment, where the code will execute.
+//************************************************
+
+//*************************************************************************
+// Stack and heap segments.
+//*************************************************************************
+-D_CSTACK_SIZE=(100*4)
+-D_IRQ_STACK_SIZE=(3*8*4)
+
+-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
+-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
+
+//*************************************************************************
+// ELF/DWARF support.
+//
+// Uncomment the line "-Felf" below to generate ELF/DWARF output.
+// Available format specifiers are:
+//
+// "-yn": Suppress DWARF debug output
+// "-yp": Multiple ELF program sections
+// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
+//
+// "-Felf" and the format specifiers can also be supplied directly as
+// command line options, or selected from the Xlink Output tab in the
+// IAR Embedded Workbench.
+//*************************************************************************
+
+// -Felf
diff --git a/openpcd/firmware/include/types.h b/openpcd/firmware/include/types.h new file mode 100644 index 0000000..c5c036c --- /dev/null +++ b/openpcd/firmware/include/types.h @@ -0,0 +1,9 @@ +#ifndef _TYPES_H +#define _TYPES_H + +typedef unsigned char u_int8_t; +typedef unsigned short u_int16_t; +typedef unsigned int u_int32_t; +typedef unsigned long long u_int64_t; + +#endif diff --git a/openpcd/firmware/include/usb_ch9.h b/openpcd/firmware/include/usb_ch9.h new file mode 100644 index 0000000..40eeba7 --- /dev/null +++ b/openpcd/firmware/include/usb_ch9.h @@ -0,0 +1,555 @@ +/* + * This file holds USB constants and structures that are needed for USB + * device APIs. These are used by the USB device model, which is defined + * in chapter 9 of the USB 2.0 specification. Linux has several APIs in C + * that need these: + * + * - the master/host side Linux-USB kernel driver API; + * - the "usbfs" user space API; and + * - the Linux "gadget" slave/device/peripheral side driver API. + * + * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems + * act either as a USB master/host or as a USB slave/device. That means + * the master and slave side APIs benefit from working well together. + * + * There's also "Wireless USB", using low power short range radios for + * peripheral interconnection but otherwise building on the USB framework. + */ + +#ifndef __LINUX_USB_CH9_H +#define __LINUX_USB_CH9_H + +#include <include/types.h> + +/*-------------------------------------------------------------------------*/ + +/* CONTROL REQUEST SUPPORT */ + +/* + * USB directions + * + * This bit flag is used in endpoint descriptors' bEndpointAddress field. + * It's also one of three fields in control requests bRequestType. + */ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +/* + * USB types, the second of three bRequestType fields + */ +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients, the third of three bRequestType fields + */ +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 + +/* + * Standard requests, for the bRequest field of a SETUP packet. + * + * These are qualified by the bRequestType field, so that for example + * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved + * by a GET_STATUS request. + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +/* + * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and + * are read as a bit array returned by USB_REQ_GET_STATUS. (So there + * are at most sixteen features of each type.) + */ +#define USB_DEVICE_SELF_POWERED 0 /* (read only) */ +#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */ +#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */ +#define USB_DEVICE_BATTERY 2 /* (wireless) */ +#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */ +#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/ +#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */ +#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */ +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ + +#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */ + + +/** + * struct usb_ctrlrequest - SETUP data for a USB device control request + * @bRequestType: matches the USB bmRequestType field + * @bRequest: matches the USB bRequest field + * @wValue: matches the USB wValue field (le16 byte order) + * @wIndex: matches the USB wIndex field (le16 byte order) + * @wLength: matches the USB wLength field (le16 byte order) + * + * This structure is used to send control requests to a USB device. It matches + * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the + * USB spec for a fuller description of the different fields, and what they are + * used for. + * + * Note that the driver for any interface can issue control requests. + * For most devices, interfaces don't coordinate with each other, so + * such requests may be made at any time. + */ +struct usb_ctrlrequest { + u_int8_t bRequestType; + u_int8_t bRequest; + u_int16_t wValue; + u_int16_t wIndex; + u_int16_t wLength; +} __attribute__ ((packed)); + +/*-------------------------------------------------------------------------*/ + +/* + * STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or + * (rarely) accepted by SET_DESCRIPTOR. + * + * Note that all multi-byte values here are encoded in little endian + * byte order "on the wire". But when exposed through Linux-USB APIs, + * they've been converted to cpu byte order. + */ + +/* + * Descriptor types ... USB 2.0 spec table 9.5 + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +/* these are from a minor usb 2.0 revision (ECN) */ +#define USB_DT_OTG 0x09 +#define USB_DT_DEBUG 0x0a +#define USB_DT_INTERFACE_ASSOCIATION 0x0b +/* these are from the Wireless USB spec */ +#define USB_DT_SECURITY 0x0c +#define USB_DT_KEY 0x0d +#define USB_DT_ENCRYPTION_TYPE 0x0e +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11 + +/* conventional codes for class-specific descriptors */ +#define USB_DT_CS_DEVICE 0x21 +#define USB_DT_CS_CONFIG 0x22 +#define USB_DT_CS_STRING 0x23 +#define USB_DT_CS_INTERFACE 0x24 +#define USB_DT_CS_ENDPOINT 0x25 + +/* All standard descriptors have these 2 fields at the beginning */ +struct usb_descriptor_header { + u_int8_t bLength; + u_int8_t bDescriptorType; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE: Device descriptor */ +struct usb_device_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t bcdUSB; + u_int8_t bDeviceClass; + u_int8_t bDeviceSubClass; + u_int8_t bDeviceProtocol; + u_int8_t bMaxPacketSize0; + u_int16_t idVendor; + u_int16_t idProduct; + u_int16_t bcdDevice; + u_int8_t iManufacturer; + u_int8_t iProduct; + u_int8_t iSerialNumber; + u_int8_t bNumConfigurations; +} __attribute__ ((packed)); + +#define USB_DT_DEVICE_SIZE 18 + + +/* + * Device and/or Interface Class codes + * as found in bDeviceClass or bInterfaceClass + * and defined by www.usb.org documents + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_STILL_IMAGE 6 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b /* chip+ smart card */ +#define USB_CLASS_CONTENT_SEC 0x0d /* content security */ +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_CONFIG: Configuration descriptor information. + * + * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the + * descriptor type is different. Highspeed-capable devices can look + * different depending on what speed they're currently running. Only + * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG + * descriptors. + */ +struct usb_config_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t wTotalLength; + u_int8_t bNumInterfaces; + u_int8_t bConfigurationValue; + u_int8_t iConfiguration; + u_int8_t bmAttributes; + u_int8_t bMaxPower; +} __attribute__ ((packed)); + +#define USB_DT_CONFIG_SIZE 9 + +/* from config descriptor bmAttributes */ +#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ +#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ +#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ +#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_STRING: String descriptor */ +struct usb_string_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t wData[1]; /* UTF-16LE encoded */ +} __attribute__ ((packed)); + +/* note that "string" zero is special, it holds language codes that + * the device supports, not Unicode characters. + */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE: Interface descriptor */ +struct usb_interface_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bInterfaceNumber; + u_int8_t bAlternateSetting; + u_int8_t bNumEndpoints; + u_int8_t bInterfaceClass; + u_int8_t bInterfaceSubClass; + u_int8_t bInterfaceProtocol; + u_int8_t iInterface; +} __attribute__ ((packed)); + +#define USB_DT_INTERFACE_SIZE 9 + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENDPOINT: Endpoint descriptor */ +struct usb_endpoint_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bEndpointAddress; + u_int8_t bmAttributes; + u_int16_t wMaxPacketSize; + u_int8_t bInterval; + + /* NOTE: these two are _only_ in audio endpoints. */ + /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */ + u_int8_t bRefresh; + u_int8_t bSynchAddress; +} __attribute__ ((packed)); + +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ + + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 +#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */ +struct usb_qualifier_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t bcdUSB; + u_int8_t bDeviceClass; + u_int8_t bDeviceSubClass; + u_int8_t bDeviceProtocol; + u_int8_t bMaxPacketSize0; + u_int8_t bNumConfigurations; + u_int8_t bRESERVED; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_OTG (from OTG 1.0a supplement) */ +struct usb_otg_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bmAttributes; /* support for HNP, SRP, etc */ +} __attribute__ ((packed)); + +/* from usb_otg_descriptor.bmAttributes */ +#define USB_OTG_SRP (1 << 0) +#define USB_OTG_HNP (1 << 1) /* swap host/device roles */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEBUG: for special highspeed devices, replacing serial console */ +struct usb_debug_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + /* bulk endpoints with 8 byte maxpacket */ + u_int8_t bDebugInEndpoint; + u_int8_t bDebugOutEndpoint; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */ +struct usb_interface_assoc_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bFirstInterface; + u_int8_t bInterfaceCount; + u_int8_t bFunctionClass; + u_int8_t bFunctionSubClass; + u_int8_t bFunctionProtocol; + u_int8_t iFunction; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SECURITY: group of wireless security descriptors, including + * encryption types available for setting up a CC/association. + */ +struct usb_security_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t wTotalLength; + u_int8_t bNumEncryptionTypes; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_KEY: used with {GET,SET}_SECURITY_DATA; only public keys + * may be retrieved. + */ +struct usb_key_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t tTKID[3]; + u_int8_t bReserved; + u_int8_t bKeyData[0]; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENCRYPTION_TYPE: bundled in DT_SECURITY groups */ +struct usb_encryption_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bEncryptionType; +#define USB_ENC_TYPE_UNSECURE 0 +#define USB_ENC_TYPE_WIRED 1 /* non-wireless mode */ +#define USB_ENC_TYPE_CCM_1 2 /* aes128/cbc session */ +#define USB_ENC_TYPE_RSA_1 3 /* rsa3072/sha1 auth */ + u_int8_t bEncryptionValue; /* use in SET_ENCRYPTION */ + u_int8_t bAuthKeyIndex; +}; + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_BOS: group of wireless capabilities */ +struct usb_bos_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int16_t wTotalLength; + u_int8_t bNumDeviceCaps; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_CAPABILITY: grouped with BOS */ +struct usb_dev_cap_header { + u_int8_t bLength; + u_int8_t bDescriptorType; + u_int8_t bDevCapabilityType; +}; + +#define USB_CAP_TYPE_WIRELESS_USB 1 + +struct usb_wireless_cap_descriptor { /* Ultra Wide Band */ + u_int8_t bLength; + u_int8_t bDescriptorType; + u_int8_t bDevCapabilityType; + + u_int8_t bmAttributes; +#define USB_WIRELESS_P2P_DRD (1 << 1) +#define USB_WIRELESS_BEACON_MASK (3 << 2) +#define USB_WIRELESS_BEACON_SELF (1 << 2) +#define USB_WIRELESS_BEACON_DIRECTED (2 << 2) +#define USB_WIRELESS_BEACON_NONE (3 << 2) + u_int16_t wPHYRates; /* bit rates, Mbps */ +#define USB_WIRELESS_PHY_53 (1 << 0) /* always set */ +#define USB_WIRELESS_PHY_80 (1 << 1) +#define USB_WIRELESS_PHY_107 (1 << 2) /* always set */ +#define USB_WIRELESS_PHY_160 (1 << 3) +#define USB_WIRELESS_PHY_200 (1 << 4) /* always set */ +#define USB_WIRELESS_PHY_320 (1 << 5) +#define USB_WIRELESS_PHY_400 (1 << 6) +#define USB_WIRELESS_PHY_480 (1 << 7) + u_int8_t bmTFITXPowerInfo; /* TFI power levels */ + u_int8_t bmFFITXPowerInfo; /* FFI power levels */ + u_int16_t bmBandGroup; + u_int8_t bReserved; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_WIRELESS_ENDPOINT_COMP: companion descriptor associated with + * each endpoint descriptor for a wireless device + */ +struct usb_wireless_ep_comp_descriptor { + u_int8_t bLength; + u_int8_t bDescriptorType; + + u_int8_t bMaxBurst; + u_int8_t bMaxSequence; + u_int16_t wMaxStreamDelay; + u_int16_t wOverTheAirPacketSize; + u_int8_t bOverTheAirInterval; + u_int8_t bmCompAttributes; +#define USB_ENDPOINT_SWITCH_MASK 0x03 /* in bmCompAttributes */ +#define USB_ENDPOINT_SWITCH_NO 0 +#define USB_ENDPOINT_SWITCH_SWITCH 1 +#define USB_ENDPOINT_SWITCH_SCALE 2 +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless + * host and a device for connection set up, mutual authentication, and + * exchanging short lived session keys. The handshake depends on a CC. + */ +struct usb_handshake { + u_int8_t bMessageNumber; + u_int8_t bStatus; + u_int8_t tTKID[3]; + u_int8_t bReserved; + u_int8_t CDID[16]; + u_int8_t nonce[16]; + u_int8_t MIC[8]; +}; + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC). + * A CC may also be set up using non-wireless secure channels (including + * wired USB!), and some devices may support CCs with multiple hosts. + */ +struct usb_connection_context { + u_int8_t CHID[16]; /* persistent host id */ + u_int8_t CDID[16]; /* device id (unique w/in host context) */ + u_int8_t CK[16]; /* connection key */ +}; + +/*-------------------------------------------------------------------------*/ + +/* USB 2.0 defines three speeds, here's how Linux identifies them */ + +enum usb_device_speed { + USB_SPEED_UNKNOWN = 0, /* enumerating */ + USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */ + USB_SPEED_HIGH, /* usb 2.0 */ + USB_SPEED_VARIABLE, /* wireless (usb 2.5) */ +}; + +enum usb_device_state { + /* NOTATTACHED isn't in the USB spec, and this state acts + * the same as ATTACHED ... but it's clearer this way. + */ + USB_STATE_NOTATTACHED = 0, + + /* chapter 9 and authentication (wireless) device states */ + USB_STATE_ATTACHED, + USB_STATE_POWERED, /* wired */ + USB_STATE_UNAUTHENTICATED, /* auth */ + USB_STATE_RECONNECTING, /* auth */ + USB_STATE_DEFAULT, /* limited function */ + USB_STATE_ADDRESS, + USB_STATE_CONFIGURED, /* most functions */ + + USB_STATE_SUSPENDED + + /* NOTE: there are actually four different SUSPENDED + * states, returning to POWERED, DEFAULT, ADDRESS, or + * CONFIGURED respectively when SOF tokens flow again. + */ +}; + +#endif /* __LINUX_USB_CH9_H */ diff --git a/openpcd/firmware/src/Makefile b/openpcd/firmware/src/Makefile index 6fd9e37..1368a77 100644 --- a/openpcd/firmware/src/Makefile +++ b/openpcd/firmware/src/Makefile @@ -66,14 +66,14 @@ TARGET = main # List C source files here. (C dependencies are automatically generated.) # use file-extension c for "c-only"-files -SRC = $(TARGET).c cdc_enumerate.c dbgu.c +#SRC = $(TARGET).c pcd_enumerate.c dbgu.c # only needed for the "dll-Target": #SRC += syscalls.c # List C source files here which must be compiled in ARM-Mode. # use file-extension c for "c-only"-files -SRCARM = interrupt_Usart.c ../compil/SrcWinARM/Cstartup_SAM7.c +SRCARM = $(TARGET).c pcd_enumerate.c fifo.c dbgu.c rc632.c ../compil/SrcWinARM/Cstartup_SAM7.c # List C++ source files here. # use file-extension cpp for C++-files (use extension .cpp) @@ -111,7 +111,7 @@ DEBUG = dwarf-2 # List any extra directories to look for include files here. # Each directory must be seperated by a space. #EXTRAINCDIRS = ./include -EXTRAINCDIRS = ../compil/SrcWinARM ../.. +EXTRAINCDIRS = ../compil/SrcWinARM ../ # Compiler flag to set the C Standard level. # c89 - "ANSI" C diff --git a/openpcd/firmware/src/fifo.c b/openpcd/firmware/src/fifo.c index 3772187..67a99e7 100644 --- a/openpcd/firmware/src/fifo.c +++ b/openpcd/firmware/src/fifo.c @@ -2,9 +2,6 @@ #include "fifo.h" -#define FIFO_SIZE 1024 - - #define FIFO_IRQ_LO 0x01 #define FIFO_IRQ_HI 0x02 #define FIFO_IRQ_OFLOW 0x04 @@ -23,14 +20,14 @@ void fifo_check_water(struct fifo *fifo) int avail = fifo_available(fifo); if (avail <= fifo->watermark) - irq |= FIFO_IRQ_LO; + fifo->irq |= FIFO_IRQ_LO; else - irq &= FIFO_IRQ_LO; + fifo->irq &= FIFO_IRQ_LO; if (fifo->size - avail >= fifo->watermark) - irq |= FIFO_IRQ_HI; + fifo->irq |= FIFO_IRQ_HI; else - irq &= FIFO_IRQ_HI; + fifo->irq &= FIFO_IRQ_HI; } void fifo_check_raise_int(struct fifo *fifo) diff --git a/openpcd/firmware/src/fifo.h b/openpcd/firmware/src/fifo.h index 68430ee..148625b 100644 --- a/openpcd/firmware/src/fifo.h +++ b/openpcd/firmware/src/fifo.h @@ -1,6 +1,10 @@ #ifndef _FIFO_H #define _FIFO_H +#include <include/types.h> + +#define FIFO_SIZE 1024 + struct fifo { u_int16_t size; /* actual FIFO size, can be smaller than 'data' */ u_int16_t producer; /* index of producer */ diff --git a/openpcd/firmware/src/interrupt_Usart.c b/openpcd/firmware/src/interrupt_Usart.c deleted file mode 100644 index 2bb8bdc..0000000 --- a/openpcd/firmware/src/interrupt_Usart.c +++ /dev/null @@ -1,169 +0,0 @@ -//*---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//*---------------------------------------------------------------------------- -//* The software is delivered "AS IS" without warranty or condition of any -//* kind, either express, implied or statutory. This includes without -//* limitation any warranty or condition with respect to merchantability or -//* fitness for any particular purpose, or against the infringements of -//* intellectual property rights of others. -//*---------------------------------------------------------------------------- -//* File Name : interrupt_Usart.c -//* Object : USART Interrupt Management -//* -//* 1.0 14/Dec/04 JPP : Creation -//* 1.1 29/Aug/05 JPP : Update AIC definion -//*---------------------------------------------------------------------------- - - -// Include Standard LIB files -#include "Board.h" - -#include "cdc_enumerate.h" - -#define USART_INTERRUPT_LEVEL 1 - -AT91PS_USART COM0; -#define USART_BAUD_RATE 115200 - -extern struct _AT91S_CDC pCDC; -static char buff_rx[100]; -static char buff_rx1[100]; -unsigned int first =0; -//*------------------------- Internal Function -------------------------------- - -//*---------------------------------------------------------------------------- -//* Function Name : Trace_Toggel_LED -//* Object : Toggel a LED -//*---------------------------------------------------------------------------- -void Trace_Toggel_LED (unsigned int Led) -{ - if ( (AT91F_PIO_GetInput(AT91C_BASE_PIOA) & Led ) == Led ) - { - AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, Led ); - } - else - { - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, Led ); - } -} -//*------------------------- Interrupt Function ------------------------------- - -//*---------------------------------------------------------------------------- -//* Function Name : Usart_c_irq_handler -//* Object : C handler interrupt function called by the interrupts -//* assembling routine -//*---------------------------------------------------------------------------- -void Usart_c_irq_handler(void) -{ - AT91PS_USART USART_pt = COM0; - unsigned int status; - - //* get Usart status register and active interrupt - status = USART_pt->US_CSR ; - status &= USART_pt->US_IMR; - - if ( status & AT91C_US_RXBUFF){ - //* Toggel LED - Trace_Toggel_LED( LED3) ; - //* transfert the char to DBGU - if ( first == 0){ - COM0->US_RPR = (unsigned int) buff_rx1; - COM0->US_RCR = 100; - pCDC.Write(&pCDC, buff_rx,100); - first =1; - }else{ - COM0->US_RPR = (unsigned int) buff_rx; - COM0->US_RCR = 100; - pCDC.Write(&pCDC, buff_rx1,100); - first=0; - } - } -//* Check error - - if ( status & AT91C_US_TIMEOUT){ - Trace_Toggel_LED( LED4) ; - status = 100 - COM0->US_RCR; - if (status !=0){ - if ( first == 0){ - COM0->US_RPR = (unsigned int) buff_rx1; - COM0->US_RCR = 100; - pCDC.Write(&pCDC, buff_rx,status); - first =1; - }else{ - COM0->US_RPR = (unsigned int) buff_rx; - COM0->US_RCR = 100; - pCDC.Write(&pCDC, buff_rx1,status); - first=0; - } - COM0->US_CR = AT91C_US_STTTO; - } - } - //* Reset the satus bit for error - USART_pt->US_CR = AT91C_US_RSTSTA; -} -//*-------------------------- External Function ------------------------------- - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Printk -//* \brief This function is used to send a string through the US channel -//*---------------------------------------------------------------------------- -void AT91F_US_Put( char *buffer) // \arg pointer to a string ending by \0 -{ - while(*buffer != '\0') { - while (!AT91F_US_TxReady(COM0)); - AT91F_US_PutChar(COM0, *buffer++); - } -} - -//*---------------------------------------------------------------------------- -//* Function Name : Usart_init -//* Object : USART initialization -//* Input Parameters : none -//* Output Parameters : TRUE -//*---------------------------------------------------------------------------- -void Usart_init ( void ) -//* Begin -{ - // Led init - // First, enable the clock of the PIOB - AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA ) ; - //* to be outputs. No need to set these pins to be driven by the PIO because it is GPIO pins only. - AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK ) ; - //* Clear the LED's. - AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK ) ; - //* Set led 1e LED's. - AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, LED1 ) ; - - - COM0= AT91C_BASE_US0; - //* Define RXD and TXD as peripheral - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA5_RXD0 ) | - ((unsigned int) AT91C_PA6_TXD0 ) , // Peripheral A - 0 ); // Peripheral B - - //* First, enable the clock of the PIOB - AT91F_PMC_EnablePeriphClock ( AT91C_BASE_PMC, 1<<AT91C_ID_US0 ) ; - - //* Usart Configure - AT91F_US_Configure (COM0, MCK,AT91C_US_ASYNC_MODE,USART_BAUD_RATE , 0); - - //* Enable usart - COM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN; - - //* open Usart interrupt - AT91F_AIC_ConfigureIt (AT91C_BASE_AIC, AT91C_ID_US0, USART_INTERRUPT_LEVEL, - AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL, Usart_c_irq_handler); - AT91F_AIC_EnableIt (AT91C_BASE_AIC, AT91C_ID_US0); - // Set the PDC - AT91F_PDC_Open (AT91C_BASE_PDC_US0); - COM0->US_RPR = (unsigned int) buff_rx; - COM0->US_RCR = 100; - first = 0; - COM0->US_RTOR = 10; - //* Enable USART IT error and AT91C_US_ENDRX - AT91F_US_EnableIt(COM0,AT91C_US_RXBUFF | AT91C_US_TIMEOUT ); -//* End -} diff --git a/openpcd/firmware/src/main.c b/openpcd/firmware/src/main.c index fc21cf6..342c258 100644 --- a/openpcd/firmware/src/main.c +++ b/openpcd/firmware/src/main.c @@ -17,17 +17,18 @@ //* 1.4 27/Apr/05 JPP : Unset the USART_COM and suppress displaying data //*-------------------------------------------------------------------------------------- -#include "board.h" +//#include "board.h" #include "dbgu.h" -#include "cdc_enumerate.h" +#include "pcd_enumerate.h" #define MSG_SIZE 1000 - +#if 0 #define USART_COM #if defined(__WinARM__) && !defined(UART_COM) #warning "make sure syscalls.c is added to the source-file list (see makefile)" #endif +#endif //* external function diff --git a/openpcd/firmware/src/pcd_enumerate.c b/openpcd/firmware/src/pcd_enumerate.c index f660fda..dddcf03 100644 --- a/openpcd/firmware/src/pcd_enumerate.c +++ b/openpcd/firmware/src/pcd_enumerate.c @@ -18,8 +18,8 @@ // 12. Apr. 2006: added modification found in the mikrocontroller.net gcc-Forum // additional line marked with /* +++ */ -#include "board.h" -#include "usb_ch9.h" +//#include "board.h" +#include <include/usb_ch9.h> #include "pcd_enumerate.h" typedef unsigned char uchar; @@ -47,7 +47,7 @@ struct usb_device_descriptor devDescriptor = { struct _desc { struct usb_config_descriptor ucfg; - struct usb_interface_descriptor uif + struct usb_interface_descriptor uif; struct usb_endpoint_descriptor ep[3]; }; @@ -56,11 +56,11 @@ const struct _desc cfgDescriptor = { .bLength = USB_DT_CONFIG_SIZE, .bDescriptorType = USB_DT_CONFIG, .wTotalLength = USB_DT_CONFIG_SIZE + - USB_DT_INTERFACE_SIZE + 3 * USB_ENDPOINT_SIZE, + USB_DT_INTERFACE_SIZE + 3 * USB_DT_ENDPOINT_SIZE, .bNumInterfaces = 1, .bConfigurationValue = 1, .iConfiguration = 0, - .bmAttributs = USB_CONFIG_ATT_ONE, + .bmAttributes = USB_CONFIG_ATT_ONE, .bMaxPower = 100, /* 200mA */ }, .uif = { @@ -71,11 +71,11 @@ const struct _desc cfgDescriptor = { .bNumEndpoints = 3, .bInterfaceClass = USB_CLASS_VENDOR_SPEC, .bInterfaceSubClass = 0, - .bInterfacePortocol = 0xff, + .bInterfaceProtocol = 0xff, .iInterface = 0, }, .ep[0] = { - .bLength = USB_ENDPOINT_SIZE, + .bLength = USB_DT_ENDPOINT_SIZE, .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x01, .bmAttributes = USB_ENDPOINT_XFER_BULK, @@ -83,7 +83,7 @@ const struct _desc cfgDescriptor = { .bInterval = 0x10, /* FIXME */ }, .ep[1] = { - .bLength = USB_ENDPOINT_SIZE, + .bLength = USB_DT_ENDPOINT_SIZE, .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x81, .bmAttributes = USB_ENDPOINT_XFER_BULK, @@ -91,7 +91,7 @@ const struct _desc cfgDescriptor = { .bInterval = 0x10, /* FIXME */ }, .ep[2] = { - .bLength = USB_ENDPOINT_SIZE, + .bLength = USB_DT_ENDPOINT_SIZE, .bDescriptorType = USB_DT_ENDPOINT, .bEndpointAddress = 0x82, .bmAttributes = USB_ENDPOINT_XFER_INT, @@ -346,10 +346,10 @@ static void AT91F_CDC_Enumerate(AT91PS_CDC pCdc) switch ((bRequest << 8) | bmRequestType) { case STD_GET_DESCRIPTOR: if (wValue == 0x100) // Return Device Descriptor - AT91F_USB_SendData(pUDP, devDescriptor, + AT91F_USB_SendData(pUDP, &devDescriptor, MIN(sizeof(devDescriptor), wLength)); else if (wValue == 0x200) // Return Configuration Descriptor - AT91F_USB_SendData(pUDP, cfgDescriptor, + AT91F_USB_SendData(pUDP, &cfgDescriptor, MIN(sizeof(cfgDescriptor), wLength)); else AT91F_USB_SendStall(pUDP); diff --git a/openpcd/firmware/src/pcd_enumerate.h b/openpcd/firmware/src/pcd_enumerate.h index fdb04b6..33ebfcf 100644 --- a/openpcd/firmware/src/pcd_enumerate.h +++ b/openpcd/firmware/src/pcd_enumerate.h @@ -15,6 +15,7 @@ #ifndef PCD_ENUMERATE_H #define PCD_ENUMERATE_H +#include <include/AT91SAM7S64.h> #define AT91C_EP_OUT 1 #define AT91C_EP_OUT_SIZE 0x40 |