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authorhenryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2007-12-03 04:55:57 +0000
committerhenryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2007-12-03 04:55:57 +0000
commite22f23efcbe54ab8aabfd54f8b55a5d01a15a487 (patch)
tree015aa7b5dcf063d4fc594eb4fade40cd086ae924 /firmware/README
parent67d9be99569c49671b4cc2217824307202b92439 (diff)
* Reduce leaking of TX buffers
* Found the problem that when switching between receiving and sending tc_cdiv would most of the time not generate an SSC_CLOCK for approx. 5ms: The issue is that after setting the divisor (which stored in RC) CV might be greater than RC. Thus no compare will happen until CV overflows (at 0xffff carrier cycles) and therefore the clock will appear to be stopped for that time. A good fix would have been TC_CV = TC_CV % TC_RC but unfortunately TC_CV is read-only. Instead use SWTRG to reset TC_CV to zero and then try to use the phase-shift code to have the phase stay correct. * Measured the transmit start delay that is introduced by the SSC TF emulation through FIQ and adjusted ISO14443A_FDT accordingly git-svn-id: https://svn.openpcd.org:2342/trunk@366 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
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