diff options
| author | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-07-25 07:20:58 +0000 |
|---|---|---|
| committer | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-07-25 07:20:58 +0000 |
| commit | 9164ed9344b1ffd2b6a545afb1dfc7ebe022d315 (patch) | |
| tree | dca971401188cc7d149cc0dda8f8b8a3f5d72442 /openpcd/firmware/include | |
| parent | 82327a2198619f705ba13dbc70ed4d5878b35d9d (diff) | |
fixed linker/makefile & updated 'board.h'-concept
git-svn-id: https://svn.openpcd.org:2342/trunk@39 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpcd/firmware/include')
| -rw-r--r-- | openpcd/firmware/include/AT91SAM7.h | 6 | ||||
| -rw-r--r-- | openpcd/firmware/include/AT91SAM7S64.html | 7 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/AT91SAM7S256.h | 1917 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/AT91SAM7S64.h | 1917 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/AT91SAM7S64.inc | 1748 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/AT91SAM7S64.rdf | 3104 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/AT91SAM7S64_inc.h | 1706 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/ioat91sam7s64.ddf | 1524 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/ioat91sam7s64.h | 3300 | ||||
| -rw-r--r-- | openpcd/firmware/include/old/lib_AT91SAM7S256.h | 3719 |
10 files changed, 3 insertions, 18945 deletions
diff --git a/openpcd/firmware/include/AT91SAM7.h b/openpcd/firmware/include/AT91SAM7.h index b35583a..5a07d00 100644 --- a/openpcd/firmware/include/AT91SAM7.h +++ b/openpcd/firmware/include/AT91SAM7.h @@ -39,8 +39,8 @@ // CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// // ---------------------------------------------------------------------------- -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H +#ifndef __AT91SAM7_H__ +#define __AT91SAM7_H__ typedef volatile unsigned int AT91_REG;// Hardware register definition @@ -1927,4 +1927,4 @@ typedef struct _AT91S_UDP { #endif #endif -#endif +#endif/*__AT91SAM7_H__*/ diff --git a/openpcd/firmware/include/AT91SAM7S64.html b/openpcd/firmware/include/AT91SAM7S64.html deleted file mode 100644 index c77cdbb..0000000 --- a/openpcd/firmware/include/AT91SAM7S64.html +++ /dev/null @@ -1,7 +0,0 @@ -<html><head>
-<meta charset="iso-8859-1" content="Arm / ATMEL/ AT91 library / AT91SAM7S64" http-equiv="Content-Type">
-<title>Hardware API Selector: AT91SAM7S64 Main Frame</title>
-</head>
-<frameset cols="20%, *"><frame name="Index" src="./HTML/AT91SAM7S64_idx.html">
-<frame name="Main" src="./HTML/AT91SAM7S64_DBGU.html"></frameset>
-</html>
diff --git a/openpcd/firmware/include/old/AT91SAM7S256.h b/openpcd/firmware/include/old/AT91SAM7S256.h deleted file mode 100644 index 64d883f..0000000 --- a/openpcd/firmware/include/old/AT91SAM7S256.h +++ /dev/null @@ -1,1917 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S256.h -// Object : AT91SAM7S256 definitions -// Generated : AT91 SW Application Group 01/16/2006 (16:36:06) -// -// CVS Reference : /AT91SAM7S256.pl/1.11/Tue Aug 30 12:00:29 2005// -// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// -// CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005// -// CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S256_H -#define AT91SAM7S256_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S256 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved -#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved -#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved -#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT ((unsigned int) 0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S256 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbytes) -// IFLASH -#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00040000) // Internal FLASH size in byte (256 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 256) // Internal FLASH Page Size: 256 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 16384) // Internal FLASH Lock Region Size: 16 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 1024) // Internal FLASH Number of Pages: 1024 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 16) // Internal FLASH Number of Lock Bits: 16 bytes - -#endif diff --git a/openpcd/firmware/include/old/AT91SAM7S64.h b/openpcd/firmware/include/old/AT91SAM7S64.h deleted file mode 100644 index 4788c56..0000000 --- a/openpcd/firmware/include/old/AT91SAM7S64.h +++ /dev/null @@ -1,1917 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 08/30/2005 (15:52:59) -// -// CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005// -// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// -// CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005// -// CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 1 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved -#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved -#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved -#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT ((unsigned int) 0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbytes) -// IFLASH -#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal FLASH size in byte (64 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 128) // Internal FLASH Page Size: 128 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 4096) // Internal FLASH Lock Region Size: 4 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 256) // Internal FLASH Number of Pages: 256 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 8) // Internal FLASH Number of Lock Bits: 8 bytes - -#endif diff --git a/openpcd/firmware/include/old/AT91SAM7S64.inc b/openpcd/firmware/include/old/AT91SAM7S64.inc deleted file mode 100644 index 972e93f..0000000 --- a/openpcd/firmware/include/old/AT91SAM7S64.inc +++ /dev/null @@ -1,1748 +0,0 @@ -;- ----------------------------------------------------------------------------
-;- ATMEL Microcontroller Software Support - ROUSSET -
-;- ----------------------------------------------------------------------------
-;- DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-;- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-;- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-;- DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-;- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-;- LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-;- OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-;- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-;- NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-;- EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;- ----------------------------------------------------------------------------
-;- File Name : AT91SAM7S64.h
-;- Object : AT91SAM7S64 definitions
-;- Generated : AT91 SW Application Group 08/30/2005 (15:53:00)
-;-
-;- CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//
-;- CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
-;- CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//
-;- CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
-;- CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//
-;- CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//
-;- CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//
-;- CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-;- CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-;- CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-;- CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-;- CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-;- CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-;- CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-;- CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-;- CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-;- CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-;- CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-;- CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-;- CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-;- CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-;- ----------------------------------------------------------------------------
-
-;- Hardware register definition
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR System Peripherals
-;- *****************************************************************************
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
-;- *****************************************************************************
- ^ 0 ;- AT91S_AIC
-AIC_SMR # 128 ;- Source Mode Register
-AIC_SVR # 128 ;- Source Vector Register
-AIC_IVR # 4 ;- IRQ Vector Register
-AIC_FVR # 4 ;- FIQ Vector Register
-AIC_ISR # 4 ;- Interrupt Status Register
-AIC_IPR # 4 ;- Interrupt Pending Register
-AIC_IMR # 4 ;- Interrupt Mask Register
-AIC_CISR # 4 ;- Core Interrupt Status Register
- # 8 ;- Reserved
-AIC_IECR # 4 ;- Interrupt Enable Command Register
-AIC_IDCR # 4 ;- Interrupt Disable Command Register
-AIC_ICCR # 4 ;- Interrupt Clear Command Register
-AIC_ISCR # 4 ;- Interrupt Set Command Register
-AIC_EOICR # 4 ;- End of Interrupt Command Register
-AIC_SPU # 4 ;- Spurious Vector Register
-AIC_DCR # 4 ;- Debug Control Register (Protect)
- # 4 ;- Reserved
-AIC_FFER # 4 ;- Fast Forcing Enable Register
-AIC_FFDR # 4 ;- Fast Forcing Disable Register
-AIC_FFSR # 4 ;- Fast Forcing Status Register
-;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
-AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0:SHL:5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1:SHL:5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
-AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
-;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
-AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Peripheral DMA Controller
-;- *****************************************************************************
- ^ 0 ;- AT91S_PDC
-PDC_RPR # 4 ;- Receive Pointer Register
-PDC_RCR # 4 ;- Receive Counter Register
-PDC_TPR # 4 ;- Transmit Pointer Register
-PDC_TCR # 4 ;- Transmit Counter Register
-PDC_RNPR # 4 ;- Receive Next Pointer Register
-PDC_RNCR # 4 ;- Receive Next Counter Register
-PDC_TNPR # 4 ;- Transmit Next Pointer Register
-PDC_TNCR # 4 ;- Transmit Next Counter Register
-PDC_PTCR # 4 ;- PDC Transfer Control Register
-PDC_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
-AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
-;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Debug Unit
-;- *****************************************************************************
- ^ 0 ;- AT91S_DBGU
-DBGU_CR # 4 ;- Control Register
-DBGU_MR # 4 ;- Mode Register
-DBGU_IER # 4 ;- Interrupt Enable Register
-DBGU_IDR # 4 ;- Interrupt Disable Register
-DBGU_IMR # 4 ;- Interrupt Mask Register
-DBGU_CSR # 4 ;- Channel Status Register
-DBGU_RHR # 4 ;- Receiver Holding Register
-DBGU_THR # 4 ;- Transmitter Holding Register
-DBGU_BRGR # 4 ;- Baud Rate Generator Register
- # 28 ;- Reserved
-DBGU_CIDR # 4 ;- Chip ID Register
-DBGU_EXID # 4 ;- Chip ID Extension Register
-DBGU_FNTR # 4 ;- Force NTRST Register
- # 180 ;- Reserved
-DBGU_RPR # 4 ;- Receive Pointer Register
-DBGU_RCR # 4 ;- Receive Counter Register
-DBGU_TPR # 4 ;- Transmit Pointer Register
-DBGU_TCR # 4 ;- Transmit Counter Register
-DBGU_RNPR # 4 ;- Receive Next Pointer Register
-DBGU_RNCR # 4 ;- Receive Next Counter Register
-DBGU_TNPR # 4 ;- Transmit Next Pointer Register
-DBGU_TNCR # 4 ;- Transmit Next Counter Register
-DBGU_PTCR # 4 ;- PDC Transfer Control Register
-DBGU_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (DBGU) Reset Status Bits
-;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
-;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
-;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
-;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
-;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
-AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
-;- *****************************************************************************
- ^ 0 ;- AT91S_PIO
-PIO_PER # 4 ;- PIO Enable Register
-PIO_PDR # 4 ;- PIO Disable Register
-PIO_PSR # 4 ;- PIO Status Register
- # 4 ;- Reserved
-PIO_OER # 4 ;- Output Enable Register
-PIO_ODR # 4 ;- Output Disable Registerr
-PIO_OSR # 4 ;- Output Status Register
- # 4 ;- Reserved
-PIO_IFER # 4 ;- Input Filter Enable Register
-PIO_IFDR # 4 ;- Input Filter Disable Register
-PIO_IFSR # 4 ;- Input Filter Status Register
- # 4 ;- Reserved
-PIO_SODR # 4 ;- Set Output Data Register
-PIO_CODR # 4 ;- Clear Output Data Register
-PIO_ODSR # 4 ;- Output Data Status Register
-PIO_PDSR # 4 ;- Pin Data Status Register
-PIO_IER # 4 ;- Interrupt Enable Register
-PIO_IDR # 4 ;- Interrupt Disable Register
-PIO_IMR # 4 ;- Interrupt Mask Register
-PIO_ISR # 4 ;- Interrupt Status Register
-PIO_MDER # 4 ;- Multi-driver Enable Register
-PIO_MDDR # 4 ;- Multi-driver Disable Register
-PIO_MDSR # 4 ;- Multi-driver Status Register
- # 4 ;- Reserved
-PIO_PPUDR # 4 ;- Pull-up Disable Register
-PIO_PPUER # 4 ;- Pull-up Enable Register
-PIO_PPUSR # 4 ;- Pull-up Status Register
- # 4 ;- Reserved
-PIO_ASR # 4 ;- Select A Register
-PIO_BSR # 4 ;- Select B Register
-PIO_ABSR # 4 ;- AB Select Status Register
- # 36 ;- Reserved
-PIO_OWER # 4 ;- Output Write Enable Register
-PIO_OWDR # 4 ;- Output Write Disable Register
-PIO_OWSR # 4 ;- Output Write Status Register
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Clock Generator Controler
-;- *****************************************************************************
- ^ 0 ;- AT91S_CKGR
-CKGR_MOR # 4 ;- Main Oscillator Register
-CKGR_MCFR # 4 ;- Main Clock Frequency Register
- # 4 ;- Reserved
-CKGR_PLLR # 4 ;- PLL Register
-;- -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register --------
-AT91C_CKGR_MOSCEN EQU (0x1:SHL:0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS EQU (0x1:SHL:1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT EQU (0xFF:SHL:8) ;- (CKGR) Main Oscillator Start-up Time
-;- -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register --------
-AT91C_CKGR_MAINF EQU (0xFFFF:SHL:0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY EQU (0x1:SHL:16) ;- (CKGR) Main Clock Ready
-;- -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register --------
-AT91C_CKGR_DIV EQU (0xFF:SHL:0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT EQU (0x3F:SHL:8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT EQU (0x3:SHL:14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0 EQU (0x0:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1 EQU (0x1:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2 EQU (0x2:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3 EQU (0x3:SHL:14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL EQU (0x7FF:SHL:16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV EQU (0x3:SHL:28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0 EQU (0x0:SHL:28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1 EQU (0x1:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2 EQU (0x2:SHL:28) ;- (CKGR) Divider output is PLL clock output divided by 4
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Power Management Controler
-;- *****************************************************************************
- ^ 0 ;- AT91S_PMC
-PMC_SCER # 4 ;- System Clock Enable Register
-PMC_SCDR # 4 ;- System Clock Disable Register
-PMC_SCSR # 4 ;- System Clock Status Register
- # 4 ;- Reserved
-PMC_PCER # 4 ;- Peripheral Clock Enable Register
-PMC_PCDR # 4 ;- Peripheral Clock Disable Register
-PMC_PCSR # 4 ;- Peripheral Clock Status Register
- # 4 ;- Reserved
-PMC_MOR # 4 ;- Main Oscillator Register
-PMC_MCFR # 4 ;- Main Clock Frequency Register
- # 4 ;- Reserved
-PMC_PLLR # 4 ;- PLL Register
-PMC_MCKR # 4 ;- Master Clock Register
- # 12 ;- Reserved
-PMC_PCKR # 12 ;- Programmable Clock Register
- # 20 ;- Reserved
-PMC_IER # 4 ;- Interrupt Enable Register
-PMC_IDR # 4 ;- Interrupt Disable Register
-PMC_SR # 4 ;- Status Register
-PMC_IMR # 4 ;- Interrupt Mask Register
-;- -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register --------
-AT91C_PMC_PCK EQU (0x1:SHL:0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP EQU (0x1:SHL:7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0 EQU (0x1:SHL:8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1 EQU (0x1:SHL:9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2 EQU (0x1:SHL:10) ;- (PMC) Programmable Clock Output
-;- -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register --------
-;- -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register --------
-;- -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register --------
-;- -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register --------
-;- -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register --------
-;- -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register --------
-AT91C_PMC_CSS EQU (0x3:SHL:0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES EQU (0x7:SHL:2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK EQU (0x0:SHL:2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2 EQU (0x1:SHL:2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4 EQU (0x2:SHL:2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8 EQU (0x3:SHL:2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16 EQU (0x4:SHL:2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32 EQU (0x5:SHL:2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64 EQU (0x6:SHL:2) ;- (PMC) Selected clock divided by 64
-;- -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register --------
-;- -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register --------
-AT91C_PMC_MOSCS EQU (0x1:SHL:0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK EQU (0x1:SHL:2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY EQU (0x1:SHL:3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY EQU (0x1:SHL:8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY EQU (0x1:SHL:9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY EQU (0x1:SHL:10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-;- -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register --------
-;- -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register --------
-;- -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Reset Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_RSTC
-RSTC_RCR # 4 ;- Reset Control Register
-RSTC_RSR # 4 ;- Reset Status Register
-RSTC_RMR # 4 ;- Reset Mode Register
-;- -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register --------
-AT91C_RSTC_PROCRST EQU (0x1:SHL:0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST EQU (0x1:SHL:2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST EQU (0x1:SHL:3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY EQU (0xFF:SHL:24) ;- (RSTC) Password
-;- -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register --------
-AT91C_RSTC_URSTS EQU (0x1:SHL:0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS EQU (0x1:SHL:1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP EQU (0x7:SHL:8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0:SHL:8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1:SHL:8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2:SHL:8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3:SHL:8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER EQU (0x4:SHL:8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5:SHL:8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL EQU (0x1:SHL:16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP EQU (0x1:SHL:17) ;- (RSTC) Software Reset Command in Progress.
-;- -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register --------
-AT91C_RSTC_URSTEN EQU (0x1:SHL:0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN EQU (0x1:SHL:4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL EQU (0xF:SHL:8) ;- (RSTC) User Reset Length
-AT91C_RSTC_BODIEN EQU (0x1:SHL:16) ;- (RSTC) Brownout Detection Interrupt Enable
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_RTTC
-RTTC_RTMR # 4 ;- Real-time Mode Register
-RTTC_RTAR # 4 ;- Real-time Alarm Register
-RTTC_RTVR # 4 ;- Real-time Value Register
-RTTC_RTSR # 4 ;- Real-time Status Register
-;- -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register --------
-AT91C_RTTC_RTPRES EQU (0xFFFF:SHL:0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN EQU (0x1:SHL:16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN EQU (0x1:SHL:17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST EQU (0x1:SHL:18) ;- (RTTC) Real Time Timer Restart
-;- -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register --------
-AT91C_RTTC_ALMV EQU (0x0:SHL:0) ;- (RTTC) Alarm Value
-;- -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register --------
-AT91C_RTTC_CRTV EQU (0x0:SHL:0) ;- (RTTC) Current Real-time Value
-;- -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register --------
-AT91C_RTTC_ALMS EQU (0x1:SHL:0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC EQU (0x1:SHL:1) ;- (RTTC) Real-time Timer Increment
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_PITC
-PITC_PIMR # 4 ;- Period Interval Mode Register
-PITC_PISR # 4 ;- Period Interval Status Register
-PITC_PIVR # 4 ;- Period Interval Value Register
-PITC_PIIR # 4 ;- Period Interval Image Register
-;- -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register --------
-AT91C_PITC_PIV EQU (0xFFFFF:SHL:0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN EQU (0x1:SHL:24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN EQU (0x1:SHL:25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-;- -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register --------
-AT91C_PITC_PITS EQU (0x1:SHL:0) ;- (PITC) Periodic Interval Timer Status
-;- -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register --------
-AT91C_PITC_CPIV EQU (0xFFFFF:SHL:0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT EQU (0xFFF:SHL:20) ;- (PITC) Periodic Interval Counter
-;- -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_WDTC
-WDTC_WDCR # 4 ;- Watchdog Control Register
-WDTC_WDMR # 4 ;- Watchdog Mode Register
-WDTC_WDSR # 4 ;- Watchdog Status Register
-;- -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register --------
-AT91C_WDTC_WDRSTT EQU (0x1:SHL:0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY EQU (0xFF:SHL:24) ;- (WDTC) Watchdog KEY Password
-;- -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register --------
-AT91C_WDTC_WDV EQU (0xFFF:SHL:0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN EQU (0x1:SHL:12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN EQU (0x1:SHL:13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC EQU (0x1:SHL:14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS EQU (0x1:SHL:15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD EQU (0xFFF:SHL:16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT EQU (0x1:SHL:28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT EQU (0x1:SHL:29) ;- (WDTC) Watchdog Idle Halt
-;- -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register --------
-AT91C_WDTC_WDUNF EQU (0x1:SHL:0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR EQU (0x1:SHL:1) ;- (WDTC) Watchdog Error
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_VREG
-VREG_MR # 4 ;- Voltage Regulator Mode Register
-;- -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register --------
-AT91C_VREG_PSTDBY EQU (0x1:SHL:0) ;- (VREG) Voltage Regulator Power Standby Mode
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Memory Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_MC
-MC_RCR # 4 ;- MC Remap Control Register
-MC_ASR # 4 ;- MC Abort Status Register
-MC_AASR # 4 ;- MC Abort Address Status Register
- # 84 ;- Reserved
-MC_FMR # 4 ;- MC Flash Mode Register
-MC_FCR # 4 ;- MC Flash Command Register
-MC_FSR # 4 ;- MC Flash Status Register
-;- -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register --------
-AT91C_MC_RCB EQU (0x1:SHL:0) ;- (MC) Remap Command Bit
-;- -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register --------
-AT91C_MC_UNDADD EQU (0x1:SHL:0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD EQU (0x1:SHL:1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ EQU (0x3:SHL:8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE EQU (0x0:SHL:8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD EQU (0x1:SHL:8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD EQU (0x2:SHL:8) ;- (MC) Word
-AT91C_MC_ABTTYP EQU (0x3:SHL:10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR EQU (0x0:SHL:10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW EQU (0x1:SHL:10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH EQU (0x2:SHL:10) ;- (MC) Code Fetch
-AT91C_MC_MST0 EQU (0x1:SHL:16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1 EQU (0x1:SHL:17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0 EQU (0x1:SHL:24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1 EQU (0x1:SHL:25) ;- (MC) Saved Master 1 Abort Source
-;- -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register --------
-AT91C_MC_FRDY EQU (0x1:SHL:0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE EQU (0x1:SHL:2) ;- (MC) Lock Error
-AT91C_MC_PROGE EQU (0x1:SHL:3) ;- (MC) Programming Error
-AT91C_MC_NEBP EQU (0x1:SHL:7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS EQU (0x3:SHL:8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS EQU (0x0:SHL:8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS EQU (0x1:SHL:8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS EQU (0x2:SHL:8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS EQU (0x3:SHL:8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN EQU (0xFF:SHL:16) ;- (MC) Flash Microsecond Cycle Number
-;- -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register --------
-AT91C_MC_FCMD EQU (0xF:SHL:0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN EQU (0x3FF:SHL:8) ;- (MC) Page Number
-AT91C_MC_KEY EQU (0xFF:SHL:24) ;- (MC) Writing Protect Key
-;- -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register --------
-AT91C_MC_SECURITY EQU (0x1:SHL:4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0 EQU (0x1:SHL:8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1 EQU (0x1:SHL:9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2 EQU (0x1:SHL:10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3 EQU (0x1:SHL:11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4 EQU (0x1:SHL:12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5 EQU (0x1:SHL:13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6 EQU (0x1:SHL:14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7 EQU (0x1:SHL:15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0 EQU (0x1:SHL:16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1 EQU (0x1:SHL:17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2 EQU (0x1:SHL:18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3 EQU (0x1:SHL:19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4 EQU (0x1:SHL:20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5 EQU (0x1:SHL:21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6 EQU (0x1:SHL:22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7 EQU (0x1:SHL:23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8 EQU (0x1:SHL:24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9 EQU (0x1:SHL:25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10 EQU (0x1:SHL:26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11 EQU (0x1:SHL:27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12 EQU (0x1:SHL:28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13 EQU (0x1:SHL:29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14 EQU (0x1:SHL:30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15 EQU (0x1:SHL:31) ;- (MC) Sector 15 Lock Status
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Serial Parallel Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_SPI
-SPI_CR # 4 ;- Control Register
-SPI_MR # 4 ;- Mode Register
-SPI_RDR # 4 ;- Receive Data Register
-SPI_TDR # 4 ;- Transmit Data Register
-SPI_SR # 4 ;- Status Register
-SPI_IER # 4 ;- Interrupt Enable Register
-SPI_IDR # 4 ;- Interrupt Disable Register
-SPI_IMR # 4 ;- Interrupt Mask Register
- # 16 ;- Reserved
-SPI_CSR # 16 ;- Chip Select Register
- # 192 ;- Reserved
-SPI_RPR # 4 ;- Receive Pointer Register
-SPI_RCR # 4 ;- Receive Counter Register
-SPI_TPR # 4 ;- Transmit Pointer Register
-SPI_TCR # 4 ;- Transmit Counter Register
-SPI_RNPR # 4 ;- Receive Next Pointer Register
-SPI_RNCR # 4 ;- Receive Next Counter Register
-SPI_TNPR # 4 ;- Transmit Next Pointer Register
-SPI_TNCR # 4 ;- Transmit Next Counter Register
-SPI_PTCR # 4 ;- PDC Transfer Control Register
-SPI_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register --------
-AT91C_SPI_SPIEN EQU (0x1:SHL:0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS EQU (0x1:SHL:1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST EQU (0x1:SHL:7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER EQU (0x1:SHL:24) ;- (SPI) SPI Last Transfer
-;- -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register --------
-AT91C_SPI_MSTR EQU (0x1:SHL:0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS EQU (0x1:SHL:1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED EQU (0x0:SHL:1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE EQU (0x1:SHL:1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC EQU (0x1:SHL:2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV EQU (0x1:SHL:3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS EQU (0x1:SHL:4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB EQU (0x1:SHL:7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS EQU (0xFF:SHL:24) ;- (SPI) Delay Between Chip Selects
-;- -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register --------
-AT91C_SPI_RD EQU (0xFFFF:SHL:0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
-;- -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register --------
-AT91C_SPI_TD EQU (0xFFFF:SHL:0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS EQU (0xF:SHL:16) ;- (SPI) Peripheral Chip Select Status
-;- -------- SPI_SR : (SPI Offset: 0x10) Status Register --------
-AT91C_SPI_RDRF EQU (0x1:SHL:0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE EQU (0x1:SHL:1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF EQU (0x1:SHL:2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES EQU (0x1:SHL:3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX EQU (0x1:SHL:4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX EQU (0x1:SHL:5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF EQU (0x1:SHL:6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE EQU (0x1:SHL:7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR EQU (0x1:SHL:8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY EQU (0x1:SHL:9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS EQU (0x1:SHL:16) ;- (SPI) Enable Status
-;- -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register --------
-;- -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register --------
-;- -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register --------
-;- -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register --------
-AT91C_SPI_CPOL EQU (0x1:SHL:0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA EQU (0x1:SHL:1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT EQU (0x1:SHL:3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS EQU (0xF:SHL:4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8 EQU (0x0:SHL:4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9 EQU (0x1:SHL:4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10 EQU (0x2:SHL:4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11 EQU (0x3:SHL:4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12 EQU (0x4:SHL:4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13 EQU (0x5:SHL:4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14 EQU (0x6:SHL:4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15 EQU (0x7:SHL:4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16 EQU (0x8:SHL:4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR EQU (0xFF:SHL:8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS EQU (0xFF:SHL:16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT EQU (0xFF:SHL:24) ;- (SPI) Delay Between Consecutive Transfers
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Analog to Digital Convertor
-;- *****************************************************************************
- ^ 0 ;- AT91S_ADC
-ADC_CR # 4 ;- ADC Control Register
-ADC_MR # 4 ;- ADC Mode Register
- # 8 ;- Reserved
-ADC_CHER # 4 ;- ADC Channel Enable Register
-ADC_CHDR # 4 ;- ADC Channel Disable Register
-ADC_CHSR # 4 ;- ADC Channel Status Register
-ADC_SR # 4 ;- ADC Status Register
-ADC_LCDR # 4 ;- ADC Last Converted Data Register
-ADC_IER # 4 ;- ADC Interrupt Enable Register
-ADC_IDR # 4 ;- ADC Interrupt Disable Register
-ADC_IMR # 4 ;- ADC Interrupt Mask Register
-ADC_CDR0 # 4 ;- ADC Channel Data Register 0
-ADC_CDR1 # 4 ;- ADC Channel Data Register 1
-ADC_CDR2 # 4 ;- ADC Channel Data Register 2
-ADC_CDR3 # 4 ;- ADC Channel Data Register 3
-ADC_CDR4 # 4 ;- ADC Channel Data Register 4
-ADC_CDR5 # 4 ;- ADC Channel Data Register 5
-ADC_CDR6 # 4 ;- ADC Channel Data Register 6
-ADC_CDR7 # 4 ;- ADC Channel Data Register 7
- # 176 ;- Reserved
-ADC_RPR # 4 ;- Receive Pointer Register
-ADC_RCR # 4 ;- Receive Counter Register
-ADC_TPR # 4 ;- Transmit Pointer Register
-ADC_TCR # 4 ;- Transmit Counter Register
-ADC_RNPR # 4 ;- Receive Next Pointer Register
-ADC_RNCR # 4 ;- Receive Next Counter Register
-ADC_TNPR # 4 ;- Transmit Next Pointer Register
-ADC_TNCR # 4 ;- Transmit Next Counter Register
-ADC_PTCR # 4 ;- PDC Transfer Control Register
-ADC_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register --------
-AT91C_ADC_SWRST EQU (0x1:SHL:0) ;- (ADC) Software Reset
-AT91C_ADC_START EQU (0x1:SHL:1) ;- (ADC) Start Conversion
-;- -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register --------
-AT91C_ADC_TRGEN EQU (0x1:SHL:0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL EQU (0x7:SHL:1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0 EQU (0x0:SHL:1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1 EQU (0x1:SHL:1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2 EQU (0x2:SHL:1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3 EQU (0x3:SHL:1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4 EQU (0x4:SHL:1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5 EQU (0x5:SHL:1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT EQU (0x6:SHL:1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES EQU (0x1:SHL:4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT EQU (0x0:SHL:4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT EQU (0x1:SHL:4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0:SHL:5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE EQU (0x1:SHL:5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL EQU (0x3F:SHL:8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP EQU (0x1F:SHL:16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM EQU (0xF:SHL:24) ;- (ADC) Sample & Hold Time
-;- -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register --------
-AT91C_ADC_CH0 EQU (0x1:SHL:0) ;- (ADC) Channel 0
-AT91C_ADC_CH1 EQU (0x1:SHL:1) ;- (ADC) Channel 1
-AT91C_ADC_CH2 EQU (0x1:SHL:2) ;- (ADC) Channel 2
-AT91C_ADC_CH3 EQU (0x1:SHL:3) ;- (ADC) Channel 3
-AT91C_ADC_CH4 EQU (0x1:SHL:4) ;- (ADC) Channel 4
-AT91C_ADC_CH5 EQU (0x1:SHL:5) ;- (ADC) Channel 5
-AT91C_ADC_CH6 EQU (0x1:SHL:6) ;- (ADC) Channel 6
-AT91C_ADC_CH7 EQU (0x1:SHL:7) ;- (ADC) Channel 7
-;- -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register --------
-;- -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register --------
-;- -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register --------
-AT91C_ADC_EOC0 EQU (0x1:SHL:0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1 EQU (0x1:SHL:1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2 EQU (0x1:SHL:2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3 EQU (0x1:SHL:3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4 EQU (0x1:SHL:4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5 EQU (0x1:SHL:5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6 EQU (0x1:SHL:6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7 EQU (0x1:SHL:7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0 EQU (0x1:SHL:8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1 EQU (0x1:SHL:9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2 EQU (0x1:SHL:10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3 EQU (0x1:SHL:11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4 EQU (0x1:SHL:12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5 EQU (0x1:SHL:13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6 EQU (0x1:SHL:14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7 EQU (0x1:SHL:15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY EQU (0x1:SHL:16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE EQU (0x1:SHL:17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX EQU (0x1:SHL:18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF EQU (0x1:SHL:19) ;- (ADC) RXBUFF Interrupt
-;- -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register --------
-AT91C_ADC_LDATA EQU (0x3FF:SHL:0) ;- (ADC) Last Data Converted
-;- -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register --------
-;- -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register --------
-;- -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register --------
-;- -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 --------
-AT91C_ADC_DATA EQU (0x3FF:SHL:0) ;- (ADC) Converted Data
-;- -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 --------
-;- -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 --------
-;- -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 --------
-;- -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 --------
-;- -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 --------
-;- -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 --------
-;- -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_SSC
-SSC_CR # 4 ;- Control Register
-SSC_CMR # 4 ;- Clock Mode Register
- # 8 ;- Reserved
-SSC_RCMR # 4 ;- Receive Clock ModeRegister
-SSC_RFMR # 4 ;- Receive Frame Mode Register
-SSC_TCMR # 4 ;- Transmit Clock Mode Register
-SSC_TFMR # 4 ;- Transmit Frame Mode Register
-SSC_RHR # 4 ;- Receive Holding Register
-SSC_THR # 4 ;- Transmit Holding Register
- # 8 ;- Reserved
-SSC_RSHR # 4 ;- Receive Sync Holding Register
-SSC_TSHR # 4 ;- Transmit Sync Holding Register
- # 8 ;- Reserved
-SSC_SR # 4 ;- Status Register
-SSC_IER # 4 ;- Interrupt Enable Register
-SSC_IDR # 4 ;- Interrupt Disable Register
-SSC_IMR # 4 ;- Interrupt Mask Register
- # 176 ;- Reserved
-SSC_RPR # 4 ;- Receive Pointer Register
-SSC_RCR # 4 ;- Receive Counter Register
-SSC_TPR # 4 ;- Transmit Pointer Register
-SSC_TCR # 4 ;- Transmit Counter Register
-SSC_RNPR # 4 ;- Receive Next Pointer Register
-SSC_RNCR # 4 ;- Receive Next Counter Register
-SSC_TNPR # 4 ;- Transmit Next Pointer Register
-SSC_TNCR # 4 ;- Transmit Next Counter Register
-SSC_PTCR # 4 ;- PDC Transfer Control Register
-SSC_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register --------
-AT91C_SSC_RXEN EQU (0x1:SHL:0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS EQU (0x1:SHL:1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN EQU (0x1:SHL:8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS EQU (0x1:SHL:9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST EQU (0x1:SHL:15) ;- (SSC) Software Reset
-;- -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register --------
-AT91C_SSC_CKS EQU (0x3:SHL:0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO EQU (0x7:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE EQU (0x0:SHL:2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS EQU (0x1:SHL:2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX EQU (0x2:SHL:2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI EQU (0x1:SHL:5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START EQU (0xF:SHL:8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0:SHL:8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX EQU (0x1:SHL:8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF EQU (0x2:SHL:8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF EQU (0x3:SHL:8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF EQU (0x4:SHL:8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF EQU (0x5:SHL:8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF EQU (0x6:SHL:8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF EQU (0x7:SHL:8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0 EQU (0x8:SHL:8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY EQU (0xFF:SHL:16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD EQU (0xFF:SHL:24) ;- (SSC) Receive/Transmit Period Divider Selection
-;- -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register --------
-AT91C_SSC_DATLEN EQU (0x1F:SHL:0) ;- (SSC) Data Length
-AT91C_SSC_LOOP EQU (0x1:SHL:5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF EQU (0x1:SHL:7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB EQU (0xF:SHL:8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN EQU (0xF:SHL:16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS EQU (0x7:SHL:20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE EQU (0x0:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE EQU (0x1:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE EQU (0x2:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW EQU (0x3:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH EQU (0x4:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE EQU (0x5:SHL:20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE EQU (0x1:SHL:24) ;- (SSC) Frame Sync Edge Detection
-;- -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register --------
-;- -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register --------
-AT91C_SSC_DATDEF EQU (0x1:SHL:5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN EQU (0x1:SHL:23) ;- (SSC) Frame Sync Data Enable
-;- -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register --------
-AT91C_SSC_TXRDY EQU (0x1:SHL:0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY EQU (0x1:SHL:1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX EQU (0x1:SHL:2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE EQU (0x1:SHL:3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY EQU (0x1:SHL:4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN EQU (0x1:SHL:5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX EQU (0x1:SHL:6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF EQU (0x1:SHL:7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN EQU (0x1:SHL:10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN EQU (0x1:SHL:11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA EQU (0x1:SHL:16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA EQU (0x1:SHL:17) ;- (SSC) Receive Enable
-;- -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register --------
-;- -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register --------
-;- -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Usart
-;- *****************************************************************************
- ^ 0 ;- AT91S_USART
-US_CR # 4 ;- Control Register
-US_MR # 4 ;- Mode Register
-US_IER # 4 ;- Interrupt Enable Register
-US_IDR # 4 ;- Interrupt Disable Register
-US_IMR # 4 ;- Interrupt Mask Register
-US_CSR # 4 ;- Channel Status Register
-US_RHR # 4 ;- Receiver Holding Register
-US_THR # 4 ;- Transmitter Holding Register
-US_BRGR # 4 ;- Baud Rate Generator Register
-US_RTOR # 4 ;- Receiver Time-out Register
-US_TTGR # 4 ;- Transmitter Time-guard Register
- # 20 ;- Reserved
-US_FIDI # 4 ;- FI_DI_Ratio Register
-US_NER # 4 ;- Nb Errors Register
- # 4 ;- Reserved
-US_IF # 4 ;- IRDA_FILTER Register
- # 176 ;- Reserved
-US_RPR # 4 ;- Receive Pointer Register
-US_RCR # 4 ;- Receive Counter Register
-US_TPR # 4 ;- Transmit Pointer Register
-US_TCR # 4 ;- Transmit Counter Register
-US_RNPR # 4 ;- Receive Next Pointer Register
-US_RNCR # 4 ;- Receive Next Counter Register
-US_TNPR # 4 ;- Transmit Next Pointer Register
-US_TNCR # 4 ;- Transmit Next Counter Register
-US_PTCR # 4 ;- PDC Transfer Control Register
-US_PTSR # 4 ;- PDC Transfer Status Register
-;- -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
-AT91C_US_STTBRK EQU (0x1:SHL:9) ;- (USART) Start Break
-AT91C_US_STPBRK EQU (0x1:SHL:10) ;- (USART) Stop Break
-AT91C_US_STTTO EQU (0x1:SHL:11) ;- (USART) Start Time-out
-AT91C_US_SENDA EQU (0x1:SHL:12) ;- (USART) Send Address
-AT91C_US_RSTIT EQU (0x1:SHL:13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK EQU (0x1:SHL:14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO EQU (0x1:SHL:15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN EQU (0x1:SHL:16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS EQU (0x1:SHL:17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN EQU (0x1:SHL:18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS EQU (0x1:SHL:19) ;- (USART) Request to Send Disable
-;- -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
-AT91C_US_USMODE EQU (0xF:SHL:0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS EQU (0x3:SHL:4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK EQU (0x0:SHL:4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1 EQU (0x1:SHL:4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW EQU (0x2:SHL:4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT EQU (0x3:SHL:4) ;- (USART) External (SCK)
-AT91C_US_CHRL EQU (0x3:SHL:6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS EQU (0x0:SHL:6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS EQU (0x1:SHL:6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS EQU (0x2:SHL:6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS EQU (0x3:SHL:6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC EQU (0x1:SHL:8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP EQU (0x3:SHL:12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT EQU (0x0:SHL:12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT EQU (0x1:SHL:12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT EQU (0x2:SHL:12) ;- (USART) 2 stop bits
-AT91C_US_MSBF EQU (0x1:SHL:16) ;- (USART) Bit Order
-AT91C_US_MODE9 EQU (0x1:SHL:17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO EQU (0x1:SHL:18) ;- (USART) Clock Output Select
-AT91C_US_OVER EQU (0x1:SHL:19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK EQU (0x1:SHL:20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK EQU (0x1:SHL:21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER EQU (0x1:SHL:24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER EQU (0x1:SHL:28) ;- (USART) Receive Line Filter
-;- -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
-AT91C_US_RXBRK EQU (0x1:SHL:2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT EQU (0x1:SHL:8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION EQU (0x1:SHL:10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK EQU (0x1:SHL:13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC EQU (0x1:SHL:16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC EQU (0x1:SHL:17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC EQU (0x1:SHL:18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC EQU (0x1:SHL:19) ;- (USART) Clear To Send Input Change Flag
-;- -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
-;- -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
-;- -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
-AT91C_US_RI EQU (0x1:SHL:20) ;- (USART) Image of RI Input
-AT91C_US_DSR EQU (0x1:SHL:21) ;- (USART) Image of DSR Input
-AT91C_US_DCD EQU (0x1:SHL:22) ;- (USART) Image of DCD Input
-AT91C_US_CTS EQU (0x1:SHL:23) ;- (USART) Image of CTS Input
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Two-wire Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_TWI
-TWI_CR # 4 ;- Control Register
-TWI_MMR # 4 ;- Master Mode Register
- # 4 ;- Reserved
-TWI_IADR # 4 ;- Internal Address Register
-TWI_CWGR # 4 ;- Clock Waveform Generator Register
- # 12 ;- Reserved
-TWI_SR # 4 ;- Status Register
-TWI_IER # 4 ;- Interrupt Enable Register
-TWI_IDR # 4 ;- Interrupt Disable Register
-TWI_IMR # 4 ;- Interrupt Mask Register
-TWI_RHR # 4 ;- Receive Holding Register
-TWI_THR # 4 ;- Transmit Holding Register
-;- -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register --------
-AT91C_TWI_START EQU (0x1:SHL:0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP EQU (0x1:SHL:1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN EQU (0x1:SHL:2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS EQU (0x1:SHL:3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST EQU (0x1:SHL:7) ;- (TWI) Software Reset
-;- -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register --------
-AT91C_TWI_IADRSZ EQU (0x3:SHL:8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO EQU (0x0:SHL:8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE EQU (0x1:SHL:8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE EQU (0x2:SHL:8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE EQU (0x3:SHL:8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD EQU (0x1:SHL:12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR EQU (0x7F:SHL:16) ;- (TWI) Device Address
-;- -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register --------
-AT91C_TWI_CLDIV EQU (0xFF:SHL:0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV EQU (0xFF:SHL:8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV EQU (0x7:SHL:16) ;- (TWI) Clock Divider
-;- -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register --------
-AT91C_TWI_TXCOMP EQU (0x1:SHL:0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY EQU (0x1:SHL:1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY EQU (0x1:SHL:2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE EQU (0x1:SHL:6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE EQU (0x1:SHL:7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK EQU (0x1:SHL:8) ;- (TWI) Not Acknowledged
-;- -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register --------
-;- -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register --------
-;- -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_TC
-TC_CCR # 4 ;- Channel Control Register
-TC_CMR # 4 ;- Channel Mode Register (Capture Mode / Waveform Mode)
- # 8 ;- Reserved
-TC_CV # 4 ;- Counter Value
-TC_RA # 4 ;- Register A
-TC_RB # 4 ;- Register B
-TC_RC # 4 ;- Register C
-TC_SR # 4 ;- Status Register
-TC_IER # 4 ;- Interrupt Enable Register
-TC_IDR # 4 ;- Interrupt Disable Register
-TC_IMR # 4 ;- Interrupt Mask Register
-;- -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
-AT91C_TC_CLKEN EQU (0x1:SHL:0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS EQU (0x1:SHL:1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG EQU (0x1:SHL:2) ;- (TC) Software Trigger Command
-;- -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
-AT91C_TC_CLKS EQU (0x7:SHL:0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI EQU (0x1:SHL:3) ;- (TC) Clock Invert
-AT91C_TC_BURST EQU (0x3:SHL:4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE EQU (0x0:SHL:4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0 EQU (0x1:SHL:4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1 EQU (0x2:SHL:4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2 EQU (0x3:SHL:4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP EQU (0x1:SHL:6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS EQU (0x1:SHL:7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG EQU (0x3:SHL:8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG EQU (0x3:SHL:8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE EQU (0x0:SHL:8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING EQU (0x1:SHL:8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING EQU (0x2:SHL:8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH EQU (0x3:SHL:8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT EQU (0x3:SHL:10) ;- (TC) External Event Selection
-AT91C_TC_EEVT_TIOB EQU (0x0:SHL:10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0 EQU (0x1:SHL:10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1 EQU (0x2:SHL:10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2 EQU (0x3:SHL:10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG EQU (0x1:SHL:10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG EQU (0x1:SHL:12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL EQU (0x3:SHL:13) ;- (TC) Waveform Selection
-AT91C_TC_WAVESEL_UP EQU (0x0:SHL:13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN EQU (0x1:SHL:13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO EQU (0x2:SHL:13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3:SHL:13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG EQU (0x1:SHL:14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE EQU (0x1:SHL:15) ;- (TC)
-AT91C_TC_ACPA EQU (0x3:SHL:16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE EQU (0x0:SHL:16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET EQU (0x1:SHL:16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR EQU (0x2:SHL:16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE EQU (0x3:SHL:16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA EQU (0x3:SHL:16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE EQU (0x0:SHL:16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING EQU (0x1:SHL:16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING EQU (0x2:SHL:16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH EQU (0x3:SHL:16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC EQU (0x3:SHL:18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE EQU (0x0:SHL:18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET EQU (0x1:SHL:18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR EQU (0x2:SHL:18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE EQU (0x3:SHL:18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB EQU (0x3:SHL:18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE EQU (0x0:SHL:18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING EQU (0x1:SHL:18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING EQU (0x2:SHL:18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH EQU (0x3:SHL:18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT EQU (0x3:SHL:20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE EQU (0x0:SHL:20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET EQU (0x1:SHL:20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR EQU (0x2:SHL:20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE EQU (0x3:SHL:20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG EQU (0x3:SHL:22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE EQU (0x0:SHL:22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET EQU (0x1:SHL:22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR EQU (0x2:SHL:22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE EQU (0x3:SHL:22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB EQU (0x3:SHL:24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE EQU (0x0:SHL:24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET EQU (0x1:SHL:24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR EQU (0x2:SHL:24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE EQU (0x3:SHL:24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC EQU (0x3:SHL:26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE EQU (0x0:SHL:26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET EQU (0x1:SHL:26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR EQU (0x2:SHL:26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE EQU (0x3:SHL:26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT EQU (0x3:SHL:28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE EQU (0x0:SHL:28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET EQU (0x1:SHL:28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR EQU (0x2:SHL:28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE EQU (0x3:SHL:28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG EQU (0x3:SHL:30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE EQU (0x0:SHL:30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET EQU (0x1:SHL:30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR EQU (0x2:SHL:30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE EQU (0x3:SHL:30) ;- (TC) Effect: toggle
-;- -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
-AT91C_TC_COVFS EQU (0x1:SHL:0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS EQU (0x1:SHL:1) ;- (TC) Load Overrun
-AT91C_TC_CPAS EQU (0x1:SHL:2) ;- (TC) RA Compare
-AT91C_TC_CPBS EQU (0x1:SHL:3) ;- (TC) RB Compare
-AT91C_TC_CPCS EQU (0x1:SHL:4) ;- (TC) RC Compare
-AT91C_TC_LDRAS EQU (0x1:SHL:5) ;- (TC) RA Loading
-AT91C_TC_LDRBS EQU (0x1:SHL:6) ;- (TC) RB Loading
-AT91C_TC_ETRGS EQU (0x1:SHL:7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA EQU (0x1:SHL:16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA EQU (0x1:SHL:17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB EQU (0x1:SHL:18) ;- (TC) TIOA Mirror
-;- -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
-;- -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
-;- -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Timer Counter Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_TCB
-TCB_TC0 # 48 ;- TC Channel 0
- # 16 ;- Reserved
-TCB_TC1 # 48 ;- TC Channel 1
- # 16 ;- Reserved
-TCB_TC2 # 48 ;- TC Channel 2
- # 16 ;- Reserved
-TCB_BCR # 4 ;- TC Block Control Register
-TCB_BMR # 4 ;- TC Block Mode Register
-;- -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
-AT91C_TCB_SYNC EQU (0x1:SHL:0) ;- (TCB) Synchro Command
-;- -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
-AT91C_TCB_TC0XC0S EQU (0x3:SHL:0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S EQU (0x3:SHL:2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0:SHL:2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE EQU (0x1:SHL:2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2:SHL:2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3:SHL:2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S EQU (0x3:SHL:4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0:SHL:4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE EQU (0x1:SHL:4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2:SHL:4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3:SHL:4) ;- (TCB) TIOA2 connected to XC2
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR PWMC Channel Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_PWMC_CH
-PWMC_CMR # 4 ;- Channel Mode Register
-PWMC_CDTYR # 4 ;- Channel Duty Cycle Register
-PWMC_CPRDR # 4 ;- Channel Period Register
-PWMC_CCNTR # 4 ;- Channel Counter Register
-PWMC_CUPDR # 4 ;- Channel Update Register
-PWMC_Reserved # 12 ;- Reserved
-;- -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register --------
-AT91C_PWMC_CPRE EQU (0xF:SHL:0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH)
-AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH)
-AT91C_PWMC_CALG EQU (0x1:SHL:8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL EQU (0x1:SHL:9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD EQU (0x1:SHL:10) ;- (PWMC_CH) Channel Update Period
-;- -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register --------
-AT91C_PWMC_CDTY EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Duty Cycle
-;- -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register --------
-AT91C_PWMC_CPRD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Period
-;- -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register --------
-AT91C_PWMC_CCNT EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Counter
-;- -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register --------
-AT91C_PWMC_CUPD EQU (0x0:SHL:0) ;- (PWMC_CH) Channel Update
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_PWMC
-PWMC_MR # 4 ;- PWMC Mode Register
-PWMC_ENA # 4 ;- PWMC Enable Register
-PWMC_DIS # 4 ;- PWMC Disable Register
-PWMC_SR # 4 ;- PWMC Status Register
-PWMC_IER # 4 ;- PWMC Interrupt Enable Register
-PWMC_IDR # 4 ;- PWMC Interrupt Disable Register
-PWMC_IMR # 4 ;- PWMC Interrupt Mask Register
-PWMC_ISR # 4 ;- PWMC Interrupt Status Register
- # 220 ;- Reserved
-PWMC_VR # 4 ;- PWMC Version Register
- # 256 ;- Reserved
-PWMC_CH # 96 ;- PWMC Channel
-;- -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register --------
-AT91C_PWMC_DIVA EQU (0xFF:SHL:0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA EQU (0xF:SHL:8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK EQU (0x0:SHL:8) ;- (PWMC)
-AT91C_PWMC_DIVB EQU (0xFF:SHL:16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB EQU (0xF:SHL:24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK EQU (0x0:SHL:24) ;- (PWMC)
-;- -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register --------
-AT91C_PWMC_CHID0 EQU (0x1:SHL:0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1 EQU (0x1:SHL:1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2 EQU (0x1:SHL:2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3 EQU (0x1:SHL:3) ;- (PWMC) Channel ID 3
-;- -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register --------
-;- -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register --------
-;- -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register --------
-;- -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register --------
-;- -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register --------
-;- -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register --------
-
-;- *****************************************************************************
-;- SOFTWARE API DEFINITION FOR USB Device Interface
-;- *****************************************************************************
- ^ 0 ;- AT91S_UDP
-UDP_NUM # 4 ;- Frame Number Register
-UDP_GLBSTATE # 4 ;- Global State Register
-UDP_FADDR # 4 ;- Function Address Register
- # 4 ;- Reserved
-UDP_IER # 4 ;- Interrupt Enable Register
-UDP_IDR # 4 ;- Interrupt Disable Register
-UDP_IMR # 4 ;- Interrupt Mask Register
-UDP_ISR # 4 ;- Interrupt Status Register
-UDP_ICR # 4 ;- Interrupt Clear Register
- # 4 ;- Reserved
-UDP_RSTEP # 4 ;- Reset Endpoint Register
- # 4 ;- Reserved
-UDP_CSR # 16 ;- Endpoint Control and Status Register
- # 16 ;- Reserved
-UDP_FDR # 16 ;- Endpoint FIFO Data Register
- # 20 ;- Reserved
-UDP_TXVC # 4 ;- Transceiver Control Register
-;- -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register --------
-AT91C_UDP_FRM_NUM EQU (0x7FF:SHL:0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR EQU (0x1:SHL:16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK EQU (0x1:SHL:17) ;- (UDP) Frame OK
-;- -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register --------
-AT91C_UDP_FADDEN EQU (0x1:SHL:0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG EQU (0x1:SHL:1) ;- (UDP) Configured
-AT91C_UDP_ESR EQU (0x1:SHL:2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR EQU (0x1:SHL:3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE EQU (0x1:SHL:4) ;- (UDP) Remote Wake Up Enable
-;- -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register --------
-AT91C_UDP_FADD EQU (0xFF:SHL:0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN EQU (0x1:SHL:8) ;- (UDP) Function Enable
-;- -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register --------
-AT91C_UDP_EPINT0 EQU (0x1:SHL:0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1 EQU (0x1:SHL:1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2 EQU (0x1:SHL:2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3 EQU (0x1:SHL:3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_RXSUSP EQU (0x1:SHL:8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM EQU (0x1:SHL:9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM EQU (0x1:SHL:10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT EQU (0x1:SHL:11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP EQU (0x1:SHL:13) ;- (UDP) USB Resume Interrupt
-;- -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register --------
-;- -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register --------
-;- -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register --------
-AT91C_UDP_ENDBUSRES EQU (0x1:SHL:12) ;- (UDP) USB End Of Bus Reset Interrupt
-;- -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register --------
-;- -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register --------
-AT91C_UDP_EP0 EQU (0x1:SHL:0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1 EQU (0x1:SHL:1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2 EQU (0x1:SHL:2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3 EQU (0x1:SHL:3) ;- (UDP) Reset Endpoint 3
-;- -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register --------
-AT91C_UDP_TXCOMP EQU (0x1:SHL:0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0 EQU (0x1:SHL:1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP EQU (0x1:SHL:2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR EQU (0x1:SHL:3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY EQU (0x1:SHL:4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL EQU (0x1:SHL:5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1 EQU (0x1:SHL:6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR EQU (0x1:SHL:7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE EQU (0x7:SHL:8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL EQU (0x0:SHL:8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1:SHL:8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2:SHL:8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT EQU (0x3:SHL:8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN EQU (0x5:SHL:8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN EQU (0x6:SHL:8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN EQU (0x7:SHL:8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE EQU (0x1:SHL:11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS EQU (0x1:SHL:15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT EQU (0x7FF:SHL:16) ;- (UDP) Number Of Bytes Available in the FIFO
-;- -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register --------
-AT91C_UDP_TXVDIS EQU (0x1:SHL:8) ;- (UDP)
-
-;- *****************************************************************************
-;- REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-;- *****************************************************************************
-;- ========== Register definition for SYS peripheral ==========
-;- ========== Register definition for AIC peripheral ==========
-AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-;- ========== Register definition for PDC_DBGU peripheral ==========
-AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-;- ========== Register definition for DBGU peripheral ==========
-AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-;- ========== Register definition for PIOA peripheral ==========
-AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-;- ========== Register definition for CKGR peripheral ==========
-AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register
-;- ========== Register definition for PMC peripheral ==========
-AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register
-AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register
-;- ========== Register definition for RSTC peripheral ==========
-AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-;- ========== Register definition for RTTC peripheral ==========
-AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-;- ========== Register definition for PITC peripheral ==========
-AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-;- ========== Register definition for WDTC peripheral ==========
-AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-;- ========== Register definition for VREG peripheral ==========
-AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-;- ========== Register definition for MC peripheral ==========
-AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-;- ========== Register definition for PDC_SPI peripheral ==========
-AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register
-AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register
-AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register
-AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register
-AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register
-AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register
-AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register
-AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register
-AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register
-AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register
-;- ========== Register definition for SPI peripheral ==========
-AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register
-AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register
-AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register
-AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register
-AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register
-AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register
-AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register
-AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register
-AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register
-;- ========== Register definition for PDC_ADC peripheral ==========
-AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-;- ========== Register definition for ADC peripheral ==========
-AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-;- ========== Register definition for PDC_SSC peripheral ==========
-AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-;- ========== Register definition for SSC peripheral ==========
-AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-;- ========== Register definition for PDC_US1 peripheral ==========
-AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-;- ========== Register definition for US1 peripheral ==========
-AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register
-;- ========== Register definition for PDC_US0 peripheral ==========
-AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-;- ========== Register definition for US0 peripheral ==========
-AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-;- ========== Register definition for TWI peripheral ==========
-AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-;- ========== Register definition for TC0 peripheral ==========
-AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-;- ========== Register definition for TC1 peripheral ==========
-AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value
-;- ========== Register definition for TC2 peripheral ==========
-AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register
-;- ========== Register definition for TCB peripheral ==========
-AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-;- ========== Register definition for PWMC_CH3 peripheral ==========
-AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-;- ========== Register definition for PWMC_CH2 peripheral ==========
-AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-;- ========== Register definition for PWMC_CH1 peripheral ==========
-AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-;- ========== Register definition for PWMC_CH0 peripheral ==========
-AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-;- ========== Register definition for PWMC peripheral ==========
-AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-;- ========== Register definition for UDP peripheral ==========
-AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-
-;- *****************************************************************************
-;- PIO DEFINITIONS FOR AT91SAM7S64
-;- *****************************************************************************
-AT91C_PIO_PA0 EQU (1:SHL:0) ;- Pin Controlled by PA0
-AT91C_PA0_PWM0 EQU (AT91C_PIO_PA0) ;- PWM Channel 0
-AT91C_PA0_TIOA0 EQU (AT91C_PIO_PA0) ;- Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA1 EQU (1:SHL:1) ;- Pin Controlled by PA1
-AT91C_PA1_PWM1 EQU (AT91C_PIO_PA1) ;- PWM Channel 1
-AT91C_PA1_TIOB0 EQU (AT91C_PIO_PA1) ;- Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA10 EQU (1:SHL:10) ;- Pin Controlled by PA10
-AT91C_PA10_DTXD EQU (AT91C_PIO_PA10) ;- DBGU Debug Transmit Data
-AT91C_PA10_NPCS2 EQU (AT91C_PIO_PA10) ;- SPI Peripheral Chip Select 2
-AT91C_PIO_PA11 EQU (1:SHL:11) ;- Pin Controlled by PA11
-AT91C_PA11_NPCS0 EQU (AT91C_PIO_PA11) ;- SPI Peripheral Chip Select 0
-AT91C_PA11_PWM0 EQU (AT91C_PIO_PA11) ;- PWM Channel 0
-AT91C_PIO_PA12 EQU (1:SHL:12) ;- Pin Controlled by PA12
-AT91C_PA12_MISO EQU (AT91C_PIO_PA12) ;- SPI Master In Slave
-AT91C_PA12_PWM1 EQU (AT91C_PIO_PA12) ;- PWM Channel 1
-AT91C_PIO_PA13 EQU (1:SHL:13) ;- Pin Controlled by PA13
-AT91C_PA13_MOSI EQU (AT91C_PIO_PA13) ;- SPI Master Out Slave
-AT91C_PA13_PWM2 EQU (AT91C_PIO_PA13) ;- PWM Channel 2
-AT91C_PIO_PA14 EQU (1:SHL:14) ;- Pin Controlled by PA14
-AT91C_PA14_SPCK EQU (AT91C_PIO_PA14) ;- SPI Serial Clock
-AT91C_PA14_PWM3 EQU (AT91C_PIO_PA14) ;- PWM Channel 3
-AT91C_PIO_PA15 EQU (1:SHL:15) ;- Pin Controlled by PA15
-AT91C_PA15_TF EQU (AT91C_PIO_PA15) ;- SSC Transmit Frame Sync
-AT91C_PA15_TIOA1 EQU (AT91C_PIO_PA15) ;- Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA16 EQU (1:SHL:16) ;- Pin Controlled by PA16
-AT91C_PA16_TK EQU (AT91C_PIO_PA16) ;- SSC Transmit Clock
-AT91C_PA16_TIOB1 EQU (AT91C_PIO_PA16) ;- Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA17 EQU (1:SHL:17) ;- Pin Controlled by PA17
-AT91C_PA17_TD EQU (AT91C_PIO_PA17) ;- SSC Transmit data
-AT91C_PA17_PCK1 EQU (AT91C_PIO_PA17) ;- PMC Programmable Clock Output 1
-AT91C_PIO_PA18 EQU (1:SHL:18) ;- Pin Controlled by PA18
-AT91C_PA18_RD EQU (AT91C_PIO_PA18) ;- SSC Receive Data
-AT91C_PA18_PCK2 EQU (AT91C_PIO_PA18) ;- PMC Programmable Clock Output 2
-AT91C_PIO_PA19 EQU (1:SHL:19) ;- Pin Controlled by PA19
-AT91C_PA19_RK EQU (AT91C_PIO_PA19) ;- SSC Receive Clock
-AT91C_PA19_FIQ EQU (AT91C_PIO_PA19) ;- AIC Fast Interrupt Input
-AT91C_PIO_PA2 EQU (1:SHL:2) ;- Pin Controlled by PA2
-AT91C_PA2_PWM2 EQU (AT91C_PIO_PA2) ;- PWM Channel 2
-AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock
-AT91C_PIO_PA20 EQU (1:SHL:20) ;- Pin Controlled by PA20
-AT91C_PA20_RF EQU (AT91C_PIO_PA20) ;- SSC Receive Frame Sync
-AT91C_PA20_IRQ0 EQU (AT91C_PIO_PA20) ;- External Interrupt 0
-AT91C_PIO_PA21 EQU (1:SHL:21) ;- Pin Controlled by PA21
-AT91C_PA21_RXD1 EQU (AT91C_PIO_PA21) ;- USART 1 Receive Data
-AT91C_PA21_PCK1 EQU (AT91C_PIO_PA21) ;- PMC Programmable Clock Output 1
-AT91C_PIO_PA22 EQU (1:SHL:22) ;- Pin Controlled by PA22
-AT91C_PA22_TXD1 EQU (AT91C_PIO_PA22) ;- USART 1 Transmit Data
-AT91C_PA22_NPCS3 EQU (AT91C_PIO_PA22) ;- SPI Peripheral Chip Select 3
-AT91C_PIO_PA23 EQU (1:SHL:23) ;- Pin Controlled by PA23
-AT91C_PA23_SCK1 EQU (AT91C_PIO_PA23) ;- USART 1 Serial Clock
-AT91C_PA23_PWM0 EQU (AT91C_PIO_PA23) ;- PWM Channel 0
-AT91C_PIO_PA24 EQU (1:SHL:24) ;- Pin Controlled by PA24
-AT91C_PA24_RTS1 EQU (AT91C_PIO_PA24) ;- USART 1 Ready To Send
-AT91C_PA24_PWM1 EQU (AT91C_PIO_PA24) ;- PWM Channel 1
-AT91C_PIO_PA25 EQU (1:SHL:25) ;- Pin Controlled by PA25
-AT91C_PA25_CTS1 EQU (AT91C_PIO_PA25) ;- USART 1 Clear To Send
-AT91C_PA25_PWM2 EQU (AT91C_PIO_PA25) ;- PWM Channel 2
-AT91C_PIO_PA26 EQU (1:SHL:26) ;- Pin Controlled by PA26
-AT91C_PA26_DCD1 EQU (AT91C_PIO_PA26) ;- USART 1 Data Carrier Detect
-AT91C_PA26_TIOA2 EQU (AT91C_PIO_PA26) ;- Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PIO_PA27 EQU (1:SHL:27) ;- Pin Controlled by PA27
-AT91C_PA27_DTR1 EQU (AT91C_PIO_PA27) ;- USART 1 Data Terminal ready
-AT91C_PA27_TIOB2 EQU (AT91C_PIO_PA27) ;- Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PIO_PA28 EQU (1:SHL:28) ;- Pin Controlled by PA28
-AT91C_PA28_DSR1 EQU (AT91C_PIO_PA28) ;- USART 1 Data Set ready
-AT91C_PA28_TCLK1 EQU (AT91C_PIO_PA28) ;- Timer Counter 1 external clock input
-AT91C_PIO_PA29 EQU (1:SHL:29) ;- Pin Controlled by PA29
-AT91C_PA29_RI1 EQU (AT91C_PIO_PA29) ;- USART 1 Ring Indicator
-AT91C_PA29_TCLK2 EQU (AT91C_PIO_PA29) ;- Timer Counter 2 external clock input
-AT91C_PIO_PA3 EQU (1:SHL:3) ;- Pin Controlled by PA3
-AT91C_PA3_TWD EQU (AT91C_PIO_PA3) ;- TWI Two-wire Serial Data
-AT91C_PA3_NPCS3 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 3
-AT91C_PIO_PA30 EQU (1:SHL:30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ1 EQU (AT91C_PIO_PA30) ;- External Interrupt 1
-AT91C_PA30_NPCS2 EQU (AT91C_PIO_PA30) ;- SPI Peripheral Chip Select 2
-AT91C_PIO_PA31 EQU (1:SHL:31) ;- Pin Controlled by PA31
-AT91C_PA31_NPCS1 EQU (AT91C_PIO_PA31) ;- SPI Peripheral Chip Select 1
-AT91C_PA31_PCK2 EQU (AT91C_PIO_PA31) ;- PMC Programmable Clock Output 2
-AT91C_PIO_PA4 EQU (1:SHL:4) ;- Pin Controlled by PA4
-AT91C_PA4_TWCK EQU (AT91C_PIO_PA4) ;- TWI Two-wire Serial Clock
-AT91C_PA4_TCLK0 EQU (AT91C_PIO_PA4) ;- Timer Counter 0 external clock input
-AT91C_PIO_PA5 EQU (1:SHL:5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD0 EQU (AT91C_PIO_PA5) ;- USART 0 Receive Data
-AT91C_PA5_NPCS3 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 3
-AT91C_PIO_PA6 EQU (1:SHL:6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD0 EQU (AT91C_PIO_PA6) ;- USART 0 Transmit Data
-AT91C_PA6_PCK0 EQU (AT91C_PIO_PA6) ;- PMC Programmable Clock Output 0
-AT91C_PIO_PA7 EQU (1:SHL:7) ;- Pin Controlled by PA7
-AT91C_PA7_RTS0 EQU (AT91C_PIO_PA7) ;- USART 0 Ready To Send
-AT91C_PA7_PWM3 EQU (AT91C_PIO_PA7) ;- PWM Channel 3
-AT91C_PIO_PA8 EQU (1:SHL:8) ;- Pin Controlled by PA8
-AT91C_PA8_CTS0 EQU (AT91C_PIO_PA8) ;- USART 0 Clear To Send
-AT91C_PA8_ADTRG EQU (AT91C_PIO_PA8) ;- ADC External Trigger
-AT91C_PIO_PA9 EQU (1:SHL:9) ;- Pin Controlled by PA9
-AT91C_PA9_DRXD EQU (AT91C_PIO_PA9) ;- DBGU Debug Receive Data
-AT91C_PA9_NPCS1 EQU (AT91C_PIO_PA9) ;- SPI Peripheral Chip Select 1
-
-;- *****************************************************************************
-;- PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-;- *****************************************************************************
-AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller
-AT91C_ID_3_Reserved EQU ( 3) ;- Reserved
-AT91C_ID_ADC EQU ( 4) ;- Analog-to-Digital Converter
-AT91C_ID_SPI EQU ( 5) ;- Serial Peripheral Interface
-AT91C_ID_US0 EQU ( 6) ;- USART 0
-AT91C_ID_US1 EQU ( 7) ;- USART 1
-AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC EQU (10) ;- PWM Controller
-AT91C_ID_UDP EQU (11) ;- USB Device Port
-AT91C_ID_TC0 EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1 EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2 EQU (14) ;- Timer Counter 2
-AT91C_ID_15_Reserved EQU (15) ;- Reserved
-AT91C_ID_16_Reserved EQU (16) ;- Reserved
-AT91C_ID_17_Reserved EQU (17) ;- Reserved
-AT91C_ID_18_Reserved EQU (18) ;- Reserved
-AT91C_ID_19_Reserved EQU (19) ;- Reserved
-AT91C_ID_20_Reserved EQU (20) ;- Reserved
-AT91C_ID_21_Reserved EQU (21) ;- Reserved
-AT91C_ID_22_Reserved EQU (22) ;- Reserved
-AT91C_ID_23_Reserved EQU (23) ;- Reserved
-AT91C_ID_24_Reserved EQU (24) ;- Reserved
-AT91C_ID_25_Reserved EQU (25) ;- Reserved
-AT91C_ID_26_Reserved EQU (26) ;- Reserved
-AT91C_ID_27_Reserved EQU (27) ;- Reserved
-AT91C_ID_28_Reserved EQU (28) ;- Reserved
-AT91C_ID_29_Reserved EQU (29) ;- Reserved
-AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-AT91C_ALL_INT EQU (0xC0007FF7) ;- ALL VALID INTERRUPTS
-
-;- *****************************************************************************
-;- BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-;- *****************************************************************************
-AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address
-AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address
-AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address
-
-;- *****************************************************************************
-;- MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-;- *****************************************************************************
-;- ISRAM
-AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbytes)
-;- IFLASH
-AT91C_IFLASH EQU (0x00100000) ;- Internal FLASH base address
-AT91C_IFLASH_SIZE EQU (0x00010000) ;- Internal FLASH size in byte (64 Kbytes)
-AT91C_IFLASH_PAGE_SIZE EQU (128) ;- Internal FLASH Page Size: 128 bytes
-AT91C_IFLASH_LOCK_REGION_SIZE EQU (4096) ;- Internal FLASH Lock Region Size: 4 Kbytes
-AT91C_IFLASH_NB_OF_PAGES EQU (256) ;- Internal FLASH Number of Pages: 256 bytes
-AT91C_IFLASH_NB_OF_LOCK_BITS EQU (8) ;- Internal FLASH Number of Lock Bits: 8 bytes
-
-
- END
diff --git a/openpcd/firmware/include/old/AT91SAM7S64.rdf b/openpcd/firmware/include/old/AT91SAM7S64.rdf deleted file mode 100644 index fbd0fe9..0000000 --- a/openpcd/firmware/include/old/AT91SAM7S64.rdf +++ /dev/null @@ -1,3104 +0,0 @@ -# ----------------------------------------------------------------------------
-# ATMEL Microcontroller Software Support - ROUSSET -
-# ----------------------------------------------------------------------------
-# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-# ----------------------------------------------------------------------------
-# File Name : AT91SAM7S64.h
-# Object : AT91SAM7S64 definitions
-# Generated : AT91 SW Application Group 08/30/2005 (15:53:00)
-#
-# CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//
-# CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
-# CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//
-# CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
-# CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//
-# CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//
-# CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//
-# CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-# CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-# CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-# CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-# CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-# CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-# CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-# CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-# CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-# CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-# CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-# CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-# CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-# CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-# ----------------------------------------------------------------------------
-
-rdf.version=1
-
-~sysinclude=arm_default.rdf
-~sysinclude=arm_status.rdf
-# ========== Register definition for SYS peripheral ==========
-# ========== Register definition for AIC peripheral ==========
-AT91C_AIC_IVR.name="AT91C_AIC_IVR"
-AT91C_AIC_IVR.description="IRQ Vector Register"
-AT91C_AIC_IVR.helpkey="IRQ Vector Register"
-AT91C_AIC_IVR.access=memorymapped
-AT91C_AIC_IVR.address=0xFFFFF100
-AT91C_AIC_IVR.width=32
-AT91C_AIC_IVR.byteEndian=little
-AT91C_AIC_IVR.permission.write=none
-AT91C_AIC_SMR.name="AT91C_AIC_SMR"
-AT91C_AIC_SMR.description="Source Mode Register"
-AT91C_AIC_SMR.helpkey="Source Mode Register"
-AT91C_AIC_SMR.access=memorymapped
-AT91C_AIC_SMR.address=0xFFFFF000
-AT91C_AIC_SMR.width=32
-AT91C_AIC_SMR.byteEndian=little
-AT91C_AIC_FVR.name="AT91C_AIC_FVR"
-AT91C_AIC_FVR.description="FIQ Vector Register"
-AT91C_AIC_FVR.helpkey="FIQ Vector Register"
-AT91C_AIC_FVR.access=memorymapped
-AT91C_AIC_FVR.address=0xFFFFF104
-AT91C_AIC_FVR.width=32
-AT91C_AIC_FVR.byteEndian=little
-AT91C_AIC_FVR.permission.write=none
-AT91C_AIC_DCR.name="AT91C_AIC_DCR"
-AT91C_AIC_DCR.description="Debug Control Register (Protect)"
-AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
-AT91C_AIC_DCR.access=memorymapped
-AT91C_AIC_DCR.address=0xFFFFF138
-AT91C_AIC_DCR.width=32
-AT91C_AIC_DCR.byteEndian=little
-AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
-AT91C_AIC_EOICR.description="End of Interrupt Command Register"
-AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
-AT91C_AIC_EOICR.access=memorymapped
-AT91C_AIC_EOICR.address=0xFFFFF130
-AT91C_AIC_EOICR.width=32
-AT91C_AIC_EOICR.byteEndian=little
-AT91C_AIC_EOICR.type=enum
-AT91C_AIC_EOICR.enum.0.name=*** Write only ***
-AT91C_AIC_EOICR.enum.1.name=Error
-AT91C_AIC_SVR.name="AT91C_AIC_SVR"
-AT91C_AIC_SVR.description="Source Vector Register"
-AT91C_AIC_SVR.helpkey="Source Vector Register"
-AT91C_AIC_SVR.access=memorymapped
-AT91C_AIC_SVR.address=0xFFFFF080
-AT91C_AIC_SVR.width=32
-AT91C_AIC_SVR.byteEndian=little
-AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
-AT91C_AIC_FFSR.description="Fast Forcing Status Register"
-AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
-AT91C_AIC_FFSR.access=memorymapped
-AT91C_AIC_FFSR.address=0xFFFFF148
-AT91C_AIC_FFSR.width=32
-AT91C_AIC_FFSR.byteEndian=little
-AT91C_AIC_FFSR.permission.write=none
-AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
-AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
-AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
-AT91C_AIC_ICCR.access=memorymapped
-AT91C_AIC_ICCR.address=0xFFFFF128
-AT91C_AIC_ICCR.width=32
-AT91C_AIC_ICCR.byteEndian=little
-AT91C_AIC_ICCR.type=enum
-AT91C_AIC_ICCR.enum.0.name=*** Write only ***
-AT91C_AIC_ICCR.enum.1.name=Error
-AT91C_AIC_ISR.name="AT91C_AIC_ISR"
-AT91C_AIC_ISR.description="Interrupt Status Register"
-AT91C_AIC_ISR.helpkey="Interrupt Status Register"
-AT91C_AIC_ISR.access=memorymapped
-AT91C_AIC_ISR.address=0xFFFFF108
-AT91C_AIC_ISR.width=32
-AT91C_AIC_ISR.byteEndian=little
-AT91C_AIC_ISR.permission.write=none
-AT91C_AIC_IMR.name="AT91C_AIC_IMR"
-AT91C_AIC_IMR.description="Interrupt Mask Register"
-AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
-AT91C_AIC_IMR.access=memorymapped
-AT91C_AIC_IMR.address=0xFFFFF110
-AT91C_AIC_IMR.width=32
-AT91C_AIC_IMR.byteEndian=little
-AT91C_AIC_IMR.permission.write=none
-AT91C_AIC_IPR.name="AT91C_AIC_IPR"
-AT91C_AIC_IPR.description="Interrupt Pending Register"
-AT91C_AIC_IPR.helpkey="Interrupt Pending Register"
-AT91C_AIC_IPR.access=memorymapped
-AT91C_AIC_IPR.address=0xFFFFF10C
-AT91C_AIC_IPR.width=32
-AT91C_AIC_IPR.byteEndian=little
-AT91C_AIC_IPR.permission.write=none
-AT91C_AIC_FFER.name="AT91C_AIC_FFER"
-AT91C_AIC_FFER.description="Fast Forcing Enable Register"
-AT91C_AIC_FFER.helpkey="Fast Forcing Enable Register"
-AT91C_AIC_FFER.access=memorymapped
-AT91C_AIC_FFER.address=0xFFFFF140
-AT91C_AIC_FFER.width=32
-AT91C_AIC_FFER.byteEndian=little
-AT91C_AIC_FFER.type=enum
-AT91C_AIC_FFER.enum.0.name=*** Write only ***
-AT91C_AIC_FFER.enum.1.name=Error
-AT91C_AIC_IECR.name="AT91C_AIC_IECR"
-AT91C_AIC_IECR.description="Interrupt Enable Command Register"
-AT91C_AIC_IECR.helpkey="Interrupt Enable Command Register"
-AT91C_AIC_IECR.access=memorymapped
-AT91C_AIC_IECR.address=0xFFFFF120
-AT91C_AIC_IECR.width=32
-AT91C_AIC_IECR.byteEndian=little
-AT91C_AIC_IECR.type=enum
-AT91C_AIC_IECR.enum.0.name=*** Write only ***
-AT91C_AIC_IECR.enum.1.name=Error
-AT91C_AIC_ISCR.name="AT91C_AIC_ISCR"
-AT91C_AIC_ISCR.description="Interrupt Set Command Register"
-AT91C_AIC_ISCR.helpkey="Interrupt Set Command Register"
-AT91C_AIC_ISCR.access=memorymapped
-AT91C_AIC_ISCR.address=0xFFFFF12C
-AT91C_AIC_ISCR.width=32
-AT91C_AIC_ISCR.byteEndian=little
-AT91C_AIC_ISCR.type=enum
-AT91C_AIC_ISCR.enum.0.name=*** Write only ***
-AT91C_AIC_ISCR.enum.1.name=Error
-AT91C_AIC_FFDR.name="AT91C_AIC_FFDR"
-AT91C_AIC_FFDR.description="Fast Forcing Disable Register"
-AT91C_AIC_FFDR.helpkey="Fast Forcing Disable Register"
-AT91C_AIC_FFDR.access=memorymapped
-AT91C_AIC_FFDR.address=0xFFFFF144
-AT91C_AIC_FFDR.width=32
-AT91C_AIC_FFDR.byteEndian=little
-AT91C_AIC_FFDR.type=enum
-AT91C_AIC_FFDR.enum.0.name=*** Write only ***
-AT91C_AIC_FFDR.enum.1.name=Error
-AT91C_AIC_CISR.name="AT91C_AIC_CISR"
-AT91C_AIC_CISR.description="Core Interrupt Status Register"
-AT91C_AIC_CISR.helpkey="Core Interrupt Status Register"
-AT91C_AIC_CISR.access=memorymapped
-AT91C_AIC_CISR.address=0xFFFFF114
-AT91C_AIC_CISR.width=32
-AT91C_AIC_CISR.byteEndian=little
-AT91C_AIC_CISR.permission.write=none
-AT91C_AIC_IDCR.name="AT91C_AIC_IDCR"
-AT91C_AIC_IDCR.description="Interrupt Disable Command Register"
-AT91C_AIC_IDCR.helpkey="Interrupt Disable Command Register"
-AT91C_AIC_IDCR.access=memorymapped
-AT91C_AIC_IDCR.address=0xFFFFF124
-AT91C_AIC_IDCR.width=32
-AT91C_AIC_IDCR.byteEndian=little
-AT91C_AIC_IDCR.type=enum
-AT91C_AIC_IDCR.enum.0.name=*** Write only ***
-AT91C_AIC_IDCR.enum.1.name=Error
-AT91C_AIC_SPU.name="AT91C_AIC_SPU"
-AT91C_AIC_SPU.description="Spurious Vector Register"
-AT91C_AIC_SPU.helpkey="Spurious Vector Register"
-AT91C_AIC_SPU.access=memorymapped
-AT91C_AIC_SPU.address=0xFFFFF134
-AT91C_AIC_SPU.width=32
-AT91C_AIC_SPU.byteEndian=little
-# ========== Register definition for PDC_DBGU peripheral ==========
-AT91C_DBGU_TCR.name="AT91C_DBGU_TCR"
-AT91C_DBGU_TCR.description="Transmit Counter Register"
-AT91C_DBGU_TCR.helpkey="Transmit Counter Register"
-AT91C_DBGU_TCR.access=memorymapped
-AT91C_DBGU_TCR.address=0xFFFFF30C
-AT91C_DBGU_TCR.width=32
-AT91C_DBGU_TCR.byteEndian=little
-AT91C_DBGU_RNPR.name="AT91C_DBGU_RNPR"
-AT91C_DBGU_RNPR.description="Receive Next Pointer Register"
-AT91C_DBGU_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_DBGU_RNPR.access=memorymapped
-AT91C_DBGU_RNPR.address=0xFFFFF310
-AT91C_DBGU_RNPR.width=32
-AT91C_DBGU_RNPR.byteEndian=little
-AT91C_DBGU_TNPR.name="AT91C_DBGU_TNPR"
-AT91C_DBGU_TNPR.description="Transmit Next Pointer Register"
-AT91C_DBGU_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_DBGU_TNPR.access=memorymapped
-AT91C_DBGU_TNPR.address=0xFFFFF318
-AT91C_DBGU_TNPR.width=32
-AT91C_DBGU_TNPR.byteEndian=little
-AT91C_DBGU_TPR.name="AT91C_DBGU_TPR"
-AT91C_DBGU_TPR.description="Transmit Pointer Register"
-AT91C_DBGU_TPR.helpkey="Transmit Pointer Register"
-AT91C_DBGU_TPR.access=memorymapped
-AT91C_DBGU_TPR.address=0xFFFFF308
-AT91C_DBGU_TPR.width=32
-AT91C_DBGU_TPR.byteEndian=little
-AT91C_DBGU_RPR.name="AT91C_DBGU_RPR"
-AT91C_DBGU_RPR.description="Receive Pointer Register"
-AT91C_DBGU_RPR.helpkey="Receive Pointer Register"
-AT91C_DBGU_RPR.access=memorymapped
-AT91C_DBGU_RPR.address=0xFFFFF300
-AT91C_DBGU_RPR.width=32
-AT91C_DBGU_RPR.byteEndian=little
-AT91C_DBGU_RCR.name="AT91C_DBGU_RCR"
-AT91C_DBGU_RCR.description="Receive Counter Register"
-AT91C_DBGU_RCR.helpkey="Receive Counter Register"
-AT91C_DBGU_RCR.access=memorymapped
-AT91C_DBGU_RCR.address=0xFFFFF304
-AT91C_DBGU_RCR.width=32
-AT91C_DBGU_RCR.byteEndian=little
-AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
-AT91C_DBGU_RNCR.description="Receive Next Counter Register"
-AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
-AT91C_DBGU_RNCR.access=memorymapped
-AT91C_DBGU_RNCR.address=0xFFFFF314
-AT91C_DBGU_RNCR.width=32
-AT91C_DBGU_RNCR.byteEndian=little
-AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
-AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
-AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_DBGU_PTCR.access=memorymapped
-AT91C_DBGU_PTCR.address=0xFFFFF320
-AT91C_DBGU_PTCR.width=32
-AT91C_DBGU_PTCR.byteEndian=little
-AT91C_DBGU_PTCR.type=enum
-AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
-AT91C_DBGU_PTCR.enum.1.name=Error
-AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
-AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
-AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_DBGU_PTSR.access=memorymapped
-AT91C_DBGU_PTSR.address=0xFFFFF324
-AT91C_DBGU_PTSR.width=32
-AT91C_DBGU_PTSR.byteEndian=little
-AT91C_DBGU_PTSR.permission.write=none
-AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
-AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
-AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_DBGU_TNCR.access=memorymapped
-AT91C_DBGU_TNCR.address=0xFFFFF31C
-AT91C_DBGU_TNCR.width=32
-AT91C_DBGU_TNCR.byteEndian=little
-# ========== Register definition for DBGU peripheral ==========
-AT91C_DBGU_EXID.name="AT91C_DBGU_EXID"
-AT91C_DBGU_EXID.description="Chip ID Extension Register"
-AT91C_DBGU_EXID.helpkey="Chip ID Extension Register"
-AT91C_DBGU_EXID.access=memorymapped
-AT91C_DBGU_EXID.address=0xFFFFF244
-AT91C_DBGU_EXID.width=32
-AT91C_DBGU_EXID.byteEndian=little
-AT91C_DBGU_EXID.permission.write=none
-AT91C_DBGU_BRGR.name="AT91C_DBGU_BRGR"
-AT91C_DBGU_BRGR.description="Baud Rate Generator Register"
-AT91C_DBGU_BRGR.helpkey="Baud Rate Generator Register"
-AT91C_DBGU_BRGR.access=memorymapped
-AT91C_DBGU_BRGR.address=0xFFFFF220
-AT91C_DBGU_BRGR.width=32
-AT91C_DBGU_BRGR.byteEndian=little
-AT91C_DBGU_IDR.name="AT91C_DBGU_IDR"
-AT91C_DBGU_IDR.description="Interrupt Disable Register"
-AT91C_DBGU_IDR.helpkey="Interrupt Disable Register"
-AT91C_DBGU_IDR.access=memorymapped
-AT91C_DBGU_IDR.address=0xFFFFF20C
-AT91C_DBGU_IDR.width=32
-AT91C_DBGU_IDR.byteEndian=little
-AT91C_DBGU_IDR.type=enum
-AT91C_DBGU_IDR.enum.0.name=*** Write only ***
-AT91C_DBGU_IDR.enum.1.name=Error
-AT91C_DBGU_CSR.name="AT91C_DBGU_CSR"
-AT91C_DBGU_CSR.description="Channel Status Register"
-AT91C_DBGU_CSR.helpkey="Channel Status Register"
-AT91C_DBGU_CSR.access=memorymapped
-AT91C_DBGU_CSR.address=0xFFFFF214
-AT91C_DBGU_CSR.width=32
-AT91C_DBGU_CSR.byteEndian=little
-AT91C_DBGU_CSR.permission.write=none
-AT91C_DBGU_CIDR.name="AT91C_DBGU_CIDR"
-AT91C_DBGU_CIDR.description="Chip ID Register"
-AT91C_DBGU_CIDR.helpkey="Chip ID Register"
-AT91C_DBGU_CIDR.access=memorymapped
-AT91C_DBGU_CIDR.address=0xFFFFF240
-AT91C_DBGU_CIDR.width=32
-AT91C_DBGU_CIDR.byteEndian=little
-AT91C_DBGU_CIDR.permission.write=none
-AT91C_DBGU_MR.name="AT91C_DBGU_MR"
-AT91C_DBGU_MR.description="Mode Register"
-AT91C_DBGU_MR.helpkey="Mode Register"
-AT91C_DBGU_MR.access=memorymapped
-AT91C_DBGU_MR.address=0xFFFFF204
-AT91C_DBGU_MR.width=32
-AT91C_DBGU_MR.byteEndian=little
-AT91C_DBGU_IMR.name="AT91C_DBGU_IMR"
-AT91C_DBGU_IMR.description="Interrupt Mask Register"
-AT91C_DBGU_IMR.helpkey="Interrupt Mask Register"
-AT91C_DBGU_IMR.access=memorymapped
-AT91C_DBGU_IMR.address=0xFFFFF210
-AT91C_DBGU_IMR.width=32
-AT91C_DBGU_IMR.byteEndian=little
-AT91C_DBGU_IMR.permission.write=none
-AT91C_DBGU_CR.name="AT91C_DBGU_CR"
-AT91C_DBGU_CR.description="Control Register"
-AT91C_DBGU_CR.helpkey="Control Register"
-AT91C_DBGU_CR.access=memorymapped
-AT91C_DBGU_CR.address=0xFFFFF200
-AT91C_DBGU_CR.width=32
-AT91C_DBGU_CR.byteEndian=little
-AT91C_DBGU_CR.type=enum
-AT91C_DBGU_CR.enum.0.name=*** Write only ***
-AT91C_DBGU_CR.enum.1.name=Error
-AT91C_DBGU_FNTR.name="AT91C_DBGU_FNTR"
-AT91C_DBGU_FNTR.description="Force NTRST Register"
-AT91C_DBGU_FNTR.helpkey="Force NTRST Register"
-AT91C_DBGU_FNTR.access=memorymapped
-AT91C_DBGU_FNTR.address=0xFFFFF248
-AT91C_DBGU_FNTR.width=32
-AT91C_DBGU_FNTR.byteEndian=little
-AT91C_DBGU_THR.name="AT91C_DBGU_THR"
-AT91C_DBGU_THR.description="Transmitter Holding Register"
-AT91C_DBGU_THR.helpkey="Transmitter Holding Register"
-AT91C_DBGU_THR.access=memorymapped
-AT91C_DBGU_THR.address=0xFFFFF21C
-AT91C_DBGU_THR.width=32
-AT91C_DBGU_THR.byteEndian=little
-AT91C_DBGU_THR.type=enum
-AT91C_DBGU_THR.enum.0.name=*** Write only ***
-AT91C_DBGU_THR.enum.1.name=Error
-AT91C_DBGU_RHR.name="AT91C_DBGU_RHR"
-AT91C_DBGU_RHR.description="Receiver Holding Register"
-AT91C_DBGU_RHR.helpkey="Receiver Holding Register"
-AT91C_DBGU_RHR.access=memorymapped
-AT91C_DBGU_RHR.address=0xFFFFF218
-AT91C_DBGU_RHR.width=32
-AT91C_DBGU_RHR.byteEndian=little
-AT91C_DBGU_RHR.permission.write=none
-AT91C_DBGU_IER.name="AT91C_DBGU_IER"
-AT91C_DBGU_IER.description="Interrupt Enable Register"
-AT91C_DBGU_IER.helpkey="Interrupt Enable Register"
-AT91C_DBGU_IER.access=memorymapped
-AT91C_DBGU_IER.address=0xFFFFF208
-AT91C_DBGU_IER.width=32
-AT91C_DBGU_IER.byteEndian=little
-AT91C_DBGU_IER.type=enum
-AT91C_DBGU_IER.enum.0.name=*** Write only ***
-AT91C_DBGU_IER.enum.1.name=Error
-# ========== Register definition for PIOA peripheral ==========
-AT91C_PIOA_ODR.name="AT91C_PIOA_ODR"
-AT91C_PIOA_ODR.description="Output Disable Registerr"
-AT91C_PIOA_ODR.helpkey="Output Disable Registerr"
-AT91C_PIOA_ODR.access=memorymapped
-AT91C_PIOA_ODR.address=0xFFFFF414
-AT91C_PIOA_ODR.width=32
-AT91C_PIOA_ODR.byteEndian=little
-AT91C_PIOA_ODR.type=enum
-AT91C_PIOA_ODR.enum.0.name=*** Write only ***
-AT91C_PIOA_ODR.enum.1.name=Error
-AT91C_PIOA_SODR.name="AT91C_PIOA_SODR"
-AT91C_PIOA_SODR.description="Set Output Data Register"
-AT91C_PIOA_SODR.helpkey="Set Output Data Register"
-AT91C_PIOA_SODR.access=memorymapped
-AT91C_PIOA_SODR.address=0xFFFFF430
-AT91C_PIOA_SODR.width=32
-AT91C_PIOA_SODR.byteEndian=little
-AT91C_PIOA_SODR.type=enum
-AT91C_PIOA_SODR.enum.0.name=*** Write only ***
-AT91C_PIOA_SODR.enum.1.name=Error
-AT91C_PIOA_ISR.name="AT91C_PIOA_ISR"
-AT91C_PIOA_ISR.description="Interrupt Status Register"
-AT91C_PIOA_ISR.helpkey="Interrupt Status Register"
-AT91C_PIOA_ISR.access=memorymapped
-AT91C_PIOA_ISR.address=0xFFFFF44C
-AT91C_PIOA_ISR.width=32
-AT91C_PIOA_ISR.byteEndian=little
-AT91C_PIOA_ISR.permission.write=none
-AT91C_PIOA_ABSR.name="AT91C_PIOA_ABSR"
-AT91C_PIOA_ABSR.description="AB Select Status Register"
-AT91C_PIOA_ABSR.helpkey="AB Select Status Register"
-AT91C_PIOA_ABSR.access=memorymapped
-AT91C_PIOA_ABSR.address=0xFFFFF478
-AT91C_PIOA_ABSR.width=32
-AT91C_PIOA_ABSR.byteEndian=little
-AT91C_PIOA_ABSR.permission.write=none
-AT91C_PIOA_IER.name="AT91C_PIOA_IER"
-AT91C_PIOA_IER.description="Interrupt Enable Register"
-AT91C_PIOA_IER.helpkey="Interrupt Enable Register"
-AT91C_PIOA_IER.access=memorymapped
-AT91C_PIOA_IER.address=0xFFFFF440
-AT91C_PIOA_IER.width=32
-AT91C_PIOA_IER.byteEndian=little
-AT91C_PIOA_IER.type=enum
-AT91C_PIOA_IER.enum.0.name=*** Write only ***
-AT91C_PIOA_IER.enum.1.name=Error
-AT91C_PIOA_PPUDR.name="AT91C_PIOA_PPUDR"
-AT91C_PIOA_PPUDR.description="Pull-up Disable Register"
-AT91C_PIOA_PPUDR.helpkey="Pull-up Disable Register"
-AT91C_PIOA_PPUDR.access=memorymapped
-AT91C_PIOA_PPUDR.address=0xFFFFF460
-AT91C_PIOA_PPUDR.width=32
-AT91C_PIOA_PPUDR.byteEndian=little
-AT91C_PIOA_PPUDR.type=enum
-AT91C_PIOA_PPUDR.enum.0.name=*** Write only ***
-AT91C_PIOA_PPUDR.enum.1.name=Error
-AT91C_PIOA_IMR.name="AT91C_PIOA_IMR"
-AT91C_PIOA_IMR.description="Interrupt Mask Register"
-AT91C_PIOA_IMR.helpkey="Interrupt Mask Register"
-AT91C_PIOA_IMR.access=memorymapped
-AT91C_PIOA_IMR.address=0xFFFFF448
-AT91C_PIOA_IMR.width=32
-AT91C_PIOA_IMR.byteEndian=little
-AT91C_PIOA_IMR.permission.write=none
-AT91C_PIOA_PER.name="AT91C_PIOA_PER"
-AT91C_PIOA_PER.description="PIO Enable Register"
-AT91C_PIOA_PER.helpkey="PIO Enable Register"
-AT91C_PIOA_PER.access=memorymapped
-AT91C_PIOA_PER.address=0xFFFFF400
-AT91C_PIOA_PER.width=32
-AT91C_PIOA_PER.byteEndian=little
-AT91C_PIOA_PER.type=enum
-AT91C_PIOA_PER.enum.0.name=*** Write only ***
-AT91C_PIOA_PER.enum.1.name=Error
-AT91C_PIOA_IFDR.name="AT91C_PIOA_IFDR"
-AT91C_PIOA_IFDR.description="Input Filter Disable Register"
-AT91C_PIOA_IFDR.helpkey="Input Filter Disable Register"
-AT91C_PIOA_IFDR.access=memorymapped
-AT91C_PIOA_IFDR.address=0xFFFFF424
-AT91C_PIOA_IFDR.width=32
-AT91C_PIOA_IFDR.byteEndian=little
-AT91C_PIOA_IFDR.type=enum
-AT91C_PIOA_IFDR.enum.0.name=*** Write only ***
-AT91C_PIOA_IFDR.enum.1.name=Error
-AT91C_PIOA_OWDR.name="AT91C_PIOA_OWDR"
-AT91C_PIOA_OWDR.description="Output Write Disable Register"
-AT91C_PIOA_OWDR.helpkey="Output Write Disable Register"
-AT91C_PIOA_OWDR.access=memorymapped
-AT91C_PIOA_OWDR.address=0xFFFFF4A4
-AT91C_PIOA_OWDR.width=32
-AT91C_PIOA_OWDR.byteEndian=little
-AT91C_PIOA_OWDR.type=enum
-AT91C_PIOA_OWDR.enum.0.name=*** Write only ***
-AT91C_PIOA_OWDR.enum.1.name=Error
-AT91C_PIOA_MDSR.name="AT91C_PIOA_MDSR"
-AT91C_PIOA_MDSR.description="Multi-driver Status Register"
-AT91C_PIOA_MDSR.helpkey="Multi-driver Status Register"
-AT91C_PIOA_MDSR.access=memorymapped
-AT91C_PIOA_MDSR.address=0xFFFFF458
-AT91C_PIOA_MDSR.width=32
-AT91C_PIOA_MDSR.byteEndian=little
-AT91C_PIOA_MDSR.permission.write=none
-AT91C_PIOA_IDR.name="AT91C_PIOA_IDR"
-AT91C_PIOA_IDR.description="Interrupt Disable Register"
-AT91C_PIOA_IDR.helpkey="Interrupt Disable Register"
-AT91C_PIOA_IDR.access=memorymapped
-AT91C_PIOA_IDR.address=0xFFFFF444
-AT91C_PIOA_IDR.width=32
-AT91C_PIOA_IDR.byteEndian=little
-AT91C_PIOA_IDR.type=enum
-AT91C_PIOA_IDR.enum.0.name=*** Write only ***
-AT91C_PIOA_IDR.enum.1.name=Error
-AT91C_PIOA_ODSR.name="AT91C_PIOA_ODSR"
-AT91C_PIOA_ODSR.description="Output Data Status Register"
-AT91C_PIOA_ODSR.helpkey="Output Data Status Register"
-AT91C_PIOA_ODSR.access=memorymapped
-AT91C_PIOA_ODSR.address=0xFFFFF438
-AT91C_PIOA_ODSR.width=32
-AT91C_PIOA_ODSR.byteEndian=little
-AT91C_PIOA_ODSR.permission.write=none
-AT91C_PIOA_PPUSR.name="AT91C_PIOA_PPUSR"
-AT91C_PIOA_PPUSR.description="Pull-up Status Register"
-AT91C_PIOA_PPUSR.helpkey="Pull-up Status Register"
-AT91C_PIOA_PPUSR.access=memorymapped
-AT91C_PIOA_PPUSR.address=0xFFFFF468
-AT91C_PIOA_PPUSR.width=32
-AT91C_PIOA_PPUSR.byteEndian=little
-AT91C_PIOA_PPUSR.permission.write=none
-AT91C_PIOA_OWSR.name="AT91C_PIOA_OWSR"
-AT91C_PIOA_OWSR.description="Output Write Status Register"
-AT91C_PIOA_OWSR.helpkey="Output Write Status Register"
-AT91C_PIOA_OWSR.access=memorymapped
-AT91C_PIOA_OWSR.address=0xFFFFF4A8
-AT91C_PIOA_OWSR.width=32
-AT91C_PIOA_OWSR.byteEndian=little
-AT91C_PIOA_OWSR.permission.write=none
-AT91C_PIOA_BSR.name="AT91C_PIOA_BSR"
-AT91C_PIOA_BSR.description="Select B Register"
-AT91C_PIOA_BSR.helpkey="Select B Register"
-AT91C_PIOA_BSR.access=memorymapped
-AT91C_PIOA_BSR.address=0xFFFFF474
-AT91C_PIOA_BSR.width=32
-AT91C_PIOA_BSR.byteEndian=little
-AT91C_PIOA_BSR.type=enum
-AT91C_PIOA_BSR.enum.0.name=*** Write only ***
-AT91C_PIOA_BSR.enum.1.name=Error
-AT91C_PIOA_OWER.name="AT91C_PIOA_OWER"
-AT91C_PIOA_OWER.description="Output Write Enable Register"
-AT91C_PIOA_OWER.helpkey="Output Write Enable Register"
-AT91C_PIOA_OWER.access=memorymapped
-AT91C_PIOA_OWER.address=0xFFFFF4A0
-AT91C_PIOA_OWER.width=32
-AT91C_PIOA_OWER.byteEndian=little
-AT91C_PIOA_OWER.type=enum
-AT91C_PIOA_OWER.enum.0.name=*** Write only ***
-AT91C_PIOA_OWER.enum.1.name=Error
-AT91C_PIOA_IFER.name="AT91C_PIOA_IFER"
-AT91C_PIOA_IFER.description="Input Filter Enable Register"
-AT91C_PIOA_IFER.helpkey="Input Filter Enable Register"
-AT91C_PIOA_IFER.access=memorymapped
-AT91C_PIOA_IFER.address=0xFFFFF420
-AT91C_PIOA_IFER.width=32
-AT91C_PIOA_IFER.byteEndian=little
-AT91C_PIOA_IFER.type=enum
-AT91C_PIOA_IFER.enum.0.name=*** Write only ***
-AT91C_PIOA_IFER.enum.1.name=Error
-AT91C_PIOA_PDSR.name="AT91C_PIOA_PDSR"
-AT91C_PIOA_PDSR.description="Pin Data Status Register"
-AT91C_PIOA_PDSR.helpkey="Pin Data Status Register"
-AT91C_PIOA_PDSR.access=memorymapped
-AT91C_PIOA_PDSR.address=0xFFFFF43C
-AT91C_PIOA_PDSR.width=32
-AT91C_PIOA_PDSR.byteEndian=little
-AT91C_PIOA_PDSR.permission.write=none
-AT91C_PIOA_PPUER.name="AT91C_PIOA_PPUER"
-AT91C_PIOA_PPUER.description="Pull-up Enable Register"
-AT91C_PIOA_PPUER.helpkey="Pull-up Enable Register"
-AT91C_PIOA_PPUER.access=memorymapped
-AT91C_PIOA_PPUER.address=0xFFFFF464
-AT91C_PIOA_PPUER.width=32
-AT91C_PIOA_PPUER.byteEndian=little
-AT91C_PIOA_PPUER.type=enum
-AT91C_PIOA_PPUER.enum.0.name=*** Write only ***
-AT91C_PIOA_PPUER.enum.1.name=Error
-AT91C_PIOA_OSR.name="AT91C_PIOA_OSR"
-AT91C_PIOA_OSR.description="Output Status Register"
-AT91C_PIOA_OSR.helpkey="Output Status Register"
-AT91C_PIOA_OSR.access=memorymapped
-AT91C_PIOA_OSR.address=0xFFFFF418
-AT91C_PIOA_OSR.width=32
-AT91C_PIOA_OSR.byteEndian=little
-AT91C_PIOA_OSR.permission.write=none
-AT91C_PIOA_ASR.name="AT91C_PIOA_ASR"
-AT91C_PIOA_ASR.description="Select A Register"
-AT91C_PIOA_ASR.helpkey="Select A Register"
-AT91C_PIOA_ASR.access=memorymapped
-AT91C_PIOA_ASR.address=0xFFFFF470
-AT91C_PIOA_ASR.width=32
-AT91C_PIOA_ASR.byteEndian=little
-AT91C_PIOA_ASR.type=enum
-AT91C_PIOA_ASR.enum.0.name=*** Write only ***
-AT91C_PIOA_ASR.enum.1.name=Error
-AT91C_PIOA_MDDR.name="AT91C_PIOA_MDDR"
-AT91C_PIOA_MDDR.description="Multi-driver Disable Register"
-AT91C_PIOA_MDDR.helpkey="Multi-driver Disable Register"
-AT91C_PIOA_MDDR.access=memorymapped
-AT91C_PIOA_MDDR.address=0xFFFFF454
-AT91C_PIOA_MDDR.width=32
-AT91C_PIOA_MDDR.byteEndian=little
-AT91C_PIOA_MDDR.type=enum
-AT91C_PIOA_MDDR.enum.0.name=*** Write only ***
-AT91C_PIOA_MDDR.enum.1.name=Error
-AT91C_PIOA_CODR.name="AT91C_PIOA_CODR"
-AT91C_PIOA_CODR.description="Clear Output Data Register"
-AT91C_PIOA_CODR.helpkey="Clear Output Data Register"
-AT91C_PIOA_CODR.access=memorymapped
-AT91C_PIOA_CODR.address=0xFFFFF434
-AT91C_PIOA_CODR.width=32
-AT91C_PIOA_CODR.byteEndian=little
-AT91C_PIOA_CODR.type=enum
-AT91C_PIOA_CODR.enum.0.name=*** Write only ***
-AT91C_PIOA_CODR.enum.1.name=Error
-AT91C_PIOA_MDER.name="AT91C_PIOA_MDER"
-AT91C_PIOA_MDER.description="Multi-driver Enable Register"
-AT91C_PIOA_MDER.helpkey="Multi-driver Enable Register"
-AT91C_PIOA_MDER.access=memorymapped
-AT91C_PIOA_MDER.address=0xFFFFF450
-AT91C_PIOA_MDER.width=32
-AT91C_PIOA_MDER.byteEndian=little
-AT91C_PIOA_MDER.type=enum
-AT91C_PIOA_MDER.enum.0.name=*** Write only ***
-AT91C_PIOA_MDER.enum.1.name=Error
-AT91C_PIOA_PDR.name="AT91C_PIOA_PDR"
-AT91C_PIOA_PDR.description="PIO Disable Register"
-AT91C_PIOA_PDR.helpkey="PIO Disable Register"
-AT91C_PIOA_PDR.access=memorymapped
-AT91C_PIOA_PDR.address=0xFFFFF404
-AT91C_PIOA_PDR.width=32
-AT91C_PIOA_PDR.byteEndian=little
-AT91C_PIOA_PDR.type=enum
-AT91C_PIOA_PDR.enum.0.name=*** Write only ***
-AT91C_PIOA_PDR.enum.1.name=Error
-AT91C_PIOA_IFSR.name="AT91C_PIOA_IFSR"
-AT91C_PIOA_IFSR.description="Input Filter Status Register"
-AT91C_PIOA_IFSR.helpkey="Input Filter Status Register"
-AT91C_PIOA_IFSR.access=memorymapped
-AT91C_PIOA_IFSR.address=0xFFFFF428
-AT91C_PIOA_IFSR.width=32
-AT91C_PIOA_IFSR.byteEndian=little
-AT91C_PIOA_IFSR.permission.write=none
-AT91C_PIOA_OER.name="AT91C_PIOA_OER"
-AT91C_PIOA_OER.description="Output Enable Register"
-AT91C_PIOA_OER.helpkey="Output Enable Register"
-AT91C_PIOA_OER.access=memorymapped
-AT91C_PIOA_OER.address=0xFFFFF410
-AT91C_PIOA_OER.width=32
-AT91C_PIOA_OER.byteEndian=little
-AT91C_PIOA_OER.type=enum
-AT91C_PIOA_OER.enum.0.name=*** Write only ***
-AT91C_PIOA_OER.enum.1.name=Error
-AT91C_PIOA_PSR.name="AT91C_PIOA_PSR"
-AT91C_PIOA_PSR.description="PIO Status Register"
-AT91C_PIOA_PSR.helpkey="PIO Status Register"
-AT91C_PIOA_PSR.access=memorymapped
-AT91C_PIOA_PSR.address=0xFFFFF408
-AT91C_PIOA_PSR.width=32
-AT91C_PIOA_PSR.byteEndian=little
-AT91C_PIOA_PSR.permission.write=none
-# ========== Register definition for CKGR peripheral ==========
-AT91C_CKGR_MOR.name="AT91C_CKGR_MOR"
-AT91C_CKGR_MOR.description="Main Oscillator Register"
-AT91C_CKGR_MOR.helpkey="Main Oscillator Register"
-AT91C_CKGR_MOR.access=memorymapped
-AT91C_CKGR_MOR.address=0xFFFFFC20
-AT91C_CKGR_MOR.width=32
-AT91C_CKGR_MOR.byteEndian=little
-AT91C_CKGR_PLLR.name="AT91C_CKGR_PLLR"
-AT91C_CKGR_PLLR.description="PLL Register"
-AT91C_CKGR_PLLR.helpkey="PLL Register"
-AT91C_CKGR_PLLR.access=memorymapped
-AT91C_CKGR_PLLR.address=0xFFFFFC2C
-AT91C_CKGR_PLLR.width=32
-AT91C_CKGR_PLLR.byteEndian=little
-AT91C_CKGR_MCFR.name="AT91C_CKGR_MCFR"
-AT91C_CKGR_MCFR.description="Main Clock Frequency Register"
-AT91C_CKGR_MCFR.helpkey="Main Clock Frequency Register"
-AT91C_CKGR_MCFR.access=memorymapped
-AT91C_CKGR_MCFR.address=0xFFFFFC24
-AT91C_CKGR_MCFR.width=32
-AT91C_CKGR_MCFR.byteEndian=little
-AT91C_CKGR_MCFR.permission.write=none
-# ========== Register definition for PMC peripheral ==========
-AT91C_PMC_IDR.name="AT91C_PMC_IDR"
-AT91C_PMC_IDR.description="Interrupt Disable Register"
-AT91C_PMC_IDR.helpkey="Interrupt Disable Register"
-AT91C_PMC_IDR.access=memorymapped
-AT91C_PMC_IDR.address=0xFFFFFC64
-AT91C_PMC_IDR.width=32
-AT91C_PMC_IDR.byteEndian=little
-AT91C_PMC_IDR.type=enum
-AT91C_PMC_IDR.enum.0.name=*** Write only ***
-AT91C_PMC_IDR.enum.1.name=Error
-AT91C_PMC_MOR.name="AT91C_PMC_MOR"
-AT91C_PMC_MOR.description="Main Oscillator Register"
-AT91C_PMC_MOR.helpkey="Main Oscillator Register"
-AT91C_PMC_MOR.access=memorymapped
-AT91C_PMC_MOR.address=0xFFFFFC20
-AT91C_PMC_MOR.width=32
-AT91C_PMC_MOR.byteEndian=little
-AT91C_PMC_PLLR.name="AT91C_PMC_PLLR"
-AT91C_PMC_PLLR.description="PLL Register"
-AT91C_PMC_PLLR.helpkey="PLL Register"
-AT91C_PMC_PLLR.access=memorymapped
-AT91C_PMC_PLLR.address=0xFFFFFC2C
-AT91C_PMC_PLLR.width=32
-AT91C_PMC_PLLR.byteEndian=little
-AT91C_PMC_PCER.name="AT91C_PMC_PCER"
-AT91C_PMC_PCER.description="Peripheral Clock Enable Register"
-AT91C_PMC_PCER.helpkey="Peripheral Clock Enable Register"
-AT91C_PMC_PCER.access=memorymapped
-AT91C_PMC_PCER.address=0xFFFFFC10
-AT91C_PMC_PCER.width=32
-AT91C_PMC_PCER.byteEndian=little
-AT91C_PMC_PCER.type=enum
-AT91C_PMC_PCER.enum.0.name=*** Write only ***
-AT91C_PMC_PCER.enum.1.name=Error
-AT91C_PMC_PCKR.name="AT91C_PMC_PCKR"
-AT91C_PMC_PCKR.description="Programmable Clock Register"
-AT91C_PMC_PCKR.helpkey="Programmable Clock Register"
-AT91C_PMC_PCKR.access=memorymapped
-AT91C_PMC_PCKR.address=0xFFFFFC40
-AT91C_PMC_PCKR.width=32
-AT91C_PMC_PCKR.byteEndian=little
-AT91C_PMC_MCKR.name="AT91C_PMC_MCKR"
-AT91C_PMC_MCKR.description="Master Clock Register"
-AT91C_PMC_MCKR.helpkey="Master Clock Register"
-AT91C_PMC_MCKR.access=memorymapped
-AT91C_PMC_MCKR.address=0xFFFFFC30
-AT91C_PMC_MCKR.width=32
-AT91C_PMC_MCKR.byteEndian=little
-AT91C_PMC_SCDR.name="AT91C_PMC_SCDR"
-AT91C_PMC_SCDR.description="System Clock Disable Register"
-AT91C_PMC_SCDR.helpkey="System Clock Disable Register"
-AT91C_PMC_SCDR.access=memorymapped
-AT91C_PMC_SCDR.address=0xFFFFFC04
-AT91C_PMC_SCDR.width=32
-AT91C_PMC_SCDR.byteEndian=little
-AT91C_PMC_SCDR.type=enum
-AT91C_PMC_SCDR.enum.0.name=*** Write only ***
-AT91C_PMC_SCDR.enum.1.name=Error
-AT91C_PMC_PCDR.name="AT91C_PMC_PCDR"
-AT91C_PMC_PCDR.description="Peripheral Clock Disable Register"
-AT91C_PMC_PCDR.helpkey="Peripheral Clock Disable Register"
-AT91C_PMC_PCDR.access=memorymapped
-AT91C_PMC_PCDR.address=0xFFFFFC14
-AT91C_PMC_PCDR.width=32
-AT91C_PMC_PCDR.byteEndian=little
-AT91C_PMC_PCDR.type=enum
-AT91C_PMC_PCDR.enum.0.name=*** Write only ***
-AT91C_PMC_PCDR.enum.1.name=Error
-AT91C_PMC_SCSR.name="AT91C_PMC_SCSR"
-AT91C_PMC_SCSR.description="System Clock Status Register"
-AT91C_PMC_SCSR.helpkey="System Clock Status Register"
-AT91C_PMC_SCSR.access=memorymapped
-AT91C_PMC_SCSR.address=0xFFFFFC08
-AT91C_PMC_SCSR.width=32
-AT91C_PMC_SCSR.byteEndian=little
-AT91C_PMC_SCSR.permission.write=none
-AT91C_PMC_PCSR.name="AT91C_PMC_PCSR"
-AT91C_PMC_PCSR.description="Peripheral Clock Status Register"
-AT91C_PMC_PCSR.helpkey="Peripheral Clock Status Register"
-AT91C_PMC_PCSR.access=memorymapped
-AT91C_PMC_PCSR.address=0xFFFFFC18
-AT91C_PMC_PCSR.width=32
-AT91C_PMC_PCSR.byteEndian=little
-AT91C_PMC_PCSR.permission.write=none
-AT91C_PMC_MCFR.name="AT91C_PMC_MCFR"
-AT91C_PMC_MCFR.description="Main Clock Frequency Register"
-AT91C_PMC_MCFR.helpkey="Main Clock Frequency Register"
-AT91C_PMC_MCFR.access=memorymapped
-AT91C_PMC_MCFR.address=0xFFFFFC24
-AT91C_PMC_MCFR.width=32
-AT91C_PMC_MCFR.byteEndian=little
-AT91C_PMC_MCFR.permission.write=none
-AT91C_PMC_SCER.name="AT91C_PMC_SCER"
-AT91C_PMC_SCER.description="System Clock Enable Register"
-AT91C_PMC_SCER.helpkey="System Clock Enable Register"
-AT91C_PMC_SCER.access=memorymapped
-AT91C_PMC_SCER.address=0xFFFFFC00
-AT91C_PMC_SCER.width=32
-AT91C_PMC_SCER.byteEndian=little
-AT91C_PMC_SCER.type=enum
-AT91C_PMC_SCER.enum.0.name=*** Write only ***
-AT91C_PMC_SCER.enum.1.name=Error
-AT91C_PMC_IMR.name="AT91C_PMC_IMR"
-AT91C_PMC_IMR.description="Interrupt Mask Register"
-AT91C_PMC_IMR.helpkey="Interrupt Mask Register"
-AT91C_PMC_IMR.access=memorymapped
-AT91C_PMC_IMR.address=0xFFFFFC6C
-AT91C_PMC_IMR.width=32
-AT91C_PMC_IMR.byteEndian=little
-AT91C_PMC_IMR.permission.write=none
-AT91C_PMC_IER.name="AT91C_PMC_IER"
-AT91C_PMC_IER.description="Interrupt Enable Register"
-AT91C_PMC_IER.helpkey="Interrupt Enable Register"
-AT91C_PMC_IER.access=memorymapped
-AT91C_PMC_IER.address=0xFFFFFC60
-AT91C_PMC_IER.width=32
-AT91C_PMC_IER.byteEndian=little
-AT91C_PMC_IER.type=enum
-AT91C_PMC_IER.enum.0.name=*** Write only ***
-AT91C_PMC_IER.enum.1.name=Error
-AT91C_PMC_SR.name="AT91C_PMC_SR"
-AT91C_PMC_SR.description="Status Register"
-AT91C_PMC_SR.helpkey="Status Register"
-AT91C_PMC_SR.access=memorymapped
-AT91C_PMC_SR.address=0xFFFFFC68
-AT91C_PMC_SR.width=32
-AT91C_PMC_SR.byteEndian=little
-AT91C_PMC_SR.permission.write=none
-# ========== Register definition for RSTC peripheral ==========
-AT91C_RSTC_RCR.name="AT91C_RSTC_RCR"
-AT91C_RSTC_RCR.description="Reset Control Register"
-AT91C_RSTC_RCR.helpkey="Reset Control Register"
-AT91C_RSTC_RCR.access=memorymapped
-AT91C_RSTC_RCR.address=0xFFFFFD00
-AT91C_RSTC_RCR.width=32
-AT91C_RSTC_RCR.byteEndian=little
-AT91C_RSTC_RCR.type=enum
-AT91C_RSTC_RCR.enum.0.name=*** Write only ***
-AT91C_RSTC_RCR.enum.1.name=Error
-AT91C_RSTC_RMR.name="AT91C_RSTC_RMR"
-AT91C_RSTC_RMR.description="Reset Mode Register"
-AT91C_RSTC_RMR.helpkey="Reset Mode Register"
-AT91C_RSTC_RMR.access=memorymapped
-AT91C_RSTC_RMR.address=0xFFFFFD08
-AT91C_RSTC_RMR.width=32
-AT91C_RSTC_RMR.byteEndian=little
-AT91C_RSTC_RSR.name="AT91C_RSTC_RSR"
-AT91C_RSTC_RSR.description="Reset Status Register"
-AT91C_RSTC_RSR.helpkey="Reset Status Register"
-AT91C_RSTC_RSR.access=memorymapped
-AT91C_RSTC_RSR.address=0xFFFFFD04
-AT91C_RSTC_RSR.width=32
-AT91C_RSTC_RSR.byteEndian=little
-AT91C_RSTC_RSR.permission.write=none
-# ========== Register definition for RTTC peripheral ==========
-AT91C_RTTC_RTSR.name="AT91C_RTTC_RTSR"
-AT91C_RTTC_RTSR.description="Real-time Status Register"
-AT91C_RTTC_RTSR.helpkey="Real-time Status Register"
-AT91C_RTTC_RTSR.access=memorymapped
-AT91C_RTTC_RTSR.address=0xFFFFFD2C
-AT91C_RTTC_RTSR.width=32
-AT91C_RTTC_RTSR.byteEndian=little
-AT91C_RTTC_RTSR.permission.write=none
-AT91C_RTTC_RTMR.name="AT91C_RTTC_RTMR"
-AT91C_RTTC_RTMR.description="Real-time Mode Register"
-AT91C_RTTC_RTMR.helpkey="Real-time Mode Register"
-AT91C_RTTC_RTMR.access=memorymapped
-AT91C_RTTC_RTMR.address=0xFFFFFD20
-AT91C_RTTC_RTMR.width=32
-AT91C_RTTC_RTMR.byteEndian=little
-AT91C_RTTC_RTVR.name="AT91C_RTTC_RTVR"
-AT91C_RTTC_RTVR.description="Real-time Value Register"
-AT91C_RTTC_RTVR.helpkey="Real-time Value Register"
-AT91C_RTTC_RTVR.access=memorymapped
-AT91C_RTTC_RTVR.address=0xFFFFFD28
-AT91C_RTTC_RTVR.width=32
-AT91C_RTTC_RTVR.byteEndian=little
-AT91C_RTTC_RTVR.permission.write=none
-AT91C_RTTC_RTAR.name="AT91C_RTTC_RTAR"
-AT91C_RTTC_RTAR.description="Real-time Alarm Register"
-AT91C_RTTC_RTAR.helpkey="Real-time Alarm Register"
-AT91C_RTTC_RTAR.access=memorymapped
-AT91C_RTTC_RTAR.address=0xFFFFFD24
-AT91C_RTTC_RTAR.width=32
-AT91C_RTTC_RTAR.byteEndian=little
-# ========== Register definition for PITC peripheral ==========
-AT91C_PITC_PIVR.name="AT91C_PITC_PIVR"
-AT91C_PITC_PIVR.description="Period Interval Value Register"
-AT91C_PITC_PIVR.helpkey="Period Interval Value Register"
-AT91C_PITC_PIVR.access=memorymapped
-AT91C_PITC_PIVR.address=0xFFFFFD38
-AT91C_PITC_PIVR.width=32
-AT91C_PITC_PIVR.byteEndian=little
-AT91C_PITC_PIVR.permission.write=none
-AT91C_PITC_PISR.name="AT91C_PITC_PISR"
-AT91C_PITC_PISR.description="Period Interval Status Register"
-AT91C_PITC_PISR.helpkey="Period Interval Status Register"
-AT91C_PITC_PISR.access=memorymapped
-AT91C_PITC_PISR.address=0xFFFFFD34
-AT91C_PITC_PISR.width=32
-AT91C_PITC_PISR.byteEndian=little
-AT91C_PITC_PISR.permission.write=none
-AT91C_PITC_PIIR.name="AT91C_PITC_PIIR"
-AT91C_PITC_PIIR.description="Period Interval Image Register"
-AT91C_PITC_PIIR.helpkey="Period Interval Image Register"
-AT91C_PITC_PIIR.access=memorymapped
-AT91C_PITC_PIIR.address=0xFFFFFD3C
-AT91C_PITC_PIIR.width=32
-AT91C_PITC_PIIR.byteEndian=little
-AT91C_PITC_PIIR.permission.write=none
-AT91C_PITC_PIMR.name="AT91C_PITC_PIMR"
-AT91C_PITC_PIMR.description="Period Interval Mode Register"
-AT91C_PITC_PIMR.helpkey="Period Interval Mode Register"
-AT91C_PITC_PIMR.access=memorymapped
-AT91C_PITC_PIMR.address=0xFFFFFD30
-AT91C_PITC_PIMR.width=32
-AT91C_PITC_PIMR.byteEndian=little
-# ========== Register definition for WDTC peripheral ==========
-AT91C_WDTC_WDCR.name="AT91C_WDTC_WDCR"
-AT91C_WDTC_WDCR.description="Watchdog Control Register"
-AT91C_WDTC_WDCR.helpkey="Watchdog Control Register"
-AT91C_WDTC_WDCR.access=memorymapped
-AT91C_WDTC_WDCR.address=0xFFFFFD40
-AT91C_WDTC_WDCR.width=32
-AT91C_WDTC_WDCR.byteEndian=little
-AT91C_WDTC_WDCR.type=enum
-AT91C_WDTC_WDCR.enum.0.name=*** Write only ***
-AT91C_WDTC_WDCR.enum.1.name=Error
-AT91C_WDTC_WDSR.name="AT91C_WDTC_WDSR"
-AT91C_WDTC_WDSR.description="Watchdog Status Register"
-AT91C_WDTC_WDSR.helpkey="Watchdog Status Register"
-AT91C_WDTC_WDSR.access=memorymapped
-AT91C_WDTC_WDSR.address=0xFFFFFD48
-AT91C_WDTC_WDSR.width=32
-AT91C_WDTC_WDSR.byteEndian=little
-AT91C_WDTC_WDSR.permission.write=none
-AT91C_WDTC_WDMR.name="AT91C_WDTC_WDMR"
-AT91C_WDTC_WDMR.description="Watchdog Mode Register"
-AT91C_WDTC_WDMR.helpkey="Watchdog Mode Register"
-AT91C_WDTC_WDMR.access=memorymapped
-AT91C_WDTC_WDMR.address=0xFFFFFD44
-AT91C_WDTC_WDMR.width=32
-AT91C_WDTC_WDMR.byteEndian=little
-# ========== Register definition for VREG peripheral ==========
-AT91C_VREG_MR.name="AT91C_VREG_MR"
-AT91C_VREG_MR.description="Voltage Regulator Mode Register"
-AT91C_VREG_MR.helpkey="Voltage Regulator Mode Register"
-AT91C_VREG_MR.access=memorymapped
-AT91C_VREG_MR.address=0xFFFFFD60
-AT91C_VREG_MR.width=32
-AT91C_VREG_MR.byteEndian=little
-# ========== Register definition for MC peripheral ==========
-AT91C_MC_ASR.name="AT91C_MC_ASR"
-AT91C_MC_ASR.description="MC Abort Status Register"
-AT91C_MC_ASR.helpkey="MC Abort Status Register"
-AT91C_MC_ASR.access=memorymapped
-AT91C_MC_ASR.address=0xFFFFFF04
-AT91C_MC_ASR.width=32
-AT91C_MC_ASR.byteEndian=little
-AT91C_MC_ASR.permission.write=none
-AT91C_MC_RCR.name="AT91C_MC_RCR"
-AT91C_MC_RCR.description="MC Remap Control Register"
-AT91C_MC_RCR.helpkey="MC Remap Control Register"
-AT91C_MC_RCR.access=memorymapped
-AT91C_MC_RCR.address=0xFFFFFF00
-AT91C_MC_RCR.width=32
-AT91C_MC_RCR.byteEndian=little
-AT91C_MC_RCR.type=enum
-AT91C_MC_RCR.enum.0.name=*** Write only ***
-AT91C_MC_RCR.enum.1.name=Error
-AT91C_MC_FCR.name="AT91C_MC_FCR"
-AT91C_MC_FCR.description="MC Flash Command Register"
-AT91C_MC_FCR.helpkey="MC Flash Command Register"
-AT91C_MC_FCR.access=memorymapped
-AT91C_MC_FCR.address=0xFFFFFF64
-AT91C_MC_FCR.width=32
-AT91C_MC_FCR.byteEndian=little
-AT91C_MC_FCR.type=enum
-AT91C_MC_FCR.enum.0.name=*** Write only ***
-AT91C_MC_FCR.enum.1.name=Error
-AT91C_MC_AASR.name="AT91C_MC_AASR"
-AT91C_MC_AASR.description="MC Abort Address Status Register"
-AT91C_MC_AASR.helpkey="MC Abort Address Status Register"
-AT91C_MC_AASR.access=memorymapped
-AT91C_MC_AASR.address=0xFFFFFF08
-AT91C_MC_AASR.width=32
-AT91C_MC_AASR.byteEndian=little
-AT91C_MC_AASR.permission.write=none
-AT91C_MC_FSR.name="AT91C_MC_FSR"
-AT91C_MC_FSR.description="MC Flash Status Register"
-AT91C_MC_FSR.helpkey="MC Flash Status Register"
-AT91C_MC_FSR.access=memorymapped
-AT91C_MC_FSR.address=0xFFFFFF68
-AT91C_MC_FSR.width=32
-AT91C_MC_FSR.byteEndian=little
-AT91C_MC_FSR.permission.write=none
-AT91C_MC_FMR.name="AT91C_MC_FMR"
-AT91C_MC_FMR.description="MC Flash Mode Register"
-AT91C_MC_FMR.helpkey="MC Flash Mode Register"
-AT91C_MC_FMR.access=memorymapped
-AT91C_MC_FMR.address=0xFFFFFF60
-AT91C_MC_FMR.width=32
-AT91C_MC_FMR.byteEndian=little
-# ========== Register definition for PDC_SPI peripheral ==========
-AT91C_SPI_PTCR.name="AT91C_SPI_PTCR"
-AT91C_SPI_PTCR.description="PDC Transfer Control Register"
-AT91C_SPI_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_SPI_PTCR.access=memorymapped
-AT91C_SPI_PTCR.address=0xFFFE0120
-AT91C_SPI_PTCR.width=32
-AT91C_SPI_PTCR.byteEndian=little
-AT91C_SPI_PTCR.type=enum
-AT91C_SPI_PTCR.enum.0.name=*** Write only ***
-AT91C_SPI_PTCR.enum.1.name=Error
-AT91C_SPI_TPR.name="AT91C_SPI_TPR"
-AT91C_SPI_TPR.description="Transmit Pointer Register"
-AT91C_SPI_TPR.helpkey="Transmit Pointer Register"
-AT91C_SPI_TPR.access=memorymapped
-AT91C_SPI_TPR.address=0xFFFE0108
-AT91C_SPI_TPR.width=32
-AT91C_SPI_TPR.byteEndian=little
-AT91C_SPI_TCR.name="AT91C_SPI_TCR"
-AT91C_SPI_TCR.description="Transmit Counter Register"
-AT91C_SPI_TCR.helpkey="Transmit Counter Register"
-AT91C_SPI_TCR.access=memorymapped
-AT91C_SPI_TCR.address=0xFFFE010C
-AT91C_SPI_TCR.width=32
-AT91C_SPI_TCR.byteEndian=little
-AT91C_SPI_RCR.name="AT91C_SPI_RCR"
-AT91C_SPI_RCR.description="Receive Counter Register"
-AT91C_SPI_RCR.helpkey="Receive Counter Register"
-AT91C_SPI_RCR.access=memorymapped
-AT91C_SPI_RCR.address=0xFFFE0104
-AT91C_SPI_RCR.width=32
-AT91C_SPI_RCR.byteEndian=little
-AT91C_SPI_PTSR.name="AT91C_SPI_PTSR"
-AT91C_SPI_PTSR.description="PDC Transfer Status Register"
-AT91C_SPI_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_SPI_PTSR.access=memorymapped
-AT91C_SPI_PTSR.address=0xFFFE0124
-AT91C_SPI_PTSR.width=32
-AT91C_SPI_PTSR.byteEndian=little
-AT91C_SPI_PTSR.permission.write=none
-AT91C_SPI_RNPR.name="AT91C_SPI_RNPR"
-AT91C_SPI_RNPR.description="Receive Next Pointer Register"
-AT91C_SPI_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_SPI_RNPR.access=memorymapped
-AT91C_SPI_RNPR.address=0xFFFE0110
-AT91C_SPI_RNPR.width=32
-AT91C_SPI_RNPR.byteEndian=little
-AT91C_SPI_RPR.name="AT91C_SPI_RPR"
-AT91C_SPI_RPR.description="Receive Pointer Register"
-AT91C_SPI_RPR.helpkey="Receive Pointer Register"
-AT91C_SPI_RPR.access=memorymapped
-AT91C_SPI_RPR.address=0xFFFE0100
-AT91C_SPI_RPR.width=32
-AT91C_SPI_RPR.byteEndian=little
-AT91C_SPI_TNCR.name="AT91C_SPI_TNCR"
-AT91C_SPI_TNCR.description="Transmit Next Counter Register"
-AT91C_SPI_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_SPI_TNCR.access=memorymapped
-AT91C_SPI_TNCR.address=0xFFFE011C
-AT91C_SPI_TNCR.width=32
-AT91C_SPI_TNCR.byteEndian=little
-AT91C_SPI_RNCR.name="AT91C_SPI_RNCR"
-AT91C_SPI_RNCR.description="Receive Next Counter Register"
-AT91C_SPI_RNCR.helpkey="Receive Next Counter Register"
-AT91C_SPI_RNCR.access=memorymapped
-AT91C_SPI_RNCR.address=0xFFFE0114
-AT91C_SPI_RNCR.width=32
-AT91C_SPI_RNCR.byteEndian=little
-AT91C_SPI_TNPR.name="AT91C_SPI_TNPR"
-AT91C_SPI_TNPR.description="Transmit Next Pointer Register"
-AT91C_SPI_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_SPI_TNPR.access=memorymapped
-AT91C_SPI_TNPR.address=0xFFFE0118
-AT91C_SPI_TNPR.width=32
-AT91C_SPI_TNPR.byteEndian=little
-# ========== Register definition for SPI peripheral ==========
-AT91C_SPI_IER.name="AT91C_SPI_IER"
-AT91C_SPI_IER.description="Interrupt Enable Register"
-AT91C_SPI_IER.helpkey="Interrupt Enable Register"
-AT91C_SPI_IER.access=memorymapped
-AT91C_SPI_IER.address=0xFFFE0014
-AT91C_SPI_IER.width=32
-AT91C_SPI_IER.byteEndian=little
-AT91C_SPI_IER.type=enum
-AT91C_SPI_IER.enum.0.name=*** Write only ***
-AT91C_SPI_IER.enum.1.name=Error
-AT91C_SPI_SR.name="AT91C_SPI_SR"
-AT91C_SPI_SR.description="Status Register"
-AT91C_SPI_SR.helpkey="Status Register"
-AT91C_SPI_SR.access=memorymapped
-AT91C_SPI_SR.address=0xFFFE0010
-AT91C_SPI_SR.width=32
-AT91C_SPI_SR.byteEndian=little
-AT91C_SPI_SR.permission.write=none
-AT91C_SPI_IDR.name="AT91C_SPI_IDR"
-AT91C_SPI_IDR.description="Interrupt Disable Register"
-AT91C_SPI_IDR.helpkey="Interrupt Disable Register"
-AT91C_SPI_IDR.access=memorymapped
-AT91C_SPI_IDR.address=0xFFFE0018
-AT91C_SPI_IDR.width=32
-AT91C_SPI_IDR.byteEndian=little
-AT91C_SPI_IDR.type=enum
-AT91C_SPI_IDR.enum.0.name=*** Write only ***
-AT91C_SPI_IDR.enum.1.name=Error
-AT91C_SPI_CR.name="AT91C_SPI_CR"
-AT91C_SPI_CR.description="Control Register"
-AT91C_SPI_CR.helpkey="Control Register"
-AT91C_SPI_CR.access=memorymapped
-AT91C_SPI_CR.address=0xFFFE0000
-AT91C_SPI_CR.width=32
-AT91C_SPI_CR.byteEndian=little
-AT91C_SPI_CR.permission.write=none
-AT91C_SPI_MR.name="AT91C_SPI_MR"
-AT91C_SPI_MR.description="Mode Register"
-AT91C_SPI_MR.helpkey="Mode Register"
-AT91C_SPI_MR.access=memorymapped
-AT91C_SPI_MR.address=0xFFFE0004
-AT91C_SPI_MR.width=32
-AT91C_SPI_MR.byteEndian=little
-AT91C_SPI_IMR.name="AT91C_SPI_IMR"
-AT91C_SPI_IMR.description="Interrupt Mask Register"
-AT91C_SPI_IMR.helpkey="Interrupt Mask Register"
-AT91C_SPI_IMR.access=memorymapped
-AT91C_SPI_IMR.address=0xFFFE001C
-AT91C_SPI_IMR.width=32
-AT91C_SPI_IMR.byteEndian=little
-AT91C_SPI_IMR.permission.write=none
-AT91C_SPI_TDR.name="AT91C_SPI_TDR"
-AT91C_SPI_TDR.description="Transmit Data Register"
-AT91C_SPI_TDR.helpkey="Transmit Data Register"
-AT91C_SPI_TDR.access=memorymapped
-AT91C_SPI_TDR.address=0xFFFE000C
-AT91C_SPI_TDR.width=32
-AT91C_SPI_TDR.byteEndian=little
-AT91C_SPI_TDR.type=enum
-AT91C_SPI_TDR.enum.0.name=*** Write only ***
-AT91C_SPI_TDR.enum.1.name=Error
-AT91C_SPI_RDR.name="AT91C_SPI_RDR"
-AT91C_SPI_RDR.description="Receive Data Register"
-AT91C_SPI_RDR.helpkey="Receive Data Register"
-AT91C_SPI_RDR.access=memorymapped
-AT91C_SPI_RDR.address=0xFFFE0008
-AT91C_SPI_RDR.width=32
-AT91C_SPI_RDR.byteEndian=little
-AT91C_SPI_RDR.permission.write=none
-AT91C_SPI_CSR.name="AT91C_SPI_CSR"
-AT91C_SPI_CSR.description="Chip Select Register"
-AT91C_SPI_CSR.helpkey="Chip Select Register"
-AT91C_SPI_CSR.access=memorymapped
-AT91C_SPI_CSR.address=0xFFFE0030
-AT91C_SPI_CSR.width=32
-AT91C_SPI_CSR.byteEndian=little
-# ========== Register definition for PDC_ADC peripheral ==========
-AT91C_ADC_PTSR.name="AT91C_ADC_PTSR"
-AT91C_ADC_PTSR.description="PDC Transfer Status Register"
-AT91C_ADC_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_ADC_PTSR.access=memorymapped
-AT91C_ADC_PTSR.address=0xFFFD8124
-AT91C_ADC_PTSR.width=32
-AT91C_ADC_PTSR.byteEndian=little
-AT91C_ADC_PTSR.permission.write=none
-AT91C_ADC_PTCR.name="AT91C_ADC_PTCR"
-AT91C_ADC_PTCR.description="PDC Transfer Control Register"
-AT91C_ADC_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_ADC_PTCR.access=memorymapped
-AT91C_ADC_PTCR.address=0xFFFD8120
-AT91C_ADC_PTCR.width=32
-AT91C_ADC_PTCR.byteEndian=little
-AT91C_ADC_PTCR.type=enum
-AT91C_ADC_PTCR.enum.0.name=*** Write only ***
-AT91C_ADC_PTCR.enum.1.name=Error
-AT91C_ADC_TNPR.name="AT91C_ADC_TNPR"
-AT91C_ADC_TNPR.description="Transmit Next Pointer Register"
-AT91C_ADC_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_ADC_TNPR.access=memorymapped
-AT91C_ADC_TNPR.address=0xFFFD8118
-AT91C_ADC_TNPR.width=32
-AT91C_ADC_TNPR.byteEndian=little
-AT91C_ADC_TNCR.name="AT91C_ADC_TNCR"
-AT91C_ADC_TNCR.description="Transmit Next Counter Register"
-AT91C_ADC_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_ADC_TNCR.access=memorymapped
-AT91C_ADC_TNCR.address=0xFFFD811C
-AT91C_ADC_TNCR.width=32
-AT91C_ADC_TNCR.byteEndian=little
-AT91C_ADC_RNPR.name="AT91C_ADC_RNPR"
-AT91C_ADC_RNPR.description="Receive Next Pointer Register"
-AT91C_ADC_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_ADC_RNPR.access=memorymapped
-AT91C_ADC_RNPR.address=0xFFFD8110
-AT91C_ADC_RNPR.width=32
-AT91C_ADC_RNPR.byteEndian=little
-AT91C_ADC_RNCR.name="AT91C_ADC_RNCR"
-AT91C_ADC_RNCR.description="Receive Next Counter Register"
-AT91C_ADC_RNCR.helpkey="Receive Next Counter Register"
-AT91C_ADC_RNCR.access=memorymapped
-AT91C_ADC_RNCR.address=0xFFFD8114
-AT91C_ADC_RNCR.width=32
-AT91C_ADC_RNCR.byteEndian=little
-AT91C_ADC_RPR.name="AT91C_ADC_RPR"
-AT91C_ADC_RPR.description="Receive Pointer Register"
-AT91C_ADC_RPR.helpkey="Receive Pointer Register"
-AT91C_ADC_RPR.access=memorymapped
-AT91C_ADC_RPR.address=0xFFFD8100
-AT91C_ADC_RPR.width=32
-AT91C_ADC_RPR.byteEndian=little
-AT91C_ADC_TCR.name="AT91C_ADC_TCR"
-AT91C_ADC_TCR.description="Transmit Counter Register"
-AT91C_ADC_TCR.helpkey="Transmit Counter Register"
-AT91C_ADC_TCR.access=memorymapped
-AT91C_ADC_TCR.address=0xFFFD810C
-AT91C_ADC_TCR.width=32
-AT91C_ADC_TCR.byteEndian=little
-AT91C_ADC_TPR.name="AT91C_ADC_TPR"
-AT91C_ADC_TPR.description="Transmit Pointer Register"
-AT91C_ADC_TPR.helpkey="Transmit Pointer Register"
-AT91C_ADC_TPR.access=memorymapped
-AT91C_ADC_TPR.address=0xFFFD8108
-AT91C_ADC_TPR.width=32
-AT91C_ADC_TPR.byteEndian=little
-AT91C_ADC_RCR.name="AT91C_ADC_RCR"
-AT91C_ADC_RCR.description="Receive Counter Register"
-AT91C_ADC_RCR.helpkey="Receive Counter Register"
-AT91C_ADC_RCR.access=memorymapped
-AT91C_ADC_RCR.address=0xFFFD8104
-AT91C_ADC_RCR.width=32
-AT91C_ADC_RCR.byteEndian=little
-# ========== Register definition for ADC peripheral ==========
-AT91C_ADC_CDR2.name="AT91C_ADC_CDR2"
-AT91C_ADC_CDR2.description="ADC Channel Data Register 2"
-AT91C_ADC_CDR2.helpkey="ADC Channel Data Register 2"
-AT91C_ADC_CDR2.access=memorymapped
-AT91C_ADC_CDR2.address=0xFFFD8038
-AT91C_ADC_CDR2.width=32
-AT91C_ADC_CDR2.byteEndian=little
-AT91C_ADC_CDR2.permission.write=none
-AT91C_ADC_CDR3.name="AT91C_ADC_CDR3"
-AT91C_ADC_CDR3.description="ADC Channel Data Register 3"
-AT91C_ADC_CDR3.helpkey="ADC Channel Data Register 3"
-AT91C_ADC_CDR3.access=memorymapped
-AT91C_ADC_CDR3.address=0xFFFD803C
-AT91C_ADC_CDR3.width=32
-AT91C_ADC_CDR3.byteEndian=little
-AT91C_ADC_CDR3.permission.write=none
-AT91C_ADC_CDR0.name="AT91C_ADC_CDR0"
-AT91C_ADC_CDR0.description="ADC Channel Data Register 0"
-AT91C_ADC_CDR0.helpkey="ADC Channel Data Register 0"
-AT91C_ADC_CDR0.access=memorymapped
-AT91C_ADC_CDR0.address=0xFFFD8030
-AT91C_ADC_CDR0.width=32
-AT91C_ADC_CDR0.byteEndian=little
-AT91C_ADC_CDR0.permission.write=none
-AT91C_ADC_CDR5.name="AT91C_ADC_CDR5"
-AT91C_ADC_CDR5.description="ADC Channel Data Register 5"
-AT91C_ADC_CDR5.helpkey="ADC Channel Data Register 5"
-AT91C_ADC_CDR5.access=memorymapped
-AT91C_ADC_CDR5.address=0xFFFD8044
-AT91C_ADC_CDR5.width=32
-AT91C_ADC_CDR5.byteEndian=little
-AT91C_ADC_CDR5.permission.write=none
-AT91C_ADC_CHDR.name="AT91C_ADC_CHDR"
-AT91C_ADC_CHDR.description="ADC Channel Disable Register"
-AT91C_ADC_CHDR.helpkey="ADC Channel Disable Register"
-AT91C_ADC_CHDR.access=memorymapped
-AT91C_ADC_CHDR.address=0xFFFD8014
-AT91C_ADC_CHDR.width=32
-AT91C_ADC_CHDR.byteEndian=little
-AT91C_ADC_CHDR.type=enum
-AT91C_ADC_CHDR.enum.0.name=*** Write only ***
-AT91C_ADC_CHDR.enum.1.name=Error
-AT91C_ADC_SR.name="AT91C_ADC_SR"
-AT91C_ADC_SR.description="ADC Status Register"
-AT91C_ADC_SR.helpkey="ADC Status Register"
-AT91C_ADC_SR.access=memorymapped
-AT91C_ADC_SR.address=0xFFFD801C
-AT91C_ADC_SR.width=32
-AT91C_ADC_SR.byteEndian=little
-AT91C_ADC_SR.permission.write=none
-AT91C_ADC_CDR4.name="AT91C_ADC_CDR4"
-AT91C_ADC_CDR4.description="ADC Channel Data Register 4"
-AT91C_ADC_CDR4.helpkey="ADC Channel Data Register 4"
-AT91C_ADC_CDR4.access=memorymapped
-AT91C_ADC_CDR4.address=0xFFFD8040
-AT91C_ADC_CDR4.width=32
-AT91C_ADC_CDR4.byteEndian=little
-AT91C_ADC_CDR4.permission.write=none
-AT91C_ADC_CDR1.name="AT91C_ADC_CDR1"
-AT91C_ADC_CDR1.description="ADC Channel Data Register 1"
-AT91C_ADC_CDR1.helpkey="ADC Channel Data Register 1"
-AT91C_ADC_CDR1.access=memorymapped
-AT91C_ADC_CDR1.address=0xFFFD8034
-AT91C_ADC_CDR1.width=32
-AT91C_ADC_CDR1.byteEndian=little
-AT91C_ADC_CDR1.permission.write=none
-AT91C_ADC_LCDR.name="AT91C_ADC_LCDR"
-AT91C_ADC_LCDR.description="ADC Last Converted Data Register"
-AT91C_ADC_LCDR.helpkey="ADC Last Converted Data Register"
-AT91C_ADC_LCDR.access=memorymapped
-AT91C_ADC_LCDR.address=0xFFFD8020
-AT91C_ADC_LCDR.width=32
-AT91C_ADC_LCDR.byteEndian=little
-AT91C_ADC_LCDR.permission.write=none
-AT91C_ADC_IDR.name="AT91C_ADC_IDR"
-AT91C_ADC_IDR.description="ADC Interrupt Disable Register"
-AT91C_ADC_IDR.helpkey="ADC Interrupt Disable Register"
-AT91C_ADC_IDR.access=memorymapped
-AT91C_ADC_IDR.address=0xFFFD8028
-AT91C_ADC_IDR.width=32
-AT91C_ADC_IDR.byteEndian=little
-AT91C_ADC_IDR.type=enum
-AT91C_ADC_IDR.enum.0.name=*** Write only ***
-AT91C_ADC_IDR.enum.1.name=Error
-AT91C_ADC_CR.name="AT91C_ADC_CR"
-AT91C_ADC_CR.description="ADC Control Register"
-AT91C_ADC_CR.helpkey="ADC Control Register"
-AT91C_ADC_CR.access=memorymapped
-AT91C_ADC_CR.address=0xFFFD8000
-AT91C_ADC_CR.width=32
-AT91C_ADC_CR.byteEndian=little
-AT91C_ADC_CR.type=enum
-AT91C_ADC_CR.enum.0.name=*** Write only ***
-AT91C_ADC_CR.enum.1.name=Error
-AT91C_ADC_CDR7.name="AT91C_ADC_CDR7"
-AT91C_ADC_CDR7.description="ADC Channel Data Register 7"
-AT91C_ADC_CDR7.helpkey="ADC Channel Data Register 7"
-AT91C_ADC_CDR7.access=memorymapped
-AT91C_ADC_CDR7.address=0xFFFD804C
-AT91C_ADC_CDR7.width=32
-AT91C_ADC_CDR7.byteEndian=little
-AT91C_ADC_CDR7.permission.write=none
-AT91C_ADC_CDR6.name="AT91C_ADC_CDR6"
-AT91C_ADC_CDR6.description="ADC Channel Data Register 6"
-AT91C_ADC_CDR6.helpkey="ADC Channel Data Register 6"
-AT91C_ADC_CDR6.access=memorymapped
-AT91C_ADC_CDR6.address=0xFFFD8048
-AT91C_ADC_CDR6.width=32
-AT91C_ADC_CDR6.byteEndian=little
-AT91C_ADC_CDR6.permission.write=none
-AT91C_ADC_IER.name="AT91C_ADC_IER"
-AT91C_ADC_IER.description="ADC Interrupt Enable Register"
-AT91C_ADC_IER.helpkey="ADC Interrupt Enable Register"
-AT91C_ADC_IER.access=memorymapped
-AT91C_ADC_IER.address=0xFFFD8024
-AT91C_ADC_IER.width=32
-AT91C_ADC_IER.byteEndian=little
-AT91C_ADC_IER.type=enum
-AT91C_ADC_IER.enum.0.name=*** Write only ***
-AT91C_ADC_IER.enum.1.name=Error
-AT91C_ADC_CHER.name="AT91C_ADC_CHER"
-AT91C_ADC_CHER.description="ADC Channel Enable Register"
-AT91C_ADC_CHER.helpkey="ADC Channel Enable Register"
-AT91C_ADC_CHER.access=memorymapped
-AT91C_ADC_CHER.address=0xFFFD8010
-AT91C_ADC_CHER.width=32
-AT91C_ADC_CHER.byteEndian=little
-AT91C_ADC_CHER.type=enum
-AT91C_ADC_CHER.enum.0.name=*** Write only ***
-AT91C_ADC_CHER.enum.1.name=Error
-AT91C_ADC_CHSR.name="AT91C_ADC_CHSR"
-AT91C_ADC_CHSR.description="ADC Channel Status Register"
-AT91C_ADC_CHSR.helpkey="ADC Channel Status Register"
-AT91C_ADC_CHSR.access=memorymapped
-AT91C_ADC_CHSR.address=0xFFFD8018
-AT91C_ADC_CHSR.width=32
-AT91C_ADC_CHSR.byteEndian=little
-AT91C_ADC_CHSR.permission.write=none
-AT91C_ADC_MR.name="AT91C_ADC_MR"
-AT91C_ADC_MR.description="ADC Mode Register"
-AT91C_ADC_MR.helpkey="ADC Mode Register"
-AT91C_ADC_MR.access=memorymapped
-AT91C_ADC_MR.address=0xFFFD8004
-AT91C_ADC_MR.width=32
-AT91C_ADC_MR.byteEndian=little
-AT91C_ADC_IMR.name="AT91C_ADC_IMR"
-AT91C_ADC_IMR.description="ADC Interrupt Mask Register"
-AT91C_ADC_IMR.helpkey="ADC Interrupt Mask Register"
-AT91C_ADC_IMR.access=memorymapped
-AT91C_ADC_IMR.address=0xFFFD802C
-AT91C_ADC_IMR.width=32
-AT91C_ADC_IMR.byteEndian=little
-AT91C_ADC_IMR.permission.write=none
-# ========== Register definition for PDC_SSC peripheral ==========
-AT91C_SSC_TNCR.name="AT91C_SSC_TNCR"
-AT91C_SSC_TNCR.description="Transmit Next Counter Register"
-AT91C_SSC_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_SSC_TNCR.access=memorymapped
-AT91C_SSC_TNCR.address=0xFFFD411C
-AT91C_SSC_TNCR.width=32
-AT91C_SSC_TNCR.byteEndian=little
-AT91C_SSC_RPR.name="AT91C_SSC_RPR"
-AT91C_SSC_RPR.description="Receive Pointer Register"
-AT91C_SSC_RPR.helpkey="Receive Pointer Register"
-AT91C_SSC_RPR.access=memorymapped
-AT91C_SSC_RPR.address=0xFFFD4100
-AT91C_SSC_RPR.width=32
-AT91C_SSC_RPR.byteEndian=little
-AT91C_SSC_RNCR.name="AT91C_SSC_RNCR"
-AT91C_SSC_RNCR.description="Receive Next Counter Register"
-AT91C_SSC_RNCR.helpkey="Receive Next Counter Register"
-AT91C_SSC_RNCR.access=memorymapped
-AT91C_SSC_RNCR.address=0xFFFD4114
-AT91C_SSC_RNCR.width=32
-AT91C_SSC_RNCR.byteEndian=little
-AT91C_SSC_TPR.name="AT91C_SSC_TPR"
-AT91C_SSC_TPR.description="Transmit Pointer Register"
-AT91C_SSC_TPR.helpkey="Transmit Pointer Register"
-AT91C_SSC_TPR.access=memorymapped
-AT91C_SSC_TPR.address=0xFFFD4108
-AT91C_SSC_TPR.width=32
-AT91C_SSC_TPR.byteEndian=little
-AT91C_SSC_PTCR.name="AT91C_SSC_PTCR"
-AT91C_SSC_PTCR.description="PDC Transfer Control Register"
-AT91C_SSC_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_SSC_PTCR.access=memorymapped
-AT91C_SSC_PTCR.address=0xFFFD4120
-AT91C_SSC_PTCR.width=32
-AT91C_SSC_PTCR.byteEndian=little
-AT91C_SSC_PTCR.type=enum
-AT91C_SSC_PTCR.enum.0.name=*** Write only ***
-AT91C_SSC_PTCR.enum.1.name=Error
-AT91C_SSC_TCR.name="AT91C_SSC_TCR"
-AT91C_SSC_TCR.description="Transmit Counter Register"
-AT91C_SSC_TCR.helpkey="Transmit Counter Register"
-AT91C_SSC_TCR.access=memorymapped
-AT91C_SSC_TCR.address=0xFFFD410C
-AT91C_SSC_TCR.width=32
-AT91C_SSC_TCR.byteEndian=little
-AT91C_SSC_RCR.name="AT91C_SSC_RCR"
-AT91C_SSC_RCR.description="Receive Counter Register"
-AT91C_SSC_RCR.helpkey="Receive Counter Register"
-AT91C_SSC_RCR.access=memorymapped
-AT91C_SSC_RCR.address=0xFFFD4104
-AT91C_SSC_RCR.width=32
-AT91C_SSC_RCR.byteEndian=little
-AT91C_SSC_RNPR.name="AT91C_SSC_RNPR"
-AT91C_SSC_RNPR.description="Receive Next Pointer Register"
-AT91C_SSC_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_SSC_RNPR.access=memorymapped
-AT91C_SSC_RNPR.address=0xFFFD4110
-AT91C_SSC_RNPR.width=32
-AT91C_SSC_RNPR.byteEndian=little
-AT91C_SSC_TNPR.name="AT91C_SSC_TNPR"
-AT91C_SSC_TNPR.description="Transmit Next Pointer Register"
-AT91C_SSC_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_SSC_TNPR.access=memorymapped
-AT91C_SSC_TNPR.address=0xFFFD4118
-AT91C_SSC_TNPR.width=32
-AT91C_SSC_TNPR.byteEndian=little
-AT91C_SSC_PTSR.name="AT91C_SSC_PTSR"
-AT91C_SSC_PTSR.description="PDC Transfer Status Register"
-AT91C_SSC_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_SSC_PTSR.access=memorymapped
-AT91C_SSC_PTSR.address=0xFFFD4124
-AT91C_SSC_PTSR.width=32
-AT91C_SSC_PTSR.byteEndian=little
-AT91C_SSC_PTSR.permission.write=none
-# ========== Register definition for SSC peripheral ==========
-AT91C_SSC_RHR.name="AT91C_SSC_RHR"
-AT91C_SSC_RHR.description="Receive Holding Register"
-AT91C_SSC_RHR.helpkey="Receive Holding Register"
-AT91C_SSC_RHR.access=memorymapped
-AT91C_SSC_RHR.address=0xFFFD4020
-AT91C_SSC_RHR.width=32
-AT91C_SSC_RHR.byteEndian=little
-AT91C_SSC_RHR.permission.write=none
-AT91C_SSC_RSHR.name="AT91C_SSC_RSHR"
-AT91C_SSC_RSHR.description="Receive Sync Holding Register"
-AT91C_SSC_RSHR.helpkey="Receive Sync Holding Register"
-AT91C_SSC_RSHR.access=memorymapped
-AT91C_SSC_RSHR.address=0xFFFD4030
-AT91C_SSC_RSHR.width=32
-AT91C_SSC_RSHR.byteEndian=little
-AT91C_SSC_RSHR.permission.write=none
-AT91C_SSC_TFMR.name="AT91C_SSC_TFMR"
-AT91C_SSC_TFMR.description="Transmit Frame Mode Register"
-AT91C_SSC_TFMR.helpkey="Transmit Frame Mode Register"
-AT91C_SSC_TFMR.access=memorymapped
-AT91C_SSC_TFMR.address=0xFFFD401C
-AT91C_SSC_TFMR.width=32
-AT91C_SSC_TFMR.byteEndian=little
-AT91C_SSC_IDR.name="AT91C_SSC_IDR"
-AT91C_SSC_IDR.description="Interrupt Disable Register"
-AT91C_SSC_IDR.helpkey="Interrupt Disable Register"
-AT91C_SSC_IDR.access=memorymapped
-AT91C_SSC_IDR.address=0xFFFD4048
-AT91C_SSC_IDR.width=32
-AT91C_SSC_IDR.byteEndian=little
-AT91C_SSC_IDR.type=enum
-AT91C_SSC_IDR.enum.0.name=*** Write only ***
-AT91C_SSC_IDR.enum.1.name=Error
-AT91C_SSC_THR.name="AT91C_SSC_THR"
-AT91C_SSC_THR.description="Transmit Holding Register"
-AT91C_SSC_THR.helpkey="Transmit Holding Register"
-AT91C_SSC_THR.access=memorymapped
-AT91C_SSC_THR.address=0xFFFD4024
-AT91C_SSC_THR.width=32
-AT91C_SSC_THR.byteEndian=little
-AT91C_SSC_THR.type=enum
-AT91C_SSC_THR.enum.0.name=*** Write only ***
-AT91C_SSC_THR.enum.1.name=Error
-AT91C_SSC_RCMR.name="AT91C_SSC_RCMR"
-AT91C_SSC_RCMR.description="Receive Clock ModeRegister"
-AT91C_SSC_RCMR.helpkey="Receive Clock ModeRegister"
-AT91C_SSC_RCMR.access=memorymapped
-AT91C_SSC_RCMR.address=0xFFFD4010
-AT91C_SSC_RCMR.width=32
-AT91C_SSC_RCMR.byteEndian=little
-AT91C_SSC_IER.name="AT91C_SSC_IER"
-AT91C_SSC_IER.description="Interrupt Enable Register"
-AT91C_SSC_IER.helpkey="Interrupt Enable Register"
-AT91C_SSC_IER.access=memorymapped
-AT91C_SSC_IER.address=0xFFFD4044
-AT91C_SSC_IER.width=32
-AT91C_SSC_IER.byteEndian=little
-AT91C_SSC_IER.type=enum
-AT91C_SSC_IER.enum.0.name=*** Write only ***
-AT91C_SSC_IER.enum.1.name=Error
-AT91C_SSC_TSHR.name="AT91C_SSC_TSHR"
-AT91C_SSC_TSHR.description="Transmit Sync Holding Register"
-AT91C_SSC_TSHR.helpkey="Transmit Sync Holding Register"
-AT91C_SSC_TSHR.access=memorymapped
-AT91C_SSC_TSHR.address=0xFFFD4034
-AT91C_SSC_TSHR.width=32
-AT91C_SSC_TSHR.byteEndian=little
-AT91C_SSC_SR.name="AT91C_SSC_SR"
-AT91C_SSC_SR.description="Status Register"
-AT91C_SSC_SR.helpkey="Status Register"
-AT91C_SSC_SR.access=memorymapped
-AT91C_SSC_SR.address=0xFFFD4040
-AT91C_SSC_SR.width=32
-AT91C_SSC_SR.byteEndian=little
-AT91C_SSC_SR.permission.write=none
-AT91C_SSC_CMR.name="AT91C_SSC_CMR"
-AT91C_SSC_CMR.description="Clock Mode Register"
-AT91C_SSC_CMR.helpkey="Clock Mode Register"
-AT91C_SSC_CMR.access=memorymapped
-AT91C_SSC_CMR.address=0xFFFD4004
-AT91C_SSC_CMR.width=32
-AT91C_SSC_CMR.byteEndian=little
-AT91C_SSC_TCMR.name="AT91C_SSC_TCMR"
-AT91C_SSC_TCMR.description="Transmit Clock Mode Register"
-AT91C_SSC_TCMR.helpkey="Transmit Clock Mode Register"
-AT91C_SSC_TCMR.access=memorymapped
-AT91C_SSC_TCMR.address=0xFFFD4018
-AT91C_SSC_TCMR.width=32
-AT91C_SSC_TCMR.byteEndian=little
-AT91C_SSC_CR.name="AT91C_SSC_CR"
-AT91C_SSC_CR.description="Control Register"
-AT91C_SSC_CR.helpkey="Control Register"
-AT91C_SSC_CR.access=memorymapped
-AT91C_SSC_CR.address=0xFFFD4000
-AT91C_SSC_CR.width=32
-AT91C_SSC_CR.byteEndian=little
-AT91C_SSC_CR.type=enum
-AT91C_SSC_CR.enum.0.name=*** Write only ***
-AT91C_SSC_CR.enum.1.name=Error
-AT91C_SSC_IMR.name="AT91C_SSC_IMR"
-AT91C_SSC_IMR.description="Interrupt Mask Register"
-AT91C_SSC_IMR.helpkey="Interrupt Mask Register"
-AT91C_SSC_IMR.access=memorymapped
-AT91C_SSC_IMR.address=0xFFFD404C
-AT91C_SSC_IMR.width=32
-AT91C_SSC_IMR.byteEndian=little
-AT91C_SSC_IMR.permission.write=none
-AT91C_SSC_RFMR.name="AT91C_SSC_RFMR"
-AT91C_SSC_RFMR.description="Receive Frame Mode Register"
-AT91C_SSC_RFMR.helpkey="Receive Frame Mode Register"
-AT91C_SSC_RFMR.access=memorymapped
-AT91C_SSC_RFMR.address=0xFFFD4014
-AT91C_SSC_RFMR.width=32
-AT91C_SSC_RFMR.byteEndian=little
-# ========== Register definition for PDC_US1 peripheral ==========
-AT91C_US1_RNCR.name="AT91C_US1_RNCR"
-AT91C_US1_RNCR.description="Receive Next Counter Register"
-AT91C_US1_RNCR.helpkey="Receive Next Counter Register"
-AT91C_US1_RNCR.access=memorymapped
-AT91C_US1_RNCR.address=0xFFFC4114
-AT91C_US1_RNCR.width=32
-AT91C_US1_RNCR.byteEndian=little
-AT91C_US1_PTCR.name="AT91C_US1_PTCR"
-AT91C_US1_PTCR.description="PDC Transfer Control Register"
-AT91C_US1_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_US1_PTCR.access=memorymapped
-AT91C_US1_PTCR.address=0xFFFC4120
-AT91C_US1_PTCR.width=32
-AT91C_US1_PTCR.byteEndian=little
-AT91C_US1_PTCR.type=enum
-AT91C_US1_PTCR.enum.0.name=*** Write only ***
-AT91C_US1_PTCR.enum.1.name=Error
-AT91C_US1_TCR.name="AT91C_US1_TCR"
-AT91C_US1_TCR.description="Transmit Counter Register"
-AT91C_US1_TCR.helpkey="Transmit Counter Register"
-AT91C_US1_TCR.access=memorymapped
-AT91C_US1_TCR.address=0xFFFC410C
-AT91C_US1_TCR.width=32
-AT91C_US1_TCR.byteEndian=little
-AT91C_US1_PTSR.name="AT91C_US1_PTSR"
-AT91C_US1_PTSR.description="PDC Transfer Status Register"
-AT91C_US1_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_US1_PTSR.access=memorymapped
-AT91C_US1_PTSR.address=0xFFFC4124
-AT91C_US1_PTSR.width=32
-AT91C_US1_PTSR.byteEndian=little
-AT91C_US1_PTSR.permission.write=none
-AT91C_US1_TNPR.name="AT91C_US1_TNPR"
-AT91C_US1_TNPR.description="Transmit Next Pointer Register"
-AT91C_US1_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_US1_TNPR.access=memorymapped
-AT91C_US1_TNPR.address=0xFFFC4118
-AT91C_US1_TNPR.width=32
-AT91C_US1_TNPR.byteEndian=little
-AT91C_US1_RCR.name="AT91C_US1_RCR"
-AT91C_US1_RCR.description="Receive Counter Register"
-AT91C_US1_RCR.helpkey="Receive Counter Register"
-AT91C_US1_RCR.access=memorymapped
-AT91C_US1_RCR.address=0xFFFC4104
-AT91C_US1_RCR.width=32
-AT91C_US1_RCR.byteEndian=little
-AT91C_US1_RNPR.name="AT91C_US1_RNPR"
-AT91C_US1_RNPR.description="Receive Next Pointer Register"
-AT91C_US1_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_US1_RNPR.access=memorymapped
-AT91C_US1_RNPR.address=0xFFFC4110
-AT91C_US1_RNPR.width=32
-AT91C_US1_RNPR.byteEndian=little
-AT91C_US1_RPR.name="AT91C_US1_RPR"
-AT91C_US1_RPR.description="Receive Pointer Register"
-AT91C_US1_RPR.helpkey="Receive Pointer Register"
-AT91C_US1_RPR.access=memorymapped
-AT91C_US1_RPR.address=0xFFFC4100
-AT91C_US1_RPR.width=32
-AT91C_US1_RPR.byteEndian=little
-AT91C_US1_TNCR.name="AT91C_US1_TNCR"
-AT91C_US1_TNCR.description="Transmit Next Counter Register"
-AT91C_US1_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_US1_TNCR.access=memorymapped
-AT91C_US1_TNCR.address=0xFFFC411C
-AT91C_US1_TNCR.width=32
-AT91C_US1_TNCR.byteEndian=little
-AT91C_US1_TPR.name="AT91C_US1_TPR"
-AT91C_US1_TPR.description="Transmit Pointer Register"
-AT91C_US1_TPR.helpkey="Transmit Pointer Register"
-AT91C_US1_TPR.access=memorymapped
-AT91C_US1_TPR.address=0xFFFC4108
-AT91C_US1_TPR.width=32
-AT91C_US1_TPR.byteEndian=little
-# ========== Register definition for US1 peripheral ==========
-AT91C_US1_IF.name="AT91C_US1_IF"
-AT91C_US1_IF.description="IRDA_FILTER Register"
-AT91C_US1_IF.helpkey="IRDA_FILTER Register"
-AT91C_US1_IF.access=memorymapped
-AT91C_US1_IF.address=0xFFFC404C
-AT91C_US1_IF.width=32
-AT91C_US1_IF.byteEndian=little
-AT91C_US1_NER.name="AT91C_US1_NER"
-AT91C_US1_NER.description="Nb Errors Register"
-AT91C_US1_NER.helpkey="Nb Errors Register"
-AT91C_US1_NER.access=memorymapped
-AT91C_US1_NER.address=0xFFFC4044
-AT91C_US1_NER.width=32
-AT91C_US1_NER.byteEndian=little
-AT91C_US1_NER.permission.write=none
-AT91C_US1_RTOR.name="AT91C_US1_RTOR"
-AT91C_US1_RTOR.description="Receiver Time-out Register"
-AT91C_US1_RTOR.helpkey="Receiver Time-out Register"
-AT91C_US1_RTOR.access=memorymapped
-AT91C_US1_RTOR.address=0xFFFC4024
-AT91C_US1_RTOR.width=32
-AT91C_US1_RTOR.byteEndian=little
-AT91C_US1_CSR.name="AT91C_US1_CSR"
-AT91C_US1_CSR.description="Channel Status Register"
-AT91C_US1_CSR.helpkey="Channel Status Register"
-AT91C_US1_CSR.access=memorymapped
-AT91C_US1_CSR.address=0xFFFC4014
-AT91C_US1_CSR.width=32
-AT91C_US1_CSR.byteEndian=little
-AT91C_US1_CSR.permission.write=none
-AT91C_US1_IDR.name="AT91C_US1_IDR"
-AT91C_US1_IDR.description="Interrupt Disable Register"
-AT91C_US1_IDR.helpkey="Interrupt Disable Register"
-AT91C_US1_IDR.access=memorymapped
-AT91C_US1_IDR.address=0xFFFC400C
-AT91C_US1_IDR.width=32
-AT91C_US1_IDR.byteEndian=little
-AT91C_US1_IDR.type=enum
-AT91C_US1_IDR.enum.0.name=*** Write only ***
-AT91C_US1_IDR.enum.1.name=Error
-AT91C_US1_IER.name="AT91C_US1_IER"
-AT91C_US1_IER.description="Interrupt Enable Register"
-AT91C_US1_IER.helpkey="Interrupt Enable Register"
-AT91C_US1_IER.access=memorymapped
-AT91C_US1_IER.address=0xFFFC4008
-AT91C_US1_IER.width=32
-AT91C_US1_IER.byteEndian=little
-AT91C_US1_IER.type=enum
-AT91C_US1_IER.enum.0.name=*** Write only ***
-AT91C_US1_IER.enum.1.name=Error
-AT91C_US1_THR.name="AT91C_US1_THR"
-AT91C_US1_THR.description="Transmitter Holding Register"
-AT91C_US1_THR.helpkey="Transmitter Holding Register"
-AT91C_US1_THR.access=memorymapped
-AT91C_US1_THR.address=0xFFFC401C
-AT91C_US1_THR.width=32
-AT91C_US1_THR.byteEndian=little
-AT91C_US1_THR.type=enum
-AT91C_US1_THR.enum.0.name=*** Write only ***
-AT91C_US1_THR.enum.1.name=Error
-AT91C_US1_TTGR.name="AT91C_US1_TTGR"
-AT91C_US1_TTGR.description="Transmitter Time-guard Register"
-AT91C_US1_TTGR.helpkey="Transmitter Time-guard Register"
-AT91C_US1_TTGR.access=memorymapped
-AT91C_US1_TTGR.address=0xFFFC4028
-AT91C_US1_TTGR.width=32
-AT91C_US1_TTGR.byteEndian=little
-AT91C_US1_RHR.name="AT91C_US1_RHR"
-AT91C_US1_RHR.description="Receiver Holding Register"
-AT91C_US1_RHR.helpkey="Receiver Holding Register"
-AT91C_US1_RHR.access=memorymapped
-AT91C_US1_RHR.address=0xFFFC4018
-AT91C_US1_RHR.width=32
-AT91C_US1_RHR.byteEndian=little
-AT91C_US1_RHR.permission.write=none
-AT91C_US1_BRGR.name="AT91C_US1_BRGR"
-AT91C_US1_BRGR.description="Baud Rate Generator Register"
-AT91C_US1_BRGR.helpkey="Baud Rate Generator Register"
-AT91C_US1_BRGR.access=memorymapped
-AT91C_US1_BRGR.address=0xFFFC4020
-AT91C_US1_BRGR.width=32
-AT91C_US1_BRGR.byteEndian=little
-AT91C_US1_IMR.name="AT91C_US1_IMR"
-AT91C_US1_IMR.description="Interrupt Mask Register"
-AT91C_US1_IMR.helpkey="Interrupt Mask Register"
-AT91C_US1_IMR.access=memorymapped
-AT91C_US1_IMR.address=0xFFFC4010
-AT91C_US1_IMR.width=32
-AT91C_US1_IMR.byteEndian=little
-AT91C_US1_IMR.permission.write=none
-AT91C_US1_FIDI.name="AT91C_US1_FIDI"
-AT91C_US1_FIDI.description="FI_DI_Ratio Register"
-AT91C_US1_FIDI.helpkey="FI_DI_Ratio Register"
-AT91C_US1_FIDI.access=memorymapped
-AT91C_US1_FIDI.address=0xFFFC4040
-AT91C_US1_FIDI.width=32
-AT91C_US1_FIDI.byteEndian=little
-AT91C_US1_CR.name="AT91C_US1_CR"
-AT91C_US1_CR.description="Control Register"
-AT91C_US1_CR.helpkey="Control Register"
-AT91C_US1_CR.access=memorymapped
-AT91C_US1_CR.address=0xFFFC4000
-AT91C_US1_CR.width=32
-AT91C_US1_CR.byteEndian=little
-AT91C_US1_CR.type=enum
-AT91C_US1_CR.enum.0.name=*** Write only ***
-AT91C_US1_CR.enum.1.name=Error
-AT91C_US1_MR.name="AT91C_US1_MR"
-AT91C_US1_MR.description="Mode Register"
-AT91C_US1_MR.helpkey="Mode Register"
-AT91C_US1_MR.access=memorymapped
-AT91C_US1_MR.address=0xFFFC4004
-AT91C_US1_MR.width=32
-AT91C_US1_MR.byteEndian=little
-# ========== Register definition for PDC_US0 peripheral ==========
-AT91C_US0_TNPR.name="AT91C_US0_TNPR"
-AT91C_US0_TNPR.description="Transmit Next Pointer Register"
-AT91C_US0_TNPR.helpkey="Transmit Next Pointer Register"
-AT91C_US0_TNPR.access=memorymapped
-AT91C_US0_TNPR.address=0xFFFC0118
-AT91C_US0_TNPR.width=32
-AT91C_US0_TNPR.byteEndian=little
-AT91C_US0_RNPR.name="AT91C_US0_RNPR"
-AT91C_US0_RNPR.description="Receive Next Pointer Register"
-AT91C_US0_RNPR.helpkey="Receive Next Pointer Register"
-AT91C_US0_RNPR.access=memorymapped
-AT91C_US0_RNPR.address=0xFFFC0110
-AT91C_US0_RNPR.width=32
-AT91C_US0_RNPR.byteEndian=little
-AT91C_US0_TCR.name="AT91C_US0_TCR"
-AT91C_US0_TCR.description="Transmit Counter Register"
-AT91C_US0_TCR.helpkey="Transmit Counter Register"
-AT91C_US0_TCR.access=memorymapped
-AT91C_US0_TCR.address=0xFFFC010C
-AT91C_US0_TCR.width=32
-AT91C_US0_TCR.byteEndian=little
-AT91C_US0_PTCR.name="AT91C_US0_PTCR"
-AT91C_US0_PTCR.description="PDC Transfer Control Register"
-AT91C_US0_PTCR.helpkey="PDC Transfer Control Register"
-AT91C_US0_PTCR.access=memorymapped
-AT91C_US0_PTCR.address=0xFFFC0120
-AT91C_US0_PTCR.width=32
-AT91C_US0_PTCR.byteEndian=little
-AT91C_US0_PTCR.type=enum
-AT91C_US0_PTCR.enum.0.name=*** Write only ***
-AT91C_US0_PTCR.enum.1.name=Error
-AT91C_US0_PTSR.name="AT91C_US0_PTSR"
-AT91C_US0_PTSR.description="PDC Transfer Status Register"
-AT91C_US0_PTSR.helpkey="PDC Transfer Status Register"
-AT91C_US0_PTSR.access=memorymapped
-AT91C_US0_PTSR.address=0xFFFC0124
-AT91C_US0_PTSR.width=32
-AT91C_US0_PTSR.byteEndian=little
-AT91C_US0_PTSR.permission.write=none
-AT91C_US0_TNCR.name="AT91C_US0_TNCR"
-AT91C_US0_TNCR.description="Transmit Next Counter Register"
-AT91C_US0_TNCR.helpkey="Transmit Next Counter Register"
-AT91C_US0_TNCR.access=memorymapped
-AT91C_US0_TNCR.address=0xFFFC011C
-AT91C_US0_TNCR.width=32
-AT91C_US0_TNCR.byteEndian=little
-AT91C_US0_TPR.name="AT91C_US0_TPR"
-AT91C_US0_TPR.description="Transmit Pointer Register"
-AT91C_US0_TPR.helpkey="Transmit Pointer Register"
-AT91C_US0_TPR.access=memorymapped
-AT91C_US0_TPR.address=0xFFFC0108
-AT91C_US0_TPR.width=32
-AT91C_US0_TPR.byteEndian=little
-AT91C_US0_RCR.name="AT91C_US0_RCR"
-AT91C_US0_RCR.description="Receive Counter Register"
-AT91C_US0_RCR.helpkey="Receive Counter Register"
-AT91C_US0_RCR.access=memorymapped
-AT91C_US0_RCR.address=0xFFFC0104
-AT91C_US0_RCR.width=32
-AT91C_US0_RCR.byteEndian=little
-AT91C_US0_RPR.name="AT91C_US0_RPR"
-AT91C_US0_RPR.description="Receive Pointer Register"
-AT91C_US0_RPR.helpkey="Receive Pointer Register"
-AT91C_US0_RPR.access=memorymapped
-AT91C_US0_RPR.address=0xFFFC0100
-AT91C_US0_RPR.width=32
-AT91C_US0_RPR.byteEndian=little
-AT91C_US0_RNCR.name="AT91C_US0_RNCR"
-AT91C_US0_RNCR.description="Receive Next Counter Register"
-AT91C_US0_RNCR.helpkey="Receive Next Counter Register"
-AT91C_US0_RNCR.access=memorymapped
-AT91C_US0_RNCR.address=0xFFFC0114
-AT91C_US0_RNCR.width=32
-AT91C_US0_RNCR.byteEndian=little
-# ========== Register definition for US0 peripheral ==========
-AT91C_US0_BRGR.name="AT91C_US0_BRGR"
-AT91C_US0_BRGR.description="Baud Rate Generator Register"
-AT91C_US0_BRGR.helpkey="Baud Rate Generator Register"
-AT91C_US0_BRGR.access=memorymapped
-AT91C_US0_BRGR.address=0xFFFC0020
-AT91C_US0_BRGR.width=32
-AT91C_US0_BRGR.byteEndian=little
-AT91C_US0_NER.name="AT91C_US0_NER"
-AT91C_US0_NER.description="Nb Errors Register"
-AT91C_US0_NER.helpkey="Nb Errors Register"
-AT91C_US0_NER.access=memorymapped
-AT91C_US0_NER.address=0xFFFC0044
-AT91C_US0_NER.width=32
-AT91C_US0_NER.byteEndian=little
-AT91C_US0_NER.permission.write=none
-AT91C_US0_CR.name="AT91C_US0_CR"
-AT91C_US0_CR.description="Control Register"
-AT91C_US0_CR.helpkey="Control Register"
-AT91C_US0_CR.access=memorymapped
-AT91C_US0_CR.address=0xFFFC0000
-AT91C_US0_CR.width=32
-AT91C_US0_CR.byteEndian=little
-AT91C_US0_CR.type=enum
-AT91C_US0_CR.enum.0.name=*** Write only ***
-AT91C_US0_CR.enum.1.name=Error
-AT91C_US0_IMR.name="AT91C_US0_IMR"
-AT91C_US0_IMR.description="Interrupt Mask Register"
-AT91C_US0_IMR.helpkey="Interrupt Mask Register"
-AT91C_US0_IMR.access=memorymapped
-AT91C_US0_IMR.address=0xFFFC0010
-AT91C_US0_IMR.width=32
-AT91C_US0_IMR.byteEndian=little
-AT91C_US0_IMR.permission.write=none
-AT91C_US0_FIDI.name="AT91C_US0_FIDI"
-AT91C_US0_FIDI.description="FI_DI_Ratio Register"
-AT91C_US0_FIDI.helpkey="FI_DI_Ratio Register"
-AT91C_US0_FIDI.access=memorymapped
-AT91C_US0_FIDI.address=0xFFFC0040
-AT91C_US0_FIDI.width=32
-AT91C_US0_FIDI.byteEndian=little
-AT91C_US0_TTGR.name="AT91C_US0_TTGR"
-AT91C_US0_TTGR.description="Transmitter Time-guard Register"
-AT91C_US0_TTGR.helpkey="Transmitter Time-guard Register"
-AT91C_US0_TTGR.access=memorymapped
-AT91C_US0_TTGR.address=0xFFFC0028
-AT91C_US0_TTGR.width=32
-AT91C_US0_TTGR.byteEndian=little
-AT91C_US0_MR.name="AT91C_US0_MR"
-AT91C_US0_MR.description="Mode Register"
-AT91C_US0_MR.helpkey="Mode Register"
-AT91C_US0_MR.access=memorymapped
-AT91C_US0_MR.address=0xFFFC0004
-AT91C_US0_MR.width=32
-AT91C_US0_MR.byteEndian=little
-AT91C_US0_RTOR.name="AT91C_US0_RTOR"
-AT91C_US0_RTOR.description="Receiver Time-out Register"
-AT91C_US0_RTOR.helpkey="Receiver Time-out Register"
-AT91C_US0_RTOR.access=memorymapped
-AT91C_US0_RTOR.address=0xFFFC0024
-AT91C_US0_RTOR.width=32
-AT91C_US0_RTOR.byteEndian=little
-AT91C_US0_CSR.name="AT91C_US0_CSR"
-AT91C_US0_CSR.description="Channel Status Register"
-AT91C_US0_CSR.helpkey="Channel Status Register"
-AT91C_US0_CSR.access=memorymapped
-AT91C_US0_CSR.address=0xFFFC0014
-AT91C_US0_CSR.width=32
-AT91C_US0_CSR.byteEndian=little
-AT91C_US0_CSR.permission.write=none
-AT91C_US0_RHR.name="AT91C_US0_RHR"
-AT91C_US0_RHR.description="Receiver Holding Register"
-AT91C_US0_RHR.helpkey="Receiver Holding Register"
-AT91C_US0_RHR.access=memorymapped
-AT91C_US0_RHR.address=0xFFFC0018
-AT91C_US0_RHR.width=32
-AT91C_US0_RHR.byteEndian=little
-AT91C_US0_RHR.permission.write=none
-AT91C_US0_IDR.name="AT91C_US0_IDR"
-AT91C_US0_IDR.description="Interrupt Disable Register"
-AT91C_US0_IDR.helpkey="Interrupt Disable Register"
-AT91C_US0_IDR.access=memorymapped
-AT91C_US0_IDR.address=0xFFFC000C
-AT91C_US0_IDR.width=32
-AT91C_US0_IDR.byteEndian=little
-AT91C_US0_IDR.type=enum
-AT91C_US0_IDR.enum.0.name=*** Write only ***
-AT91C_US0_IDR.enum.1.name=Error
-AT91C_US0_THR.name="AT91C_US0_THR"
-AT91C_US0_THR.description="Transmitter Holding Register"
-AT91C_US0_THR.helpkey="Transmitter Holding Register"
-AT91C_US0_THR.access=memorymapped
-AT91C_US0_THR.address=0xFFFC001C
-AT91C_US0_THR.width=32
-AT91C_US0_THR.byteEndian=little
-AT91C_US0_THR.type=enum
-AT91C_US0_THR.enum.0.name=*** Write only ***
-AT91C_US0_THR.enum.1.name=Error
-AT91C_US0_IF.name="AT91C_US0_IF"
-AT91C_US0_IF.description="IRDA_FILTER Register"
-AT91C_US0_IF.helpkey="IRDA_FILTER Register"
-AT91C_US0_IF.access=memorymapped
-AT91C_US0_IF.address=0xFFFC004C
-AT91C_US0_IF.width=32
-AT91C_US0_IF.byteEndian=little
-AT91C_US0_IER.name="AT91C_US0_IER"
-AT91C_US0_IER.description="Interrupt Enable Register"
-AT91C_US0_IER.helpkey="Interrupt Enable Register"
-AT91C_US0_IER.access=memorymapped
-AT91C_US0_IER.address=0xFFFC0008
-AT91C_US0_IER.width=32
-AT91C_US0_IER.byteEndian=little
-AT91C_US0_IER.type=enum
-AT91C_US0_IER.enum.0.name=*** Write only ***
-AT91C_US0_IER.enum.1.name=Error
-# ========== Register definition for TWI peripheral ==========
-AT91C_TWI_IER.name="AT91C_TWI_IER"
-AT91C_TWI_IER.description="Interrupt Enable Register"
-AT91C_TWI_IER.helpkey="Interrupt Enable Register"
-AT91C_TWI_IER.access=memorymapped
-AT91C_TWI_IER.address=0xFFFB8024
-AT91C_TWI_IER.width=32
-AT91C_TWI_IER.byteEndian=little
-AT91C_TWI_IER.type=enum
-AT91C_TWI_IER.enum.0.name=*** Write only ***
-AT91C_TWI_IER.enum.1.name=Error
-AT91C_TWI_CR.name="AT91C_TWI_CR"
-AT91C_TWI_CR.description="Control Register"
-AT91C_TWI_CR.helpkey="Control Register"
-AT91C_TWI_CR.access=memorymapped
-AT91C_TWI_CR.address=0xFFFB8000
-AT91C_TWI_CR.width=32
-AT91C_TWI_CR.byteEndian=little
-AT91C_TWI_CR.type=enum
-AT91C_TWI_CR.enum.0.name=*** Write only ***
-AT91C_TWI_CR.enum.1.name=Error
-AT91C_TWI_SR.name="AT91C_TWI_SR"
-AT91C_TWI_SR.description="Status Register"
-AT91C_TWI_SR.helpkey="Status Register"
-AT91C_TWI_SR.access=memorymapped
-AT91C_TWI_SR.address=0xFFFB8020
-AT91C_TWI_SR.width=32
-AT91C_TWI_SR.byteEndian=little
-AT91C_TWI_SR.permission.write=none
-AT91C_TWI_IMR.name="AT91C_TWI_IMR"
-AT91C_TWI_IMR.description="Interrupt Mask Register"
-AT91C_TWI_IMR.helpkey="Interrupt Mask Register"
-AT91C_TWI_IMR.access=memorymapped
-AT91C_TWI_IMR.address=0xFFFB802C
-AT91C_TWI_IMR.width=32
-AT91C_TWI_IMR.byteEndian=little
-AT91C_TWI_IMR.permission.write=none
-AT91C_TWI_THR.name="AT91C_TWI_THR"
-AT91C_TWI_THR.description="Transmit Holding Register"
-AT91C_TWI_THR.helpkey="Transmit Holding Register"
-AT91C_TWI_THR.access=memorymapped
-AT91C_TWI_THR.address=0xFFFB8034
-AT91C_TWI_THR.width=32
-AT91C_TWI_THR.byteEndian=little
-AT91C_TWI_THR.type=enum
-AT91C_TWI_THR.enum.0.name=*** Write only ***
-AT91C_TWI_THR.enum.1.name=Error
-AT91C_TWI_IDR.name="AT91C_TWI_IDR"
-AT91C_TWI_IDR.description="Interrupt Disable Register"
-AT91C_TWI_IDR.helpkey="Interrupt Disable Register"
-AT91C_TWI_IDR.access=memorymapped
-AT91C_TWI_IDR.address=0xFFFB8028
-AT91C_TWI_IDR.width=32
-AT91C_TWI_IDR.byteEndian=little
-AT91C_TWI_IDR.type=enum
-AT91C_TWI_IDR.enum.0.name=*** Write only ***
-AT91C_TWI_IDR.enum.1.name=Error
-AT91C_TWI_IADR.name="AT91C_TWI_IADR"
-AT91C_TWI_IADR.description="Internal Address Register"
-AT91C_TWI_IADR.helpkey="Internal Address Register"
-AT91C_TWI_IADR.access=memorymapped
-AT91C_TWI_IADR.address=0xFFFB800C
-AT91C_TWI_IADR.width=32
-AT91C_TWI_IADR.byteEndian=little
-AT91C_TWI_MMR.name="AT91C_TWI_MMR"
-AT91C_TWI_MMR.description="Master Mode Register"
-AT91C_TWI_MMR.helpkey="Master Mode Register"
-AT91C_TWI_MMR.access=memorymapped
-AT91C_TWI_MMR.address=0xFFFB8004
-AT91C_TWI_MMR.width=32
-AT91C_TWI_MMR.byteEndian=little
-AT91C_TWI_CWGR.name="AT91C_TWI_CWGR"
-AT91C_TWI_CWGR.description="Clock Waveform Generator Register"
-AT91C_TWI_CWGR.helpkey="Clock Waveform Generator Register"
-AT91C_TWI_CWGR.access=memorymapped
-AT91C_TWI_CWGR.address=0xFFFB8010
-AT91C_TWI_CWGR.width=32
-AT91C_TWI_CWGR.byteEndian=little
-AT91C_TWI_RHR.name="AT91C_TWI_RHR"
-AT91C_TWI_RHR.description="Receive Holding Register"
-AT91C_TWI_RHR.helpkey="Receive Holding Register"
-AT91C_TWI_RHR.access=memorymapped
-AT91C_TWI_RHR.address=0xFFFB8030
-AT91C_TWI_RHR.width=32
-AT91C_TWI_RHR.byteEndian=little
-AT91C_TWI_RHR.permission.write=none
-# ========== Register definition for TC0 peripheral ==========
-AT91C_TC0_SR.name="AT91C_TC0_SR"
-AT91C_TC0_SR.description="Status Register"
-AT91C_TC0_SR.helpkey="Status Register"
-AT91C_TC0_SR.access=memorymapped
-AT91C_TC0_SR.address=0xFFFA0020
-AT91C_TC0_SR.width=32
-AT91C_TC0_SR.byteEndian=little
-AT91C_TC0_SR.permission.write=none
-AT91C_TC0_RC.name="AT91C_TC0_RC"
-AT91C_TC0_RC.description="Register C"
-AT91C_TC0_RC.helpkey="Register C"
-AT91C_TC0_RC.access=memorymapped
-AT91C_TC0_RC.address=0xFFFA001C
-AT91C_TC0_RC.width=32
-AT91C_TC0_RC.byteEndian=little
-AT91C_TC0_RB.name="AT91C_TC0_RB"
-AT91C_TC0_RB.description="Register B"
-AT91C_TC0_RB.helpkey="Register B"
-AT91C_TC0_RB.access=memorymapped
-AT91C_TC0_RB.address=0xFFFA0018
-AT91C_TC0_RB.width=32
-AT91C_TC0_RB.byteEndian=little
-AT91C_TC0_CCR.name="AT91C_TC0_CCR"
-AT91C_TC0_CCR.description="Channel Control Register"
-AT91C_TC0_CCR.helpkey="Channel Control Register"
-AT91C_TC0_CCR.access=memorymapped
-AT91C_TC0_CCR.address=0xFFFA0000
-AT91C_TC0_CCR.width=32
-AT91C_TC0_CCR.byteEndian=little
-AT91C_TC0_CCR.type=enum
-AT91C_TC0_CCR.enum.0.name=*** Write only ***
-AT91C_TC0_CCR.enum.1.name=Error
-AT91C_TC0_CMR.name="AT91C_TC0_CMR"
-AT91C_TC0_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC0_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC0_CMR.access=memorymapped
-AT91C_TC0_CMR.address=0xFFFA0004
-AT91C_TC0_CMR.width=32
-AT91C_TC0_CMR.byteEndian=little
-AT91C_TC0_IER.name="AT91C_TC0_IER"
-AT91C_TC0_IER.description="Interrupt Enable Register"
-AT91C_TC0_IER.helpkey="Interrupt Enable Register"
-AT91C_TC0_IER.access=memorymapped
-AT91C_TC0_IER.address=0xFFFA0024
-AT91C_TC0_IER.width=32
-AT91C_TC0_IER.byteEndian=little
-AT91C_TC0_IER.type=enum
-AT91C_TC0_IER.enum.0.name=*** Write only ***
-AT91C_TC0_IER.enum.1.name=Error
-AT91C_TC0_RA.name="AT91C_TC0_RA"
-AT91C_TC0_RA.description="Register A"
-AT91C_TC0_RA.helpkey="Register A"
-AT91C_TC0_RA.access=memorymapped
-AT91C_TC0_RA.address=0xFFFA0014
-AT91C_TC0_RA.width=32
-AT91C_TC0_RA.byteEndian=little
-AT91C_TC0_IDR.name="AT91C_TC0_IDR"
-AT91C_TC0_IDR.description="Interrupt Disable Register"
-AT91C_TC0_IDR.helpkey="Interrupt Disable Register"
-AT91C_TC0_IDR.access=memorymapped
-AT91C_TC0_IDR.address=0xFFFA0028
-AT91C_TC0_IDR.width=32
-AT91C_TC0_IDR.byteEndian=little
-AT91C_TC0_IDR.type=enum
-AT91C_TC0_IDR.enum.0.name=*** Write only ***
-AT91C_TC0_IDR.enum.1.name=Error
-AT91C_TC0_CV.name="AT91C_TC0_CV"
-AT91C_TC0_CV.description="Counter Value"
-AT91C_TC0_CV.helpkey="Counter Value"
-AT91C_TC0_CV.access=memorymapped
-AT91C_TC0_CV.address=0xFFFA0010
-AT91C_TC0_CV.width=32
-AT91C_TC0_CV.byteEndian=little
-AT91C_TC0_IMR.name="AT91C_TC0_IMR"
-AT91C_TC0_IMR.description="Interrupt Mask Register"
-AT91C_TC0_IMR.helpkey="Interrupt Mask Register"
-AT91C_TC0_IMR.access=memorymapped
-AT91C_TC0_IMR.address=0xFFFA002C
-AT91C_TC0_IMR.width=32
-AT91C_TC0_IMR.byteEndian=little
-AT91C_TC0_IMR.permission.write=none
-# ========== Register definition for TC1 peripheral ==========
-AT91C_TC1_RB.name="AT91C_TC1_RB"
-AT91C_TC1_RB.description="Register B"
-AT91C_TC1_RB.helpkey="Register B"
-AT91C_TC1_RB.access=memorymapped
-AT91C_TC1_RB.address=0xFFFA0058
-AT91C_TC1_RB.width=32
-AT91C_TC1_RB.byteEndian=little
-AT91C_TC1_CCR.name="AT91C_TC1_CCR"
-AT91C_TC1_CCR.description="Channel Control Register"
-AT91C_TC1_CCR.helpkey="Channel Control Register"
-AT91C_TC1_CCR.access=memorymapped
-AT91C_TC1_CCR.address=0xFFFA0040
-AT91C_TC1_CCR.width=32
-AT91C_TC1_CCR.byteEndian=little
-AT91C_TC1_CCR.type=enum
-AT91C_TC1_CCR.enum.0.name=*** Write only ***
-AT91C_TC1_CCR.enum.1.name=Error
-AT91C_TC1_IER.name="AT91C_TC1_IER"
-AT91C_TC1_IER.description="Interrupt Enable Register"
-AT91C_TC1_IER.helpkey="Interrupt Enable Register"
-AT91C_TC1_IER.access=memorymapped
-AT91C_TC1_IER.address=0xFFFA0064
-AT91C_TC1_IER.width=32
-AT91C_TC1_IER.byteEndian=little
-AT91C_TC1_IER.type=enum
-AT91C_TC1_IER.enum.0.name=*** Write only ***
-AT91C_TC1_IER.enum.1.name=Error
-AT91C_TC1_IDR.name="AT91C_TC1_IDR"
-AT91C_TC1_IDR.description="Interrupt Disable Register"
-AT91C_TC1_IDR.helpkey="Interrupt Disable Register"
-AT91C_TC1_IDR.access=memorymapped
-AT91C_TC1_IDR.address=0xFFFA0068
-AT91C_TC1_IDR.width=32
-AT91C_TC1_IDR.byteEndian=little
-AT91C_TC1_IDR.type=enum
-AT91C_TC1_IDR.enum.0.name=*** Write only ***
-AT91C_TC1_IDR.enum.1.name=Error
-AT91C_TC1_SR.name="AT91C_TC1_SR"
-AT91C_TC1_SR.description="Status Register"
-AT91C_TC1_SR.helpkey="Status Register"
-AT91C_TC1_SR.access=memorymapped
-AT91C_TC1_SR.address=0xFFFA0060
-AT91C_TC1_SR.width=32
-AT91C_TC1_SR.byteEndian=little
-AT91C_TC1_SR.permission.write=none
-AT91C_TC1_CMR.name="AT91C_TC1_CMR"
-AT91C_TC1_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC1_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC1_CMR.access=memorymapped
-AT91C_TC1_CMR.address=0xFFFA0044
-AT91C_TC1_CMR.width=32
-AT91C_TC1_CMR.byteEndian=little
-AT91C_TC1_RA.name="AT91C_TC1_RA"
-AT91C_TC1_RA.description="Register A"
-AT91C_TC1_RA.helpkey="Register A"
-AT91C_TC1_RA.access=memorymapped
-AT91C_TC1_RA.address=0xFFFA0054
-AT91C_TC1_RA.width=32
-AT91C_TC1_RA.byteEndian=little
-AT91C_TC1_RC.name="AT91C_TC1_RC"
-AT91C_TC1_RC.description="Register C"
-AT91C_TC1_RC.helpkey="Register C"
-AT91C_TC1_RC.access=memorymapped
-AT91C_TC1_RC.address=0xFFFA005C
-AT91C_TC1_RC.width=32
-AT91C_TC1_RC.byteEndian=little
-AT91C_TC1_IMR.name="AT91C_TC1_IMR"
-AT91C_TC1_IMR.description="Interrupt Mask Register"
-AT91C_TC1_IMR.helpkey="Interrupt Mask Register"
-AT91C_TC1_IMR.access=memorymapped
-AT91C_TC1_IMR.address=0xFFFA006C
-AT91C_TC1_IMR.width=32
-AT91C_TC1_IMR.byteEndian=little
-AT91C_TC1_IMR.permission.write=none
-AT91C_TC1_CV.name="AT91C_TC1_CV"
-AT91C_TC1_CV.description="Counter Value"
-AT91C_TC1_CV.helpkey="Counter Value"
-AT91C_TC1_CV.access=memorymapped
-AT91C_TC1_CV.address=0xFFFA0050
-AT91C_TC1_CV.width=32
-AT91C_TC1_CV.byteEndian=little
-# ========== Register definition for TC2 peripheral ==========
-AT91C_TC2_CMR.name="AT91C_TC2_CMR"
-AT91C_TC2_CMR.description="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC2_CMR.helpkey="Channel Mode Register (Capture Mode / Waveform Mode)"
-AT91C_TC2_CMR.access=memorymapped
-AT91C_TC2_CMR.address=0xFFFA0084
-AT91C_TC2_CMR.width=32
-AT91C_TC2_CMR.byteEndian=little
-AT91C_TC2_CCR.name="AT91C_TC2_CCR"
-AT91C_TC2_CCR.description="Channel Control Register"
-AT91C_TC2_CCR.helpkey="Channel Control Register"
-AT91C_TC2_CCR.access=memorymapped
-AT91C_TC2_CCR.address=0xFFFA0080
-AT91C_TC2_CCR.width=32
-AT91C_TC2_CCR.byteEndian=little
-AT91C_TC2_CCR.type=enum
-AT91C_TC2_CCR.enum.0.name=*** Write only ***
-AT91C_TC2_CCR.enum.1.name=Error
-AT91C_TC2_CV.name="AT91C_TC2_CV"
-AT91C_TC2_CV.description="Counter Value"
-AT91C_TC2_CV.helpkey="Counter Value"
-AT91C_TC2_CV.access=memorymapped
-AT91C_TC2_CV.address=0xFFFA0090
-AT91C_TC2_CV.width=32
-AT91C_TC2_CV.byteEndian=little
-AT91C_TC2_RA.name="AT91C_TC2_RA"
-AT91C_TC2_RA.description="Register A"
-AT91C_TC2_RA.helpkey="Register A"
-AT91C_TC2_RA.access=memorymapped
-AT91C_TC2_RA.address=0xFFFA0094
-AT91C_TC2_RA.width=32
-AT91C_TC2_RA.byteEndian=little
-AT91C_TC2_RB.name="AT91C_TC2_RB"
-AT91C_TC2_RB.description="Register B"
-AT91C_TC2_RB.helpkey="Register B"
-AT91C_TC2_RB.access=memorymapped
-AT91C_TC2_RB.address=0xFFFA0098
-AT91C_TC2_RB.width=32
-AT91C_TC2_RB.byteEndian=little
-AT91C_TC2_IDR.name="AT91C_TC2_IDR"
-AT91C_TC2_IDR.description="Interrupt Disable Register"
-AT91C_TC2_IDR.helpkey="Interrupt Disable Register"
-AT91C_TC2_IDR.access=memorymapped
-AT91C_TC2_IDR.address=0xFFFA00A8
-AT91C_TC2_IDR.width=32
-AT91C_TC2_IDR.byteEndian=little
-AT91C_TC2_IDR.type=enum
-AT91C_TC2_IDR.enum.0.name=*** Write only ***
-AT91C_TC2_IDR.enum.1.name=Error
-AT91C_TC2_IMR.name="AT91C_TC2_IMR"
-AT91C_TC2_IMR.description="Interrupt Mask Register"
-AT91C_TC2_IMR.helpkey="Interrupt Mask Register"
-AT91C_TC2_IMR.access=memorymapped
-AT91C_TC2_IMR.address=0xFFFA00AC
-AT91C_TC2_IMR.width=32
-AT91C_TC2_IMR.byteEndian=little
-AT91C_TC2_IMR.permission.write=none
-AT91C_TC2_RC.name="AT91C_TC2_RC"
-AT91C_TC2_RC.description="Register C"
-AT91C_TC2_RC.helpkey="Register C"
-AT91C_TC2_RC.access=memorymapped
-AT91C_TC2_RC.address=0xFFFA009C
-AT91C_TC2_RC.width=32
-AT91C_TC2_RC.byteEndian=little
-AT91C_TC2_IER.name="AT91C_TC2_IER"
-AT91C_TC2_IER.description="Interrupt Enable Register"
-AT91C_TC2_IER.helpkey="Interrupt Enable Register"
-AT91C_TC2_IER.access=memorymapped
-AT91C_TC2_IER.address=0xFFFA00A4
-AT91C_TC2_IER.width=32
-AT91C_TC2_IER.byteEndian=little
-AT91C_TC2_IER.type=enum
-AT91C_TC2_IER.enum.0.name=*** Write only ***
-AT91C_TC2_IER.enum.1.name=Error
-AT91C_TC2_SR.name="AT91C_TC2_SR"
-AT91C_TC2_SR.description="Status Register"
-AT91C_TC2_SR.helpkey="Status Register"
-AT91C_TC2_SR.access=memorymapped
-AT91C_TC2_SR.address=0xFFFA00A0
-AT91C_TC2_SR.width=32
-AT91C_TC2_SR.byteEndian=little
-AT91C_TC2_SR.permission.write=none
-# ========== Register definition for TCB peripheral ==========
-AT91C_TCB_BMR.name="AT91C_TCB_BMR"
-AT91C_TCB_BMR.description="TC Block Mode Register"
-AT91C_TCB_BMR.helpkey="TC Block Mode Register"
-AT91C_TCB_BMR.access=memorymapped
-AT91C_TCB_BMR.address=0xFFFA00C4
-AT91C_TCB_BMR.width=32
-AT91C_TCB_BMR.byteEndian=little
-AT91C_TCB_BCR.name="AT91C_TCB_BCR"
-AT91C_TCB_BCR.description="TC Block Control Register"
-AT91C_TCB_BCR.helpkey="TC Block Control Register"
-AT91C_TCB_BCR.access=memorymapped
-AT91C_TCB_BCR.address=0xFFFA00C0
-AT91C_TCB_BCR.width=32
-AT91C_TCB_BCR.byteEndian=little
-AT91C_TCB_BCR.type=enum
-AT91C_TCB_BCR.enum.0.name=*** Write only ***
-AT91C_TCB_BCR.enum.1.name=Error
-# ========== Register definition for PWMC_CH3 peripheral ==========
-AT91C_PWMC_CH3_CUPDR.name="AT91C_PWMC_CH3_CUPDR"
-AT91C_PWMC_CH3_CUPDR.description="Channel Update Register"
-AT91C_PWMC_CH3_CUPDR.helpkey="Channel Update Register"
-AT91C_PWMC_CH3_CUPDR.access=memorymapped
-AT91C_PWMC_CH3_CUPDR.address=0xFFFCC270
-AT91C_PWMC_CH3_CUPDR.width=32
-AT91C_PWMC_CH3_CUPDR.byteEndian=little
-AT91C_PWMC_CH3_CUPDR.type=enum
-AT91C_PWMC_CH3_CUPDR.enum.0.name=*** Write only ***
-AT91C_PWMC_CH3_CUPDR.enum.1.name=Error
-AT91C_PWMC_CH3_Reserved.name="AT91C_PWMC_CH3_Reserved"
-AT91C_PWMC_CH3_Reserved.description="Reserved"
-AT91C_PWMC_CH3_Reserved.helpkey="Reserved"
-AT91C_PWMC_CH3_Reserved.access=memorymapped
-AT91C_PWMC_CH3_Reserved.address=0xFFFCC274
-AT91C_PWMC_CH3_Reserved.width=32
-AT91C_PWMC_CH3_Reserved.byteEndian=little
-AT91C_PWMC_CH3_Reserved.type=enum
-AT91C_PWMC_CH3_Reserved.enum.0.name=*** Write only ***
-AT91C_PWMC_CH3_Reserved.enum.1.name=Error
-AT91C_PWMC_CH3_CPRDR.name="AT91C_PWMC_CH3_CPRDR"
-AT91C_PWMC_CH3_CPRDR.description="Channel Period Register"
-AT91C_PWMC_CH3_CPRDR.helpkey="Channel Period Register"
-AT91C_PWMC_CH3_CPRDR.access=memorymapped
-AT91C_PWMC_CH3_CPRDR.address=0xFFFCC268
-AT91C_PWMC_CH3_CPRDR.width=32
-AT91C_PWMC_CH3_CPRDR.byteEndian=little
-AT91C_PWMC_CH3_CDTYR.name="AT91C_PWMC_CH3_CDTYR"
-AT91C_PWMC_CH3_CDTYR.description="Channel Duty Cycle Register"
-AT91C_PWMC_CH3_CDTYR.helpkey="Channel Duty Cycle Register"
-AT91C_PWMC_CH3_CDTYR.access=memorymapped
-AT91C_PWMC_CH3_CDTYR.address=0xFFFCC264
-AT91C_PWMC_CH3_CDTYR.width=32
-AT91C_PWMC_CH3_CDTYR.byteEndian=little
-AT91C_PWMC_CH3_CCNTR.name="AT91C_PWMC_CH3_CCNTR"
-AT91C_PWMC_CH3_CCNTR.description="Channel Counter Register"
-AT91C_PWMC_CH3_CCNTR.helpkey="Channel Counter Register"
-AT91C_PWMC_CH3_CCNTR.access=memorymapped
-AT91C_PWMC_CH3_CCNTR.address=0xFFFCC26C
-AT91C_PWMC_CH3_CCNTR.width=32
-AT91C_PWMC_CH3_CCNTR.byteEndian=little
-AT91C_PWMC_CH3_CCNTR.permission.write=none
-AT91C_PWMC_CH3_CMR.name="AT91C_PWMC_CH3_CMR"
-AT91C_PWMC_CH3_CMR.description="Channel Mode Register"
-AT91C_PWMC_CH3_CMR.helpkey="Channel Mode Register"
-AT91C_PWMC_CH3_CMR.access=memorymapped
-AT91C_PWMC_CH3_CMR.address=0xFFFCC260
-AT91C_PWMC_CH3_CMR.width=32
-AT91C_PWMC_CH3_CMR.byteEndian=little
-# ========== Register definition for PWMC_CH2 peripheral ==========
-AT91C_PWMC_CH2_Reserved.name="AT91C_PWMC_CH2_Reserved"
-AT91C_PWMC_CH2_Reserved.description="Reserved"
-AT91C_PWMC_CH2_Reserved.helpkey="Reserved"
-AT91C_PWMC_CH2_Reserved.access=memorymapped
-AT91C_PWMC_CH2_Reserved.address=0xFFFCC254
-AT91C_PWMC_CH2_Reserved.width=32
-AT91C_PWMC_CH2_Reserved.byteEndian=little
-AT91C_PWMC_CH2_Reserved.type=enum
-AT91C_PWMC_CH2_Reserved.enum.0.name=*** Write only ***
-AT91C_PWMC_CH2_Reserved.enum.1.name=Error
-AT91C_PWMC_CH2_CMR.name="AT91C_PWMC_CH2_CMR"
-AT91C_PWMC_CH2_CMR.description="Channel Mode Register"
-AT91C_PWMC_CH2_CMR.helpkey="Channel Mode Register"
-AT91C_PWMC_CH2_CMR.access=memorymapped
-AT91C_PWMC_CH2_CMR.address=0xFFFCC240
-AT91C_PWMC_CH2_CMR.width=32
-AT91C_PWMC_CH2_CMR.byteEndian=little
-AT91C_PWMC_CH2_CCNTR.name="AT91C_PWMC_CH2_CCNTR"
-AT91C_PWMC_CH2_CCNTR.description="Channel Counter Register"
-AT91C_PWMC_CH2_CCNTR.helpkey="Channel Counter Register"
-AT91C_PWMC_CH2_CCNTR.access=memorymapped
-AT91C_PWMC_CH2_CCNTR.address=0xFFFCC24C
-AT91C_PWMC_CH2_CCNTR.width=32
-AT91C_PWMC_CH2_CCNTR.byteEndian=little
-AT91C_PWMC_CH2_CCNTR.permission.write=none
-AT91C_PWMC_CH2_CPRDR.name="AT91C_PWMC_CH2_CPRDR"
-AT91C_PWMC_CH2_CPRDR.description="Channel Period Register"
-AT91C_PWMC_CH2_CPRDR.helpkey="Channel Period Register"
-AT91C_PWMC_CH2_CPRDR.access=memorymapped
-AT91C_PWMC_CH2_CPRDR.address=0xFFFCC248
-AT91C_PWMC_CH2_CPRDR.width=32
-AT91C_PWMC_CH2_CPRDR.byteEndian=little
-AT91C_PWMC_CH2_CUPDR.name="AT91C_PWMC_CH2_CUPDR"
-AT91C_PWMC_CH2_CUPDR.description="Channel Update Register"
-AT91C_PWMC_CH2_CUPDR.helpkey="Channel Update Register"
-AT91C_PWMC_CH2_CUPDR.access=memorymapped
-AT91C_PWMC_CH2_CUPDR.address=0xFFFCC250
-AT91C_PWMC_CH2_CUPDR.width=32
-AT91C_PWMC_CH2_CUPDR.byteEndian=little
-AT91C_PWMC_CH2_CUPDR.type=enum
-AT91C_PWMC_CH2_CUPDR.enum.0.name=*** Write only ***
-AT91C_PWMC_CH2_CUPDR.enum.1.name=Error
-AT91C_PWMC_CH2_CDTYR.name="AT91C_PWMC_CH2_CDTYR"
-AT91C_PWMC_CH2_CDTYR.description="Channel Duty Cycle Register"
-AT91C_PWMC_CH2_CDTYR.helpkey="Channel Duty Cycle Register"
-AT91C_PWMC_CH2_CDTYR.access=memorymapped
-AT91C_PWMC_CH2_CDTYR.address=0xFFFCC244
-AT91C_PWMC_CH2_CDTYR.width=32
-AT91C_PWMC_CH2_CDTYR.byteEndian=little
-# ========== Register definition for PWMC_CH1 peripheral ==========
-AT91C_PWMC_CH1_Reserved.name="AT91C_PWMC_CH1_Reserved"
-AT91C_PWMC_CH1_Reserved.description="Reserved"
-AT91C_PWMC_CH1_Reserved.helpkey="Reserved"
-AT91C_PWMC_CH1_Reserved.access=memorymapped
-AT91C_PWMC_CH1_Reserved.address=0xFFFCC234
-AT91C_PWMC_CH1_Reserved.width=32
-AT91C_PWMC_CH1_Reserved.byteEndian=little
-AT91C_PWMC_CH1_Reserved.type=enum
-AT91C_PWMC_CH1_Reserved.enum.0.name=*** Write only ***
-AT91C_PWMC_CH1_Reserved.enum.1.name=Error
-AT91C_PWMC_CH1_CUPDR.name="AT91C_PWMC_CH1_CUPDR"
-AT91C_PWMC_CH1_CUPDR.description="Channel Update Register"
-AT91C_PWMC_CH1_CUPDR.helpkey="Channel Update Register"
-AT91C_PWMC_CH1_CUPDR.access=memorymapped
-AT91C_PWMC_CH1_CUPDR.address=0xFFFCC230
-AT91C_PWMC_CH1_CUPDR.width=32
-AT91C_PWMC_CH1_CUPDR.byteEndian=little
-AT91C_PWMC_CH1_CUPDR.type=enum
-AT91C_PWMC_CH1_CUPDR.enum.0.name=*** Write only ***
-AT91C_PWMC_CH1_CUPDR.enum.1.name=Error
-AT91C_PWMC_CH1_CPRDR.name="AT91C_PWMC_CH1_CPRDR"
-AT91C_PWMC_CH1_CPRDR.description="Channel Period Register"
-AT91C_PWMC_CH1_CPRDR.helpkey="Channel Period Register"
-AT91C_PWMC_CH1_CPRDR.access=memorymapped
-AT91C_PWMC_CH1_CPRDR.address=0xFFFCC228
-AT91C_PWMC_CH1_CPRDR.width=32
-AT91C_PWMC_CH1_CPRDR.byteEndian=little
-AT91C_PWMC_CH1_CCNTR.name="AT91C_PWMC_CH1_CCNTR"
-AT91C_PWMC_CH1_CCNTR.description="Channel Counter Register"
-AT91C_PWMC_CH1_CCNTR.helpkey="Channel Counter Register"
-AT91C_PWMC_CH1_CCNTR.access=memorymapped
-AT91C_PWMC_CH1_CCNTR.address=0xFFFCC22C
-AT91C_PWMC_CH1_CCNTR.width=32
-AT91C_PWMC_CH1_CCNTR.byteEndian=little
-AT91C_PWMC_CH1_CCNTR.permission.write=none
-AT91C_PWMC_CH1_CDTYR.name="AT91C_PWMC_CH1_CDTYR"
-AT91C_PWMC_CH1_CDTYR.description="Channel Duty Cycle Register"
-AT91C_PWMC_CH1_CDTYR.helpkey="Channel Duty Cycle Register"
-AT91C_PWMC_CH1_CDTYR.access=memorymapped
-AT91C_PWMC_CH1_CDTYR.address=0xFFFCC224
-AT91C_PWMC_CH1_CDTYR.width=32
-AT91C_PWMC_CH1_CDTYR.byteEndian=little
-AT91C_PWMC_CH1_CMR.name="AT91C_PWMC_CH1_CMR"
-AT91C_PWMC_CH1_CMR.description="Channel Mode Register"
-AT91C_PWMC_CH1_CMR.helpkey="Channel Mode Register"
-AT91C_PWMC_CH1_CMR.access=memorymapped
-AT91C_PWMC_CH1_CMR.address=0xFFFCC220
-AT91C_PWMC_CH1_CMR.width=32
-AT91C_PWMC_CH1_CMR.byteEndian=little
-# ========== Register definition for PWMC_CH0 peripheral ==========
-AT91C_PWMC_CH0_Reserved.name="AT91C_PWMC_CH0_Reserved"
-AT91C_PWMC_CH0_Reserved.description="Reserved"
-AT91C_PWMC_CH0_Reserved.helpkey="Reserved"
-AT91C_PWMC_CH0_Reserved.access=memorymapped
-AT91C_PWMC_CH0_Reserved.address=0xFFFCC214
-AT91C_PWMC_CH0_Reserved.width=32
-AT91C_PWMC_CH0_Reserved.byteEndian=little
-AT91C_PWMC_CH0_Reserved.type=enum
-AT91C_PWMC_CH0_Reserved.enum.0.name=*** Write only ***
-AT91C_PWMC_CH0_Reserved.enum.1.name=Error
-AT91C_PWMC_CH0_CPRDR.name="AT91C_PWMC_CH0_CPRDR"
-AT91C_PWMC_CH0_CPRDR.description="Channel Period Register"
-AT91C_PWMC_CH0_CPRDR.helpkey="Channel Period Register"
-AT91C_PWMC_CH0_CPRDR.access=memorymapped
-AT91C_PWMC_CH0_CPRDR.address=0xFFFCC208
-AT91C_PWMC_CH0_CPRDR.width=32
-AT91C_PWMC_CH0_CPRDR.byteEndian=little
-AT91C_PWMC_CH0_CDTYR.name="AT91C_PWMC_CH0_CDTYR"
-AT91C_PWMC_CH0_CDTYR.description="Channel Duty Cycle Register"
-AT91C_PWMC_CH0_CDTYR.helpkey="Channel Duty Cycle Register"
-AT91C_PWMC_CH0_CDTYR.access=memorymapped
-AT91C_PWMC_CH0_CDTYR.address=0xFFFCC204
-AT91C_PWMC_CH0_CDTYR.width=32
-AT91C_PWMC_CH0_CDTYR.byteEndian=little
-AT91C_PWMC_CH0_CMR.name="AT91C_PWMC_CH0_CMR"
-AT91C_PWMC_CH0_CMR.description="Channel Mode Register"
-AT91C_PWMC_CH0_CMR.helpkey="Channel Mode Register"
-AT91C_PWMC_CH0_CMR.access=memorymapped
-AT91C_PWMC_CH0_CMR.address=0xFFFCC200
-AT91C_PWMC_CH0_CMR.width=32
-AT91C_PWMC_CH0_CMR.byteEndian=little
-AT91C_PWMC_CH0_CUPDR.name="AT91C_PWMC_CH0_CUPDR"
-AT91C_PWMC_CH0_CUPDR.description="Channel Update Register"
-AT91C_PWMC_CH0_CUPDR.helpkey="Channel Update Register"
-AT91C_PWMC_CH0_CUPDR.access=memorymapped
-AT91C_PWMC_CH0_CUPDR.address=0xFFFCC210
-AT91C_PWMC_CH0_CUPDR.width=32
-AT91C_PWMC_CH0_CUPDR.byteEndian=little
-AT91C_PWMC_CH0_CUPDR.type=enum
-AT91C_PWMC_CH0_CUPDR.enum.0.name=*** Write only ***
-AT91C_PWMC_CH0_CUPDR.enum.1.name=Error
-AT91C_PWMC_CH0_CCNTR.name="AT91C_PWMC_CH0_CCNTR"
-AT91C_PWMC_CH0_CCNTR.description="Channel Counter Register"
-AT91C_PWMC_CH0_CCNTR.helpkey="Channel Counter Register"
-AT91C_PWMC_CH0_CCNTR.access=memorymapped
-AT91C_PWMC_CH0_CCNTR.address=0xFFFCC20C
-AT91C_PWMC_CH0_CCNTR.width=32
-AT91C_PWMC_CH0_CCNTR.byteEndian=little
-AT91C_PWMC_CH0_CCNTR.permission.write=none
-# ========== Register definition for PWMC peripheral ==========
-AT91C_PWMC_IDR.name="AT91C_PWMC_IDR"
-AT91C_PWMC_IDR.description="PWMC Interrupt Disable Register"
-AT91C_PWMC_IDR.helpkey="PWMC Interrupt Disable Register"
-AT91C_PWMC_IDR.access=memorymapped
-AT91C_PWMC_IDR.address=0xFFFCC014
-AT91C_PWMC_IDR.width=32
-AT91C_PWMC_IDR.byteEndian=little
-AT91C_PWMC_IDR.type=enum
-AT91C_PWMC_IDR.enum.0.name=*** Write only ***
-AT91C_PWMC_IDR.enum.1.name=Error
-AT91C_PWMC_DIS.name="AT91C_PWMC_DIS"
-AT91C_PWMC_DIS.description="PWMC Disable Register"
-AT91C_PWMC_DIS.helpkey="PWMC Disable Register"
-AT91C_PWMC_DIS.access=memorymapped
-AT91C_PWMC_DIS.address=0xFFFCC008
-AT91C_PWMC_DIS.width=32
-AT91C_PWMC_DIS.byteEndian=little
-AT91C_PWMC_DIS.type=enum
-AT91C_PWMC_DIS.enum.0.name=*** Write only ***
-AT91C_PWMC_DIS.enum.1.name=Error
-AT91C_PWMC_IER.name="AT91C_PWMC_IER"
-AT91C_PWMC_IER.description="PWMC Interrupt Enable Register"
-AT91C_PWMC_IER.helpkey="PWMC Interrupt Enable Register"
-AT91C_PWMC_IER.access=memorymapped
-AT91C_PWMC_IER.address=0xFFFCC010
-AT91C_PWMC_IER.width=32
-AT91C_PWMC_IER.byteEndian=little
-AT91C_PWMC_IER.type=enum
-AT91C_PWMC_IER.enum.0.name=*** Write only ***
-AT91C_PWMC_IER.enum.1.name=Error
-AT91C_PWMC_VR.name="AT91C_PWMC_VR"
-AT91C_PWMC_VR.description="PWMC Version Register"
-AT91C_PWMC_VR.helpkey="PWMC Version Register"
-AT91C_PWMC_VR.access=memorymapped
-AT91C_PWMC_VR.address=0xFFFCC0FC
-AT91C_PWMC_VR.width=32
-AT91C_PWMC_VR.byteEndian=little
-AT91C_PWMC_VR.permission.write=none
-AT91C_PWMC_ISR.name="AT91C_PWMC_ISR"
-AT91C_PWMC_ISR.description="PWMC Interrupt Status Register"
-AT91C_PWMC_ISR.helpkey="PWMC Interrupt Status Register"
-AT91C_PWMC_ISR.access=memorymapped
-AT91C_PWMC_ISR.address=0xFFFCC01C
-AT91C_PWMC_ISR.width=32
-AT91C_PWMC_ISR.byteEndian=little
-AT91C_PWMC_ISR.permission.write=none
-AT91C_PWMC_SR.name="AT91C_PWMC_SR"
-AT91C_PWMC_SR.description="PWMC Status Register"
-AT91C_PWMC_SR.helpkey="PWMC Status Register"
-AT91C_PWMC_SR.access=memorymapped
-AT91C_PWMC_SR.address=0xFFFCC00C
-AT91C_PWMC_SR.width=32
-AT91C_PWMC_SR.byteEndian=little
-AT91C_PWMC_SR.permission.write=none
-AT91C_PWMC_IMR.name="AT91C_PWMC_IMR"
-AT91C_PWMC_IMR.description="PWMC Interrupt Mask Register"
-AT91C_PWMC_IMR.helpkey="PWMC Interrupt Mask Register"
-AT91C_PWMC_IMR.access=memorymapped
-AT91C_PWMC_IMR.address=0xFFFCC018
-AT91C_PWMC_IMR.width=32
-AT91C_PWMC_IMR.byteEndian=little
-AT91C_PWMC_IMR.permission.write=none
-AT91C_PWMC_MR.name="AT91C_PWMC_MR"
-AT91C_PWMC_MR.description="PWMC Mode Register"
-AT91C_PWMC_MR.helpkey="PWMC Mode Register"
-AT91C_PWMC_MR.access=memorymapped
-AT91C_PWMC_MR.address=0xFFFCC000
-AT91C_PWMC_MR.width=32
-AT91C_PWMC_MR.byteEndian=little
-AT91C_PWMC_ENA.name="AT91C_PWMC_ENA"
-AT91C_PWMC_ENA.description="PWMC Enable Register"
-AT91C_PWMC_ENA.helpkey="PWMC Enable Register"
-AT91C_PWMC_ENA.access=memorymapped
-AT91C_PWMC_ENA.address=0xFFFCC004
-AT91C_PWMC_ENA.width=32
-AT91C_PWMC_ENA.byteEndian=little
-AT91C_PWMC_ENA.type=enum
-AT91C_PWMC_ENA.enum.0.name=*** Write only ***
-AT91C_PWMC_ENA.enum.1.name=Error
-# ========== Register definition for UDP peripheral ==========
-AT91C_UDP_IMR.name="AT91C_UDP_IMR"
-AT91C_UDP_IMR.description="Interrupt Mask Register"
-AT91C_UDP_IMR.helpkey="Interrupt Mask Register"
-AT91C_UDP_IMR.access=memorymapped
-AT91C_UDP_IMR.address=0xFFFB0018
-AT91C_UDP_IMR.width=32
-AT91C_UDP_IMR.byteEndian=little
-AT91C_UDP_IMR.permission.write=none
-AT91C_UDP_FADDR.name="AT91C_UDP_FADDR"
-AT91C_UDP_FADDR.description="Function Address Register"
-AT91C_UDP_FADDR.helpkey="Function Address Register"
-AT91C_UDP_FADDR.access=memorymapped
-AT91C_UDP_FADDR.address=0xFFFB0008
-AT91C_UDP_FADDR.width=32
-AT91C_UDP_FADDR.byteEndian=little
-AT91C_UDP_NUM.name="AT91C_UDP_NUM"
-AT91C_UDP_NUM.description="Frame Number Register"
-AT91C_UDP_NUM.helpkey="Frame Number Register"
-AT91C_UDP_NUM.access=memorymapped
-AT91C_UDP_NUM.address=0xFFFB0000
-AT91C_UDP_NUM.width=32
-AT91C_UDP_NUM.byteEndian=little
-AT91C_UDP_NUM.permission.write=none
-AT91C_UDP_FDR.name="AT91C_UDP_FDR"
-AT91C_UDP_FDR.description="Endpoint FIFO Data Register"
-AT91C_UDP_FDR.helpkey="Endpoint FIFO Data Register"
-AT91C_UDP_FDR.access=memorymapped
-AT91C_UDP_FDR.address=0xFFFB0050
-AT91C_UDP_FDR.width=32
-AT91C_UDP_FDR.byteEndian=little
-AT91C_UDP_ISR.name="AT91C_UDP_ISR"
-AT91C_UDP_ISR.description="Interrupt Status Register"
-AT91C_UDP_ISR.helpkey="Interrupt Status Register"
-AT91C_UDP_ISR.access=memorymapped
-AT91C_UDP_ISR.address=0xFFFB001C
-AT91C_UDP_ISR.width=32
-AT91C_UDP_ISR.byteEndian=little
-AT91C_UDP_ISR.permission.write=none
-AT91C_UDP_CSR.name="AT91C_UDP_CSR"
-AT91C_UDP_CSR.description="Endpoint Control and Status Register"
-AT91C_UDP_CSR.helpkey="Endpoint Control and Status Register"
-AT91C_UDP_CSR.access=memorymapped
-AT91C_UDP_CSR.address=0xFFFB0030
-AT91C_UDP_CSR.width=32
-AT91C_UDP_CSR.byteEndian=little
-AT91C_UDP_IDR.name="AT91C_UDP_IDR"
-AT91C_UDP_IDR.description="Interrupt Disable Register"
-AT91C_UDP_IDR.helpkey="Interrupt Disable Register"
-AT91C_UDP_IDR.access=memorymapped
-AT91C_UDP_IDR.address=0xFFFB0014
-AT91C_UDP_IDR.width=32
-AT91C_UDP_IDR.byteEndian=little
-AT91C_UDP_IDR.type=enum
-AT91C_UDP_IDR.enum.0.name=*** Write only ***
-AT91C_UDP_IDR.enum.1.name=Error
-AT91C_UDP_ICR.name="AT91C_UDP_ICR"
-AT91C_UDP_ICR.description="Interrupt Clear Register"
-AT91C_UDP_ICR.helpkey="Interrupt Clear Register"
-AT91C_UDP_ICR.access=memorymapped
-AT91C_UDP_ICR.address=0xFFFB0020
-AT91C_UDP_ICR.width=32
-AT91C_UDP_ICR.byteEndian=little
-AT91C_UDP_ICR.permission.write=none
-AT91C_UDP_RSTEP.name="AT91C_UDP_RSTEP"
-AT91C_UDP_RSTEP.description="Reset Endpoint Register"
-AT91C_UDP_RSTEP.helpkey="Reset Endpoint Register"
-AT91C_UDP_RSTEP.access=memorymapped
-AT91C_UDP_RSTEP.address=0xFFFB0028
-AT91C_UDP_RSTEP.width=32
-AT91C_UDP_RSTEP.byteEndian=little
-AT91C_UDP_RSTEP.permission.write=none
-AT91C_UDP_TXVC.name="AT91C_UDP_TXVC"
-AT91C_UDP_TXVC.description="Transceiver Control Register"
-AT91C_UDP_TXVC.helpkey="Transceiver Control Register"
-AT91C_UDP_TXVC.access=memorymapped
-AT91C_UDP_TXVC.address=0xFFFB0074
-AT91C_UDP_TXVC.width=32
-AT91C_UDP_TXVC.byteEndian=little
-AT91C_UDP_GLBSTATE.name="AT91C_UDP_GLBSTATE"
-AT91C_UDP_GLBSTATE.description="Global State Register"
-AT91C_UDP_GLBSTATE.helpkey="Global State Register"
-AT91C_UDP_GLBSTATE.access=memorymapped
-AT91C_UDP_GLBSTATE.address=0xFFFB0004
-AT91C_UDP_GLBSTATE.width=32
-AT91C_UDP_GLBSTATE.byteEndian=little
-AT91C_UDP_IER.name="AT91C_UDP_IER"
-AT91C_UDP_IER.description="Interrupt Enable Register"
-AT91C_UDP_IER.helpkey="Interrupt Enable Register"
-AT91C_UDP_IER.access=memorymapped
-AT91C_UDP_IER.address=0xFFFB0010
-AT91C_UDP_IER.width=32
-AT91C_UDP_IER.byteEndian=little
-AT91C_UDP_IER.type=enum
-AT91C_UDP_IER.enum.0.name=*** Write only ***
-AT91C_UDP_IER.enum.1.name=Error
-# ========== Group definition for SYS peripheral ==========
-group.SYS.description="ATMEL SYS Registers"
-group.SYS.helpkey="ATMEL SYS Registers"
-# ========== Group definition for AIC peripheral ==========
-group.AIC.description="ATMEL AIC Registers"
-group.AIC.helpkey="ATMEL AIC Registers"
-group.AIC.register.0=AT91C_AIC_IVR
-group.AIC.register.1=AT91C_AIC_SMR
-group.AIC.register.2=AT91C_AIC_FVR
-group.AIC.register.3=AT91C_AIC_DCR
-group.AIC.register.4=AT91C_AIC_EOICR
-group.AIC.register.5=AT91C_AIC_SVR
-group.AIC.register.6=AT91C_AIC_FFSR
-group.AIC.register.7=AT91C_AIC_ICCR
-group.AIC.register.8=AT91C_AIC_ISR
-group.AIC.register.9=AT91C_AIC_IMR
-group.AIC.register.10=AT91C_AIC_IPR
-group.AIC.register.11=AT91C_AIC_FFER
-group.AIC.register.12=AT91C_AIC_IECR
-group.AIC.register.13=AT91C_AIC_ISCR
-group.AIC.register.14=AT91C_AIC_FFDR
-group.AIC.register.15=AT91C_AIC_CISR
-group.AIC.register.16=AT91C_AIC_IDCR
-group.AIC.register.17=AT91C_AIC_SPU
-# ========== Group definition for PDC_DBGU peripheral ==========
-group.PDC_DBGU.description="ATMEL PDC_DBGU Registers"
-group.PDC_DBGU.helpkey="ATMEL PDC_DBGU Registers"
-group.PDC_DBGU.register.0=AT91C_DBGU_TCR
-group.PDC_DBGU.register.1=AT91C_DBGU_RNPR
-group.PDC_DBGU.register.2=AT91C_DBGU_TNPR
-group.PDC_DBGU.register.3=AT91C_DBGU_TPR
-group.PDC_DBGU.register.4=AT91C_DBGU_RPR
-group.PDC_DBGU.register.5=AT91C_DBGU_RCR
-group.PDC_DBGU.register.6=AT91C_DBGU_RNCR
-group.PDC_DBGU.register.7=AT91C_DBGU_PTCR
-group.PDC_DBGU.register.8=AT91C_DBGU_PTSR
-group.PDC_DBGU.register.9=AT91C_DBGU_TNCR
-# ========== Group definition for DBGU peripheral ==========
-group.DBGU.description="ATMEL DBGU Registers"
-group.DBGU.helpkey="ATMEL DBGU Registers"
-group.DBGU.register.0=AT91C_DBGU_EXID
-group.DBGU.register.1=AT91C_DBGU_BRGR
-group.DBGU.register.2=AT91C_DBGU_IDR
-group.DBGU.register.3=AT91C_DBGU_CSR
-group.DBGU.register.4=AT91C_DBGU_CIDR
-group.DBGU.register.5=AT91C_DBGU_MR
-group.DBGU.register.6=AT91C_DBGU_IMR
-group.DBGU.register.7=AT91C_DBGU_CR
-group.DBGU.register.8=AT91C_DBGU_FNTR
-group.DBGU.register.9=AT91C_DBGU_THR
-group.DBGU.register.10=AT91C_DBGU_RHR
-group.DBGU.register.11=AT91C_DBGU_IER
-# ========== Group definition for PIOA peripheral ==========
-group.PIOA.description="ATMEL PIOA Registers"
-group.PIOA.helpkey="ATMEL PIOA Registers"
-group.PIOA.register.0=AT91C_PIOA_ODR
-group.PIOA.register.1=AT91C_PIOA_SODR
-group.PIOA.register.2=AT91C_PIOA_ISR
-group.PIOA.register.3=AT91C_PIOA_ABSR
-group.PIOA.register.4=AT91C_PIOA_IER
-group.PIOA.register.5=AT91C_PIOA_PPUDR
-group.PIOA.register.6=AT91C_PIOA_IMR
-group.PIOA.register.7=AT91C_PIOA_PER
-group.PIOA.register.8=AT91C_PIOA_IFDR
-group.PIOA.register.9=AT91C_PIOA_OWDR
-group.PIOA.register.10=AT91C_PIOA_MDSR
-group.PIOA.register.11=AT91C_PIOA_IDR
-group.PIOA.register.12=AT91C_PIOA_ODSR
-group.PIOA.register.13=AT91C_PIOA_PPUSR
-group.PIOA.register.14=AT91C_PIOA_OWSR
-group.PIOA.register.15=AT91C_PIOA_BSR
-group.PIOA.register.16=AT91C_PIOA_OWER
-group.PIOA.register.17=AT91C_PIOA_IFER
-group.PIOA.register.18=AT91C_PIOA_PDSR
-group.PIOA.register.19=AT91C_PIOA_PPUER
-group.PIOA.register.20=AT91C_PIOA_OSR
-group.PIOA.register.21=AT91C_PIOA_ASR
-group.PIOA.register.22=AT91C_PIOA_MDDR
-group.PIOA.register.23=AT91C_PIOA_CODR
-group.PIOA.register.24=AT91C_PIOA_MDER
-group.PIOA.register.25=AT91C_PIOA_PDR
-group.PIOA.register.26=AT91C_PIOA_IFSR
-group.PIOA.register.27=AT91C_PIOA_OER
-group.PIOA.register.28=AT91C_PIOA_PSR
-# ========== Group definition for CKGR peripheral ==========
-group.CKGR.description="ATMEL CKGR Registers"
-group.CKGR.helpkey="ATMEL CKGR Registers"
-group.CKGR.register.0=AT91C_CKGR_MOR
-group.CKGR.register.1=AT91C_CKGR_PLLR
-group.CKGR.register.2=AT91C_CKGR_MCFR
-# ========== Group definition for PMC peripheral ==========
-group.PMC.description="ATMEL PMC Registers"
-group.PMC.helpkey="ATMEL PMC Registers"
-group.PMC.register.0=AT91C_PMC_IDR
-group.PMC.register.1=AT91C_PMC_MOR
-group.PMC.register.2=AT91C_PMC_PLLR
-group.PMC.register.3=AT91C_PMC_PCER
-group.PMC.register.4=AT91C_PMC_PCKR
-group.PMC.register.5=AT91C_PMC_MCKR
-group.PMC.register.6=AT91C_PMC_SCDR
-group.PMC.register.7=AT91C_PMC_PCDR
-group.PMC.register.8=AT91C_PMC_SCSR
-group.PMC.register.9=AT91C_PMC_PCSR
-group.PMC.register.10=AT91C_PMC_MCFR
-group.PMC.register.11=AT91C_PMC_SCER
-group.PMC.register.12=AT91C_PMC_IMR
-group.PMC.register.13=AT91C_PMC_IER
-group.PMC.register.14=AT91C_PMC_SR
-# ========== Group definition for RSTC peripheral ==========
-group.RSTC.description="ATMEL RSTC Registers"
-group.RSTC.helpkey="ATMEL RSTC Registers"
-group.RSTC.register.0=AT91C_RSTC_RCR
-group.RSTC.register.1=AT91C_RSTC_RMR
-group.RSTC.register.2=AT91C_RSTC_RSR
-# ========== Group definition for RTTC peripheral ==========
-group.RTTC.description="ATMEL RTTC Registers"
-group.RTTC.helpkey="ATMEL RTTC Registers"
-group.RTTC.register.0=AT91C_RTTC_RTSR
-group.RTTC.register.1=AT91C_RTTC_RTMR
-group.RTTC.register.2=AT91C_RTTC_RTVR
-group.RTTC.register.3=AT91C_RTTC_RTAR
-# ========== Group definition for PITC peripheral ==========
-group.PITC.description="ATMEL PITC Registers"
-group.PITC.helpkey="ATMEL PITC Registers"
-group.PITC.register.0=AT91C_PITC_PIVR
-group.PITC.register.1=AT91C_PITC_PISR
-group.PITC.register.2=AT91C_PITC_PIIR
-group.PITC.register.3=AT91C_PITC_PIMR
-# ========== Group definition for WDTC peripheral ==========
-group.WDTC.description="ATMEL WDTC Registers"
-group.WDTC.helpkey="ATMEL WDTC Registers"
-group.WDTC.register.0=AT91C_WDTC_WDCR
-group.WDTC.register.1=AT91C_WDTC_WDSR
-group.WDTC.register.2=AT91C_WDTC_WDMR
-# ========== Group definition for VREG peripheral ==========
-group.VREG.description="ATMEL VREG Registers"
-group.VREG.helpkey="ATMEL VREG Registers"
-group.VREG.register.0=AT91C_VREG_MR
-# ========== Group definition for MC peripheral ==========
-group.MC.description="ATMEL MC Registers"
-group.MC.helpkey="ATMEL MC Registers"
-group.MC.register.0=AT91C_MC_ASR
-group.MC.register.1=AT91C_MC_RCR
-group.MC.register.2=AT91C_MC_FCR
-group.MC.register.3=AT91C_MC_AASR
-group.MC.register.4=AT91C_MC_FSR
-group.MC.register.5=AT91C_MC_FMR
-# ========== Group definition for PDC_SPI peripheral ==========
-group.PDC_SPI.description="ATMEL PDC_SPI Registers"
-group.PDC_SPI.helpkey="ATMEL PDC_SPI Registers"
-group.PDC_SPI.register.0=AT91C_SPI_PTCR
-group.PDC_SPI.register.1=AT91C_SPI_TPR
-group.PDC_SPI.register.2=AT91C_SPI_TCR
-group.PDC_SPI.register.3=AT91C_SPI_RCR
-group.PDC_SPI.register.4=AT91C_SPI_PTSR
-group.PDC_SPI.register.5=AT91C_SPI_RNPR
-group.PDC_SPI.register.6=AT91C_SPI_RPR
-group.PDC_SPI.register.7=AT91C_SPI_TNCR
-group.PDC_SPI.register.8=AT91C_SPI_RNCR
-group.PDC_SPI.register.9=AT91C_SPI_TNPR
-# ========== Group definition for SPI peripheral ==========
-group.SPI.description="ATMEL SPI Registers"
-group.SPI.helpkey="ATMEL SPI Registers"
-group.SPI.register.0=AT91C_SPI_IER
-group.SPI.register.1=AT91C_SPI_SR
-group.SPI.register.2=AT91C_SPI_IDR
-group.SPI.register.3=AT91C_SPI_CR
-group.SPI.register.4=AT91C_SPI_MR
-group.SPI.register.5=AT91C_SPI_IMR
-group.SPI.register.6=AT91C_SPI_TDR
-group.SPI.register.7=AT91C_SPI_RDR
-group.SPI.register.8=AT91C_SPI_CSR
-# ========== Group definition for PDC_ADC peripheral ==========
-group.PDC_ADC.description="ATMEL PDC_ADC Registers"
-group.PDC_ADC.helpkey="ATMEL PDC_ADC Registers"
-group.PDC_ADC.register.0=AT91C_ADC_PTSR
-group.PDC_ADC.register.1=AT91C_ADC_PTCR
-group.PDC_ADC.register.2=AT91C_ADC_TNPR
-group.PDC_ADC.register.3=AT91C_ADC_TNCR
-group.PDC_ADC.register.4=AT91C_ADC_RNPR
-group.PDC_ADC.register.5=AT91C_ADC_RNCR
-group.PDC_ADC.register.6=AT91C_ADC_RPR
-group.PDC_ADC.register.7=AT91C_ADC_TCR
-group.PDC_ADC.register.8=AT91C_ADC_TPR
-group.PDC_ADC.register.9=AT91C_ADC_RCR
-# ========== Group definition for ADC peripheral ==========
-group.ADC.description="ATMEL ADC Registers"
-group.ADC.helpkey="ATMEL ADC Registers"
-group.ADC.register.0=AT91C_ADC_CDR2
-group.ADC.register.1=AT91C_ADC_CDR3
-group.ADC.register.2=AT91C_ADC_CDR0
-group.ADC.register.3=AT91C_ADC_CDR5
-group.ADC.register.4=AT91C_ADC_CHDR
-group.ADC.register.5=AT91C_ADC_SR
-group.ADC.register.6=AT91C_ADC_CDR4
-group.ADC.register.7=AT91C_ADC_CDR1
-group.ADC.register.8=AT91C_ADC_LCDR
-group.ADC.register.9=AT91C_ADC_IDR
-group.ADC.register.10=AT91C_ADC_CR
-group.ADC.register.11=AT91C_ADC_CDR7
-group.ADC.register.12=AT91C_ADC_CDR6
-group.ADC.register.13=AT91C_ADC_IER
-group.ADC.register.14=AT91C_ADC_CHER
-group.ADC.register.15=AT91C_ADC_CHSR
-group.ADC.register.16=AT91C_ADC_MR
-group.ADC.register.17=AT91C_ADC_IMR
-# ========== Group definition for PDC_SSC peripheral ==========
-group.PDC_SSC.description="ATMEL PDC_SSC Registers"
-group.PDC_SSC.helpkey="ATMEL PDC_SSC Registers"
-group.PDC_SSC.register.0=AT91C_SSC_TNCR
-group.PDC_SSC.register.1=AT91C_SSC_RPR
-group.PDC_SSC.register.2=AT91C_SSC_RNCR
-group.PDC_SSC.register.3=AT91C_SSC_TPR
-group.PDC_SSC.register.4=AT91C_SSC_PTCR
-group.PDC_SSC.register.5=AT91C_SSC_TCR
-group.PDC_SSC.register.6=AT91C_SSC_RCR
-group.PDC_SSC.register.7=AT91C_SSC_RNPR
-group.PDC_SSC.register.8=AT91C_SSC_TNPR
-group.PDC_SSC.register.9=AT91C_SSC_PTSR
-# ========== Group definition for SSC peripheral ==========
-group.SSC.description="ATMEL SSC Registers"
-group.SSC.helpkey="ATMEL SSC Registers"
-group.SSC.register.0=AT91C_SSC_RHR
-group.SSC.register.1=AT91C_SSC_RSHR
-group.SSC.register.2=AT91C_SSC_TFMR
-group.SSC.register.3=AT91C_SSC_IDR
-group.SSC.register.4=AT91C_SSC_THR
-group.SSC.register.5=AT91C_SSC_RCMR
-group.SSC.register.6=AT91C_SSC_IER
-group.SSC.register.7=AT91C_SSC_TSHR
-group.SSC.register.8=AT91C_SSC_SR
-group.SSC.register.9=AT91C_SSC_CMR
-group.SSC.register.10=AT91C_SSC_TCMR
-group.SSC.register.11=AT91C_SSC_CR
-group.SSC.register.12=AT91C_SSC_IMR
-group.SSC.register.13=AT91C_SSC_RFMR
-# ========== Group definition for PDC_US1 peripheral ==========
-group.PDC_US1.description="ATMEL PDC_US1 Registers"
-group.PDC_US1.helpkey="ATMEL PDC_US1 Registers"
-group.PDC_US1.register.0=AT91C_US1_RNCR
-group.PDC_US1.register.1=AT91C_US1_PTCR
-group.PDC_US1.register.2=AT91C_US1_TCR
-group.PDC_US1.register.3=AT91C_US1_PTSR
-group.PDC_US1.register.4=AT91C_US1_TNPR
-group.PDC_US1.register.5=AT91C_US1_RCR
-group.PDC_US1.register.6=AT91C_US1_RNPR
-group.PDC_US1.register.7=AT91C_US1_RPR
-group.PDC_US1.register.8=AT91C_US1_TNCR
-group.PDC_US1.register.9=AT91C_US1_TPR
-# ========== Group definition for US1 peripheral ==========
-group.US1.description="ATMEL US1 Registers"
-group.US1.helpkey="ATMEL US1 Registers"
-group.US1.register.0=AT91C_US1_IF
-group.US1.register.1=AT91C_US1_NER
-group.US1.register.2=AT91C_US1_RTOR
-group.US1.register.3=AT91C_US1_CSR
-group.US1.register.4=AT91C_US1_IDR
-group.US1.register.5=AT91C_US1_IER
-group.US1.register.6=AT91C_US1_THR
-group.US1.register.7=AT91C_US1_TTGR
-group.US1.register.8=AT91C_US1_RHR
-group.US1.register.9=AT91C_US1_BRGR
-group.US1.register.10=AT91C_US1_IMR
-group.US1.register.11=AT91C_US1_FIDI
-group.US1.register.12=AT91C_US1_CR
-group.US1.register.13=AT91C_US1_MR
-# ========== Group definition for PDC_US0 peripheral ==========
-group.PDC_US0.description="ATMEL PDC_US0 Registers"
-group.PDC_US0.helpkey="ATMEL PDC_US0 Registers"
-group.PDC_US0.register.0=AT91C_US0_TNPR
-group.PDC_US0.register.1=AT91C_US0_RNPR
-group.PDC_US0.register.2=AT91C_US0_TCR
-group.PDC_US0.register.3=AT91C_US0_PTCR
-group.PDC_US0.register.4=AT91C_US0_PTSR
-group.PDC_US0.register.5=AT91C_US0_TNCR
-group.PDC_US0.register.6=AT91C_US0_TPR
-group.PDC_US0.register.7=AT91C_US0_RCR
-group.PDC_US0.register.8=AT91C_US0_RPR
-group.PDC_US0.register.9=AT91C_US0_RNCR
-# ========== Group definition for US0 peripheral ==========
-group.US0.description="ATMEL US0 Registers"
-group.US0.helpkey="ATMEL US0 Registers"
-group.US0.register.0=AT91C_US0_BRGR
-group.US0.register.1=AT91C_US0_NER
-group.US0.register.2=AT91C_US0_CR
-group.US0.register.3=AT91C_US0_IMR
-group.US0.register.4=AT91C_US0_FIDI
-group.US0.register.5=AT91C_US0_TTGR
-group.US0.register.6=AT91C_US0_MR
-group.US0.register.7=AT91C_US0_RTOR
-group.US0.register.8=AT91C_US0_CSR
-group.US0.register.9=AT91C_US0_RHR
-group.US0.register.10=AT91C_US0_IDR
-group.US0.register.11=AT91C_US0_THR
-group.US0.register.12=AT91C_US0_IF
-group.US0.register.13=AT91C_US0_IER
-# ========== Group definition for TWI peripheral ==========
-group.TWI.description="ATMEL TWI Registers"
-group.TWI.helpkey="ATMEL TWI Registers"
-group.TWI.register.0=AT91C_TWI_IER
-group.TWI.register.1=AT91C_TWI_CR
-group.TWI.register.2=AT91C_TWI_SR
-group.TWI.register.3=AT91C_TWI_IMR
-group.TWI.register.4=AT91C_TWI_THR
-group.TWI.register.5=AT91C_TWI_IDR
-group.TWI.register.6=AT91C_TWI_IADR
-group.TWI.register.7=AT91C_TWI_MMR
-group.TWI.register.8=AT91C_TWI_CWGR
-group.TWI.register.9=AT91C_TWI_RHR
-# ========== Group definition for TC0 peripheral ==========
-group.TC0.description="ATMEL TC0 Registers"
-group.TC0.helpkey="ATMEL TC0 Registers"
-group.TC0.register.0=AT91C_TC0_SR
-group.TC0.register.1=AT91C_TC0_RC
-group.TC0.register.2=AT91C_TC0_RB
-group.TC0.register.3=AT91C_TC0_CCR
-group.TC0.register.4=AT91C_TC0_CMR
-group.TC0.register.5=AT91C_TC0_IER
-group.TC0.register.6=AT91C_TC0_RA
-group.TC0.register.7=AT91C_TC0_IDR
-group.TC0.register.8=AT91C_TC0_CV
-group.TC0.register.9=AT91C_TC0_IMR
-# ========== Group definition for TC1 peripheral ==========
-group.TC1.description="ATMEL TC1 Registers"
-group.TC1.helpkey="ATMEL TC1 Registers"
-group.TC1.register.0=AT91C_TC1_RB
-group.TC1.register.1=AT91C_TC1_CCR
-group.TC1.register.2=AT91C_TC1_IER
-group.TC1.register.3=AT91C_TC1_IDR
-group.TC1.register.4=AT91C_TC1_SR
-group.TC1.register.5=AT91C_TC1_CMR
-group.TC1.register.6=AT91C_TC1_RA
-group.TC1.register.7=AT91C_TC1_RC
-group.TC1.register.8=AT91C_TC1_IMR
-group.TC1.register.9=AT91C_TC1_CV
-# ========== Group definition for TC2 peripheral ==========
-group.TC2.description="ATMEL TC2 Registers"
-group.TC2.helpkey="ATMEL TC2 Registers"
-group.TC2.register.0=AT91C_TC2_CMR
-group.TC2.register.1=AT91C_TC2_CCR
-group.TC2.register.2=AT91C_TC2_CV
-group.TC2.register.3=AT91C_TC2_RA
-group.TC2.register.4=AT91C_TC2_RB
-group.TC2.register.5=AT91C_TC2_IDR
-group.TC2.register.6=AT91C_TC2_IMR
-group.TC2.register.7=AT91C_TC2_RC
-group.TC2.register.8=AT91C_TC2_IER
-group.TC2.register.9=AT91C_TC2_SR
-# ========== Group definition for TCB peripheral ==========
-group.TCB.description="ATMEL TCB Registers"
-group.TCB.helpkey="ATMEL TCB Registers"
-group.TCB.register.0=AT91C_TCB_BMR
-group.TCB.register.1=AT91C_TCB_BCR
-# ========== Group definition for PWMC_CH3 peripheral ==========
-group.PWMC_CH3.description="ATMEL PWMC_CH3 Registers"
-group.PWMC_CH3.helpkey="ATMEL PWMC_CH3 Registers"
-group.PWMC_CH3.register.0=AT91C_PWMC_CH3_CUPDR
-group.PWMC_CH3.register.1=AT91C_PWMC_CH3_Reserved
-group.PWMC_CH3.register.2=AT91C_PWMC_CH3_CPRDR
-group.PWMC_CH3.register.3=AT91C_PWMC_CH3_CDTYR
-group.PWMC_CH3.register.4=AT91C_PWMC_CH3_CCNTR
-group.PWMC_CH3.register.5=AT91C_PWMC_CH3_CMR
-# ========== Group definition for PWMC_CH2 peripheral ==========
-group.PWMC_CH2.description="ATMEL PWMC_CH2 Registers"
-group.PWMC_CH2.helpkey="ATMEL PWMC_CH2 Registers"
-group.PWMC_CH2.register.0=AT91C_PWMC_CH2_Reserved
-group.PWMC_CH2.register.1=AT91C_PWMC_CH2_CMR
-group.PWMC_CH2.register.2=AT91C_PWMC_CH2_CCNTR
-group.PWMC_CH2.register.3=AT91C_PWMC_CH2_CPRDR
-group.PWMC_CH2.register.4=AT91C_PWMC_CH2_CUPDR
-group.PWMC_CH2.register.5=AT91C_PWMC_CH2_CDTYR
-# ========== Group definition for PWMC_CH1 peripheral ==========
-group.PWMC_CH1.description="ATMEL PWMC_CH1 Registers"
-group.PWMC_CH1.helpkey="ATMEL PWMC_CH1 Registers"
-group.PWMC_CH1.register.0=AT91C_PWMC_CH1_Reserved
-group.PWMC_CH1.register.1=AT91C_PWMC_CH1_CUPDR
-group.PWMC_CH1.register.2=AT91C_PWMC_CH1_CPRDR
-group.PWMC_CH1.register.3=AT91C_PWMC_CH1_CCNTR
-group.PWMC_CH1.register.4=AT91C_PWMC_CH1_CDTYR
-group.PWMC_CH1.register.5=AT91C_PWMC_CH1_CMR
-# ========== Group definition for PWMC_CH0 peripheral ==========
-group.PWMC_CH0.description="ATMEL PWMC_CH0 Registers"
-group.PWMC_CH0.helpkey="ATMEL PWMC_CH0 Registers"
-group.PWMC_CH0.register.0=AT91C_PWMC_CH0_Reserved
-group.PWMC_CH0.register.1=AT91C_PWMC_CH0_CPRDR
-group.PWMC_CH0.register.2=AT91C_PWMC_CH0_CDTYR
-group.PWMC_CH0.register.3=AT91C_PWMC_CH0_CMR
-group.PWMC_CH0.register.4=AT91C_PWMC_CH0_CUPDR
-group.PWMC_CH0.register.5=AT91C_PWMC_CH0_CCNTR
-# ========== Group definition for PWMC peripheral ==========
-group.PWMC.description="ATMEL PWMC Registers"
-group.PWMC.helpkey="ATMEL PWMC Registers"
-group.PWMC.register.0=AT91C_PWMC_IDR
-group.PWMC.register.1=AT91C_PWMC_DIS
-group.PWMC.register.2=AT91C_PWMC_IER
-group.PWMC.register.3=AT91C_PWMC_VR
-group.PWMC.register.4=AT91C_PWMC_ISR
-group.PWMC.register.5=AT91C_PWMC_SR
-group.PWMC.register.6=AT91C_PWMC_IMR
-group.PWMC.register.7=AT91C_PWMC_MR
-group.PWMC.register.8=AT91C_PWMC_ENA
-# ========== Group definition for UDP peripheral ==========
-group.UDP.description="ATMEL UDP Registers"
-group.UDP.helpkey="ATMEL UDP Registers"
-group.UDP.register.0=AT91C_UDP_IMR
-group.UDP.register.1=AT91C_UDP_FADDR
-group.UDP.register.2=AT91C_UDP_NUM
-group.UDP.register.3=AT91C_UDP_FDR
-group.UDP.register.4=AT91C_UDP_ISR
-group.UDP.register.5=AT91C_UDP_CSR
-group.UDP.register.6=AT91C_UDP_IDR
-group.UDP.register.7=AT91C_UDP_ICR
-group.UDP.register.8=AT91C_UDP_RSTEP
-group.UDP.register.9=AT91C_UDP_TXVC
-group.UDP.register.10=AT91C_UDP_GLBSTATE
-group.UDP.register.11=AT91C_UDP_IER
-group.AT91SAM7S64.description="ATMEL AT91SAM7S64 Registers"
-group.AT91SAM7S64.helpkey="ATMEL AT91SAM7S64 Registers"
-group.AT91SAM7S64.topLevelIndex=100
-group.AT91SAM7S64.group.0=SYS
-group.AT91SAM7S64.group.1=AIC
-group.AT91SAM7S64.group.2=PDC_DBGU
-group.AT91SAM7S64.group.3=DBGU
-group.AT91SAM7S64.group.4=PIOA
-group.AT91SAM7S64.group.5=CKGR
-group.AT91SAM7S64.group.6=PMC
-group.AT91SAM7S64.group.7=RSTC
-group.AT91SAM7S64.group.8=RTTC
-group.AT91SAM7S64.group.9=PITC
-group.AT91SAM7S64.group.10=WDTC
-group.AT91SAM7S64.group.11=VREG
-group.AT91SAM7S64.group.12=MC
-group.AT91SAM7S64.group.13=PDC_SPI
-group.AT91SAM7S64.group.14=SPI
-group.AT91SAM7S64.group.15=PDC_ADC
-group.AT91SAM7S64.group.16=ADC
-group.AT91SAM7S64.group.17=PDC_SSC
-group.AT91SAM7S64.group.18=SSC
-group.AT91SAM7S64.group.19=PDC_US1
-group.AT91SAM7S64.group.20=US1
-group.AT91SAM7S64.group.21=PDC_US0
-group.AT91SAM7S64.group.22=US0
-group.AT91SAM7S64.group.23=TWI
-group.AT91SAM7S64.group.24=TC0
-group.AT91SAM7S64.group.25=TC1
-group.AT91SAM7S64.group.26=TC2
-group.AT91SAM7S64.group.27=TCB
-group.AT91SAM7S64.group.28=PWMC_CH3
-group.AT91SAM7S64.group.29=PWMC_CH2
-group.AT91SAM7S64.group.30=PWMC_CH1
-group.AT91SAM7S64.group.31=PWMC_CH0
-group.AT91SAM7S64.group.32=PWMC
-group.AT91SAM7S64.group.33=UDP
diff --git a/openpcd/firmware/include/old/AT91SAM7S64_inc.h b/openpcd/firmware/include/old/AT91SAM7S64_inc.h deleted file mode 100644 index 7ac6975..0000000 --- a/openpcd/firmware/include/old/AT91SAM7S64_inc.h +++ /dev/null @@ -1,1706 +0,0 @@ -// ---------------------------------------------------------------------------- -// ATMEL Microcontroller Software Support - ROUSSET - -// ---------------------------------------------------------------------------- -// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// ---------------------------------------------------------------------------- -// File Name : AT91SAM7S64.h -// Object : AT91SAM7S64 definitions -// Generated : AT91 SW Application Group 08/30/2005 (15:52:59) -// -// CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005// -// CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// -// CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005// -// CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// -// CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005// -// CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005// -// CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005// -// CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// ---------------------------------------------------------------------------- - -// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -// *** Register offset in AT91S_AIC structure *** -#define AIC_SMR ( 0) // Source Mode Register -#define AIC_SVR (128) // Source Vector Register -#define AIC_IVR (256) // IRQ Vector Register -#define AIC_FVR (260) // FIQ Vector Register -#define AIC_ISR (264) // Interrupt Status Register -#define AIC_IPR (268) // Interrupt Pending Register -#define AIC_IMR (272) // Interrupt Mask Register -#define AIC_CISR (276) // Core Interrupt Status Register -#define AIC_IECR (288) // Interrupt Enable Command Register -#define AIC_IDCR (292) // Interrupt Disable Command Register -#define AIC_ICCR (296) // Interrupt Clear Command Register -#define AIC_ISCR (300) // Interrupt Set Command Register -#define AIC_EOICR (304) // End of Interrupt Command Register -#define AIC_SPU (308) // Spurious Vector Register -#define AIC_DCR (312) // Debug Control Register (Protect) -#define AIC_FFER (320) // Fast Forcing Enable Register -#define AIC_FFDR (324) // Fast Forcing Disable Register -#define AIC_FFSR (328) // Fast Forcing Status Register -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR (0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST (0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST (0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE (0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL (0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL (0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE (0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE (0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL (0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE (0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ (0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ (0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT (0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK (0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -// *** Register offset in AT91S_PDC structure *** -#define PDC_RPR ( 0) // Receive Pointer Register -#define PDC_RCR ( 4) // Receive Counter Register -#define PDC_TPR ( 8) // Transmit Pointer Register -#define PDC_TCR (12) // Transmit Counter Register -#define PDC_RNPR (16) // Receive Next Pointer Register -#define PDC_RNCR (20) // Receive Next Counter Register -#define PDC_TNPR (24) // Transmit Next Pointer Register -#define PDC_TNCR (28) // Transmit Next Counter Register -#define PDC_PTCR (32) // PDC Transfer Control Register -#define PDC_PTSR (36) // PDC Transfer Status Register -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN (0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS (0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN (0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS (0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -// *** Register offset in AT91S_DBGU structure *** -#define DBGU_CR ( 0) // Control Register -#define DBGU_MR ( 4) // Mode Register -#define DBGU_IER ( 8) // Interrupt Enable Register -#define DBGU_IDR (12) // Interrupt Disable Register -#define DBGU_IMR (16) // Interrupt Mask Register -#define DBGU_CSR (20) // Channel Status Register -#define DBGU_RHR (24) // Receiver Holding Register -#define DBGU_THR (28) // Transmitter Holding Register -#define DBGU_BRGR (32) // Baud Rate Generator Register -#define DBGU_CIDR (64) // Chip ID Register -#define DBGU_EXID (68) // Chip ID Extension Register -#define DBGU_FNTR (72) // Force NTRST Register -#define DBGU_RPR (256) // Receive Pointer Register -#define DBGU_RCR (260) // Receive Counter Register -#define DBGU_TPR (264) // Transmit Pointer Register -#define DBGU_TCR (268) // Transmit Counter Register -#define DBGU_RNPR (272) // Receive Next Pointer Register -#define DBGU_RNCR (276) // Receive Next Counter Register -#define DBGU_TNPR (280) // Transmit Next Pointer Register -#define DBGU_TNCR (284) // Transmit Next Counter Register -#define DBGU_PTCR (288) // PDC Transfer Control Register -#define DBGU_PTSR (292) // PDC Transfer Status Register -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX (0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX (0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN (0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS (0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN (0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS (0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA (0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR (0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN (0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD (0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE (0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK (0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE (0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP (0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE (0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY (0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY (0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX (0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX (0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE (0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME (0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE (0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY (0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE (0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF (0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX (0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX (0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST (0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -// *** Register offset in AT91S_PIO structure *** -#define PIO_PER ( 0) // PIO Enable Register -#define PIO_PDR ( 4) // PIO Disable Register -#define PIO_PSR ( 8) // PIO Status Register -#define PIO_OER (16) // Output Enable Register -#define PIO_ODR (20) // Output Disable Registerr -#define PIO_OSR (24) // Output Status Register -#define PIO_IFER (32) // Input Filter Enable Register -#define PIO_IFDR (36) // Input Filter Disable Register -#define PIO_IFSR (40) // Input Filter Status Register -#define PIO_SODR (48) // Set Output Data Register -#define PIO_CODR (52) // Clear Output Data Register -#define PIO_ODSR (56) // Output Data Status Register -#define PIO_PDSR (60) // Pin Data Status Register -#define PIO_IER (64) // Interrupt Enable Register -#define PIO_IDR (68) // Interrupt Disable Register -#define PIO_IMR (72) // Interrupt Mask Register -#define PIO_ISR (76) // Interrupt Status Register -#define PIO_MDER (80) // Multi-driver Enable Register -#define PIO_MDDR (84) // Multi-driver Disable Register -#define PIO_MDSR (88) // Multi-driver Status Register -#define PIO_PPUDR (96) // Pull-up Disable Register -#define PIO_PPUER (100) // Pull-up Enable Register -#define PIO_PPUSR (104) // Pull-up Status Register -#define PIO_ASR (112) // Select A Register -#define PIO_BSR (116) // Select B Register -#define PIO_ABSR (120) // AB Select Status Register -#define PIO_OWER (160) // Output Write Enable Register -#define PIO_OWDR (164) // Output Write Disable Register -#define PIO_OWSR (168) // Output Write Status Register - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -// *** Register offset in AT91S_CKGR structure *** -#define CKGR_MOR ( 0) // Main Oscillator Register -#define CKGR_MCFR ( 4) // Main Clock Frequency Register -#define CKGR_PLLR (12) // PLL Register -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN (0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS (0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT (0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF (0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY (0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV (0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 (0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS (0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT (0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT (0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 (0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 (0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 (0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 (0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL (0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV (0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 (0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -// *** Register offset in AT91S_PMC structure *** -#define PMC_SCER ( 0) // System Clock Enable Register -#define PMC_SCDR ( 4) // System Clock Disable Register -#define PMC_SCSR ( 8) // System Clock Status Register -#define PMC_PCER (16) // Peripheral Clock Enable Register -#define PMC_PCDR (20) // Peripheral Clock Disable Register -#define PMC_PCSR (24) // Peripheral Clock Status Register -#define PMC_MOR (32) // Main Oscillator Register -#define PMC_MCFR (36) // Main Clock Frequency Register -#define PMC_PLLR (44) // PLL Register -#define PMC_MCKR (48) // Master Clock Register -#define PMC_PCKR (64) // Programmable Clock Register -#define PMC_IER (96) // Interrupt Enable Register -#define PMC_IDR (100) // Interrupt Disable Register -#define PMC_SR (104) // Status Register -#define PMC_IMR (108) // Interrupt Mask Register -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK (0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP (0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 (0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 (0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 (0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS (0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK (0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK (0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK (0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES (0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK (0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 (0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 (0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 (0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 (0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 (0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 (0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS (0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK (0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY (0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY (0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY (0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RSTC structure *** -#define RSTC_RCR ( 0) // Reset Control Register -#define RSTC_RSR ( 4) // Reset Status Register -#define RSTC_RMR ( 8) // Reset Mode Register -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST (0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST (0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST (0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY (0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS (0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS (0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP (0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP (0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP (0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG (0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE (0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER (0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT (0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL (0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP (0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN (0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN (0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL (0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_RTTC structure *** -#define RTTC_RTMR ( 0) // Real-time Mode Register -#define RTTC_RTAR ( 4) // Real-time Alarm Register -#define RTTC_RTVR ( 8) // Real-time Value Register -#define RTTC_RTSR (12) // Real-time Status Register -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES (0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN (0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST (0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV (0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV (0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS (0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC (0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PITC structure *** -#define PITC_PIMR ( 0) // Period Interval Mode Register -#define PITC_PISR ( 4) // Period Interval Status Register -#define PITC_PIVR ( 8) // Period Interval Value Register -#define PITC_PIIR (12) // Period Interval Image Register -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV (0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN (0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS (0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV (0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT (0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_WDTC structure *** -#define WDTC_WDCR ( 0) // Watchdog Control Register -#define WDTC_WDMR ( 4) // Watchdog Mode Register -#define WDTC_WDSR ( 8) // Watchdog Status Register -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT (0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY (0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV (0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN (0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC (0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS (0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD (0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT (0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT (0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF (0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR (0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_VREG structure *** -#define VREG_MR ( 0) // Voltage Regulator Mode Register -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY (0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_MC structure *** -#define MC_RCR ( 0) // MC Remap Control Register -#define MC_ASR ( 4) // MC Abort Status Register -#define MC_AASR ( 8) // MC Abort Address Status Register -#define MC_FMR (96) // MC Flash Mode Register -#define MC_FCR (100) // MC Flash Command Register -#define MC_FSR (104) // MC Flash Status Register -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB (0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD (0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD (0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ (0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE (0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD (0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD (0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP (0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR (0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW (0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH (0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 (0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 (0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 (0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 (0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY (0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE (0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE (0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP (0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS (0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS (0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS (0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS (0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS (0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN (0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD (0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG (0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM (0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM (0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY (0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN (0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY (0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY (0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 (0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 (0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 (0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 (0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 (0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 (0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 (0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 (0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 (0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 (0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 (0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 (0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 (0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 (0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 (0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 (0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 (0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 (0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 (0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 (0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 (0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 (0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 (0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 (0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -// *** Register offset in AT91S_SPI structure *** -#define SPI_CR ( 0) // Control Register -#define SPI_MR ( 4) // Mode Register -#define SPI_RDR ( 8) // Receive Data Register -#define SPI_TDR (12) // Transmit Data Register -#define SPI_SR (16) // Status Register -#define SPI_IER (20) // Interrupt Enable Register -#define SPI_IDR (24) // Interrupt Disable Register -#define SPI_IMR (28) // Interrupt Mask Register -#define SPI_CSR (48) // Chip Select Register -#define SPI_RPR (256) // Receive Pointer Register -#define SPI_RCR (260) // Receive Counter Register -#define SPI_TPR (264) // Transmit Pointer Register -#define SPI_TCR (268) // Transmit Counter Register -#define SPI_RNPR (272) // Receive Next Pointer Register -#define SPI_RNCR (276) // Receive Next Counter Register -#define SPI_TNPR (280) // Transmit Next Pointer Register -#define SPI_TNCR (284) // Transmit Next Counter Register -#define SPI_PTCR (288) // PDC Transfer Control Register -#define SPI_PTSR (292) // PDC Transfer Status Register -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN (0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS (0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST (0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER (0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR (0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS (0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED (0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE (0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC (0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV (0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS (0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB (0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS (0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS (0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD (0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD (0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS (0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF (0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE (0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF (0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES (0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX (0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX (0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF (0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE (0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR (0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY (0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS (0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL (0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA (0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT (0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS (0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 (0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 (0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 (0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 (0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 (0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 (0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 (0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 (0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 (0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR (0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS (0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT (0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -// *** Register offset in AT91S_ADC structure *** -#define ADC_CR ( 0) // ADC Control Register -#define ADC_MR ( 4) // ADC Mode Register -#define ADC_CHER (16) // ADC Channel Enable Register -#define ADC_CHDR (20) // ADC Channel Disable Register -#define ADC_CHSR (24) // ADC Channel Status Register -#define ADC_SR (28) // ADC Status Register -#define ADC_LCDR (32) // ADC Last Converted Data Register -#define ADC_IER (36) // ADC Interrupt Enable Register -#define ADC_IDR (40) // ADC Interrupt Disable Register -#define ADC_IMR (44) // ADC Interrupt Mask Register -#define ADC_CDR0 (48) // ADC Channel Data Register 0 -#define ADC_CDR1 (52) // ADC Channel Data Register 1 -#define ADC_CDR2 (56) // ADC Channel Data Register 2 -#define ADC_CDR3 (60) // ADC Channel Data Register 3 -#define ADC_CDR4 (64) // ADC Channel Data Register 4 -#define ADC_CDR5 (68) // ADC Channel Data Register 5 -#define ADC_CDR6 (72) // ADC Channel Data Register 6 -#define ADC_CDR7 (76) // ADC Channel Data Register 7 -#define ADC_RPR (256) // Receive Pointer Register -#define ADC_RCR (260) // Receive Counter Register -#define ADC_TPR (264) // Transmit Pointer Register -#define ADC_TCR (268) // Transmit Counter Register -#define ADC_RNPR (272) // Receive Next Pointer Register -#define ADC_RNCR (276) // Receive Next Counter Register -#define ADC_TNPR (280) // Transmit Next Pointer Register -#define ADC_TNCR (284) // Transmit Next Counter Register -#define ADC_PTCR (288) // PDC Transfer Control Register -#define ADC_PTSR (292) // PDC Transfer Status Register -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST (0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START (0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN (0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL (0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 (0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 (0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 (0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 (0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 (0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 (0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT (0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES (0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT (0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT (0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE (0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE (0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL (0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP (0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM (0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 (0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 (0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 (0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 (0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 (0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 (0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 (0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 (0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 (0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 (0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 (0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 (0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 (0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 (0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 (0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 (0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 (0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 (0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 (0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 (0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 (0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 (0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 (0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 (0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY (0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE (0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX (0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF (0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA (0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA (0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_SSC structure *** -#define SSC_CR ( 0) // Control Register -#define SSC_CMR ( 4) // Clock Mode Register -#define SSC_RCMR (16) // Receive Clock ModeRegister -#define SSC_RFMR (20) // Receive Frame Mode Register -#define SSC_TCMR (24) // Transmit Clock Mode Register -#define SSC_TFMR (28) // Transmit Frame Mode Register -#define SSC_RHR (32) // Receive Holding Register -#define SSC_THR (36) // Transmit Holding Register -#define SSC_RSHR (48) // Receive Sync Holding Register -#define SSC_TSHR (52) // Transmit Sync Holding Register -#define SSC_SR (64) // Status Register -#define SSC_IER (68) // Interrupt Enable Register -#define SSC_IDR (72) // Interrupt Disable Register -#define SSC_IMR (76) // Interrupt Mask Register -#define SSC_RPR (256) // Receive Pointer Register -#define SSC_RCR (260) // Receive Counter Register -#define SSC_TPR (264) // Transmit Pointer Register -#define SSC_TCR (268) // Transmit Counter Register -#define SSC_RNPR (272) // Receive Next Pointer Register -#define SSC_RNCR (276) // Receive Next Counter Register -#define SSC_TNPR (280) // Transmit Next Pointer Register -#define SSC_TNCR (284) // Transmit Next Counter Register -#define SSC_PTCR (288) // PDC Transfer Control Register -#define SSC_PTSR (292) // PDC Transfer Status Register -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN (0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS (0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN (0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS (0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST (0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS (0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV (0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK (0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK (0x2) // (SSC) RK pin -#define AT91C_SSC_CKO (0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE (0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS (0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX (0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI (0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START (0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS (0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX (0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF (0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF (0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF (0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF (0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF (0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF (0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 (0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY (0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN (0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP (0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF (0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB (0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN (0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE (0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF (0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN (0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY (0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY (0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX (0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE (0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY (0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN (0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX (0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF (0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN (0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN (0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA (0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA (0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -// *** Register offset in AT91S_USART structure *** -#define US_CR ( 0) // Control Register -#define US_MR ( 4) // Mode Register -#define US_IER ( 8) // Interrupt Enable Register -#define US_IDR (12) // Interrupt Disable Register -#define US_IMR (16) // Interrupt Mask Register -#define US_CSR (20) // Channel Status Register -#define US_RHR (24) // Receiver Holding Register -#define US_THR (28) // Transmitter Holding Register -#define US_BRGR (32) // Baud Rate Generator Register -#define US_RTOR (36) // Receiver Time-out Register -#define US_TTGR (40) // Transmitter Time-guard Register -#define US_FIDI (64) // FI_DI_Ratio Register -#define US_NER (68) // Nb Errors Register -#define US_IF (76) // IRDA_FILTER Register -#define US_RPR (256) // Receive Pointer Register -#define US_RCR (260) // Receive Counter Register -#define US_TPR (264) // Transmit Pointer Register -#define US_TCR (268) // Transmit Counter Register -#define US_RNPR (272) // Receive Next Pointer Register -#define US_RNCR (276) // Receive Next Counter Register -#define US_TNPR (280) // Transmit Next Pointer Register -#define US_TNCR (284) // Transmit Next Counter Register -#define US_PTCR (288) // PDC Transfer Control Register -#define US_PTSR (292) // PDC Transfer Status Register -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK (0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK (0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO (0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA (0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT (0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK (0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO (0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN (0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS (0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN (0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS (0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE (0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL (0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 (0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH (0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM (0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 (0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 (0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA (0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH (0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS (0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK (0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 (0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW (0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT (0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL (0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS (0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS (0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS (0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS (0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC (0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP (0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT (0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT (0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF (0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 (0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO (0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER (0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK (0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK (0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER (0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER (0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK (0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT (0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION (0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK (0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC (0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC (0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC (0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC (0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI (0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR (0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD (0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS (0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -// *** Register offset in AT91S_TWI structure *** -#define TWI_CR ( 0) // Control Register -#define TWI_MMR ( 4) // Master Mode Register -#define TWI_IADR (12) // Internal Address Register -#define TWI_CWGR (16) // Clock Waveform Generator Register -#define TWI_SR (32) // Status Register -#define TWI_IER (36) // Interrupt Enable Register -#define TWI_IDR (40) // Interrupt Disable Register -#define TWI_IMR (44) // Interrupt Mask Register -#define TWI_RHR (48) // Receive Holding Register -#define TWI_THR (52) // Transmit Holding Register -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START (0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP (0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN (0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS (0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST (0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ (0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO (0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE (0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE (0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE (0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD (0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR (0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV (0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV (0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV (0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP (0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY (0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY (0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE (0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE (0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK (0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_TC structure *** -#define TC_CCR ( 0) // Channel Control Register -#define TC_CMR ( 4) // Channel Mode Register (Capture Mode / Waveform Mode) -#define TC_CV (16) // Counter Value -#define TC_RA (20) // Register A -#define TC_RB (24) // Register B -#define TC_RC (28) // Register C -#define TC_SR (32) // Status Register -#define TC_IER (36) // Interrupt Enable Register -#define TC_IDR (40) // Interrupt Disable Register -#define TC_IMR (44) // Interrupt Mask Register -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN (0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS (0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG (0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS (0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 (0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 (0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 (0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI (0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST (0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE (0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 (0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 (0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 (0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP (0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS (0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS (0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG (0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG (0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE (0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING (0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING (0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH (0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT (0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG (0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL (0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG (0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE (0x1 << 15) // (TC) -#define AT91C_TC_ACPA (0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE (0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET (0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR (0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE (0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA (0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE (0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING (0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING (0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH (0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC (0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE (0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET (0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR (0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE (0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB (0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE (0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING (0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING (0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH (0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT (0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE (0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET (0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR (0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE (0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG (0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE (0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET (0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR (0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE (0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB (0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE (0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET (0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR (0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE (0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC (0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE (0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET (0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR (0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE (0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT (0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE (0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET (0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR (0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE (0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG (0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE (0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET (0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR (0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE (0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS (0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS (0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS (0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS (0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS (0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS (0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS (0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS (0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA (0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA (0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB (0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -// *** Register offset in AT91S_TCB structure *** -#define TCB_TC0 ( 0) // TC Channel 0 -#define TCB_TC1 (64) // TC Channel 1 -#define TCB_TC2 (128) // TC Channel 2 -#define TCB_BCR (192) // TC Block Control Register -#define TCB_BMR (196) // TC Block Mode Register -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC (0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S (0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 (0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE (0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 (0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 (0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S (0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 (0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE (0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 (0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 (0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S (0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 (0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE (0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 (0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 (0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC_CH structure *** -#define PWMC_CMR ( 0) // Channel Mode Register -#define PWMC_CDTYR ( 4) // Channel Duty Cycle Register -#define PWMC_CPRDR ( 8) // Channel Period Register -#define PWMC_CCNTR (12) // Channel Counter Register -#define PWMC_CUPDR (16) // Channel Update Register -#define PWMC_Reserved (20) // Reserved -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE (0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK (0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA (0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB (0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG (0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL (0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD (0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY (0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD (0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT (0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD (0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -// *** Register offset in AT91S_PWMC structure *** -#define PWMC_MR ( 0) // PWMC Mode Register -#define PWMC_ENA ( 4) // PWMC Enable Register -#define PWMC_DIS ( 8) // PWMC Disable Register -#define PWMC_SR (12) // PWMC Status Register -#define PWMC_IER (16) // PWMC Interrupt Enable Register -#define PWMC_IDR (20) // PWMC Interrupt Disable Register -#define PWMC_IMR (24) // PWMC Interrupt Mask Register -#define PWMC_ISR (28) // PWMC Interrupt Status Register -#define PWMC_VR (252) // PWMC Version Register -#define PWMC_CH (512) // PWMC Channel -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA (0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA (0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK (0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB (0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB (0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK (0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 (0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 (0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 (0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 (0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -// *** Register offset in AT91S_UDP structure *** -#define UDP_NUM ( 0) // Frame Number Register -#define UDP_GLBSTATE ( 4) // Global State Register -#define UDP_FADDR ( 8) // Function Address Register -#define UDP_IER (16) // Interrupt Enable Register -#define UDP_IDR (20) // Interrupt Disable Register -#define UDP_IMR (24) // Interrupt Mask Register -#define UDP_ISR (28) // Interrupt Status Register -#define UDP_ICR (32) // Interrupt Clear Register -#define UDP_RSTEP (40) // Reset Endpoint Register -#define UDP_CSR (48) // Endpoint Control and Status Register -#define UDP_FDR (80) // Endpoint FIFO Data Register -#define UDP_TXVC (116) // Transceiver Control Register -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM (0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR (0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK (0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN (0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG (0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR (0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR (0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE (0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD (0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN (0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 (0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 (0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 (0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 (0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP (0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM (0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM (0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT (0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP (0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 (0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 (0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 (0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 (0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP (0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 (0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP (0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR (0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY (0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL (0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 (0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR (0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE (0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL (0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT (0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT (0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT (0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN (0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN (0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN (0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE (0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS (0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS (0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR (0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR (0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR (0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR (0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR (0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR (0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR (0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR (0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR (0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR (0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR (0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER (0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR (0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR (0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR (0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR (0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR (0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU (0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR (0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID (0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR (0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR (0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR (0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR (0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR (0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR (0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR (0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR (0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR (0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR (0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER (0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR (0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR (0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR (0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR (0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER (0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR (0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR (0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER (0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR (0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR (0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR (0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR (0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR (0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR (0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR (0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR (0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER (0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER (0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR (0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER (0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR (0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR (0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR (0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR (0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER (0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR (0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR (0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER (0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR (0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR (0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR (0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR (0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR (0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR (0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR (0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR (0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR (0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR (0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR (0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR (0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR (0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER (0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR (0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER (0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR (0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR (0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR (0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR (0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR (0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR (0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR (0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR (0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR (0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR (0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR (0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR (0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR (0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR (0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR (0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR (0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR (0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR (0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR (0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR (0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR (0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR (0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR (0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR (0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER (0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR (0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR (0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR (0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR (0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR (0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR (0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR (0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR (0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR (0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR (0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR (0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 (0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 (0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 (0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 (0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR (0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR (0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 (0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 (0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR (0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR (0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR (0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 (0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 (0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER (0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER (0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR (0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR (0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR (0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR (0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR (0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR (0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR (0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR (0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR (0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR (0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR (0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR (0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER (0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR (0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR (0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR (0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR (0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR (0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR (0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR (0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR (0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR (0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR (0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR (0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR (0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF (0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER (0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR (0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR (0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR (0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER (0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR (0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR (0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR (0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR (0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR (0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI (0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR (0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR (0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR (0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR (0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR (0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR (0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR (0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR (0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER (0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR (0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR (0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI (0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR (0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR (0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR (0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR (0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR (0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR (0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR (0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF (0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER (0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER (0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR (0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR (0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR (0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR (0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR (0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR (0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR (0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR (0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR (0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR (0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC (0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB (0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR (0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER (0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA (0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR (0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV (0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR (0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB (0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR (0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER (0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR (0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR (0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA (0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC (0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR (0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV (0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR (0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV (0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA (0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB (0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR (0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR (0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC (0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER (0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR (0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR (0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR (0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR (0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved (0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR (0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR (0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved (0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR (0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR (0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR (0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved (0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR (0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR (0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR (0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved (0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR (0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR (0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR (0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS (0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR (0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR (0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR (0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA (0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR (0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR (0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM (0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR (0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR (0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR (0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR (0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR (0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP (0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC (0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE (0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER (0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 (1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 (AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 (AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 (1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 (AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 (AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 (1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD (AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 (AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 (1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 (AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 (AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 (1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO (AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 (AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 (1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI (AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 (AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 (1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK (AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 (AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 (1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF (AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 (AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 (1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK (AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 (AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 (1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD (AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 (AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 (1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD (AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 (AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 (1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK (AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ (AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 (1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 (AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 (AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 (1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF (AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 (AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 (1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 (AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 (AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 (1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 (AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 (AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 (1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 (AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 (AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 (1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 (AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 (AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 (1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 (AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 (AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 (1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 (AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 (AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 (1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 (AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 (AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 (1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 (AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 (AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 (1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 (AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 (AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 (1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD (AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 (AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 (1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 (AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 (AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 (1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 (AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 (AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 (1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK (AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 (AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 (1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 (AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 (AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 (1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 (AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 (AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 (1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 (AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 (AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 (1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 (AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG (AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 (1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD (AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 (AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ( 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ( 1) // System Peripheral -#define AT91C_ID_PIOA ( 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ( 3) // Reserved -#define AT91C_ID_ADC ( 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ( 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ( 6) // USART 0 -#define AT91C_ID_US1 ( 7) // USART 1 -#define AT91C_ID_SSC ( 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ( 9) // Two-Wire Interface -#define AT91C_ID_PWMC (10) // PWM Controller -#define AT91C_ID_UDP (11) // USB Device Port -#define AT91C_ID_TC0 (12) // Timer Counter 0 -#define AT91C_ID_TC1 (13) // Timer Counter 1 -#define AT91C_ID_TC2 (14) // Timer Counter 2 -#define AT91C_ID_15_Reserved (15) // Reserved -#define AT91C_ID_16_Reserved (16) // Reserved -#define AT91C_ID_17_Reserved (17) // Reserved -#define AT91C_ID_18_Reserved (18) // Reserved -#define AT91C_ID_19_Reserved (19) // Reserved -#define AT91C_ID_20_Reserved (20) // Reserved -#define AT91C_ID_21_Reserved (21) // Reserved -#define AT91C_ID_22_Reserved (22) // Reserved -#define AT91C_ID_23_Reserved (23) // Reserved -#define AT91C_ID_24_Reserved (24) // Reserved -#define AT91C_ID_25_Reserved (25) // Reserved -#define AT91C_ID_26_Reserved (26) // Reserved -#define AT91C_ID_27_Reserved (27) // Reserved -#define AT91C_ID_28_Reserved (28) // Reserved -#define AT91C_ID_29_Reserved (29) // Reserved -#define AT91C_ID_IRQ0 (30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 (31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT (0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYS (0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC (0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU (0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU (0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA (0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR (0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC (0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC (0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC (0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC (0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC (0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG (0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC (0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI (0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI (0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC (0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC (0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC (0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC (0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 (0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 (0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 (0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 (0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI (0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 (0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 (0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 (0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB (0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 (0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 (0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 (0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 (0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC (0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP (0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM (0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE (0x00004000) // Internal SRAM size in byte (16 Kbytes) -// IFLASH -#define AT91C_IFLASH (0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE (0x00010000) // Internal FLASH size in byte (64 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE (128) // Internal FLASH Page Size: 128 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE (4096) // Internal FLASH Lock Region Size: 4 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES (256) // Internal FLASH Number of Pages: 256 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS (8) // Internal FLASH Number of Lock Bits: 8 bytes - - diff --git a/openpcd/firmware/include/old/ioat91sam7s64.ddf b/openpcd/firmware/include/old/ioat91sam7s64.ddf deleted file mode 100644 index a62c9a8..0000000 --- a/openpcd/firmware/include/old/ioat91sam7s64.ddf +++ /dev/null @@ -1,1524 +0,0 @@ -; ----------------------------------------------------------------------------
-; ATMEL Microcontroller Software Support - ROUSSET -
-; ----------------------------------------------------------------------------
-; DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-; IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-; MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-; DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-; INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-; LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-; OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-; LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-; NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-; EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-; ----------------------------------------------------------------------------
-; File Name : AT91SAM7S64.ddf
-; Object : AT91SAM7S64 definitions
-; Generated : AT91 SW Application Group 08/30/2005 (15:53:03)
-;
-; CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005//
-; CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005//
-; CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005//
-; CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005//
-; CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005//
-; CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005//
-; CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005//
-; CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004//
-; CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004//
-; CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004//
-; CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005//
-; CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-; CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005//
-; CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-; CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-; CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-; CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-; CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-; CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-; CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005//
-; CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-; ----------------------------------------------------------------------------
-
-[Sfr]
-
-; ========== Register definition for SYS peripheral ==========
-; ========== Register definition for AIC peripheral ==========
-sfr = "AIC_SMR", "Memory", 0xfffff000, 4, base=16
-sfr = "AIC_SMR.PRIOR", "Memory", 0xfffff000, 4, base=16, bitRange=0-2
-sfr = "AIC_SMR.SRCTYPE", "Memory", 0xfffff000, 4, base=16, bitRange=5-6
-sfr = "AIC_SVR", "Memory", 0xfffff080, 4, base=16
-sfr = "AIC_IVR", "Memory", 0xfffff100, 4, base=16
-sfr = "AIC_FVR", "Memory", 0xfffff104, 4, base=16
-sfr = "AIC_ISR", "Memory", 0xfffff108, 4, base=16
-sfr = "AIC_IPR", "Memory", 0xfffff10c, 4, base=16
-sfr = "AIC_IMR", "Memory", 0xfffff110, 4, base=16
-sfr = "AIC_CISR", "Memory", 0xfffff114, 4, base=16
-sfr = "AIC_CISR.NFIQ", "Memory", 0xfffff114, 4, base=16, bitRange=0
-sfr = "AIC_CISR.NIRQ", "Memory", 0xfffff114, 4, base=16, bitRange=1
-sfr = "AIC_IECR", "Memory", 0xfffff120, 4, base=16
-sfr = "AIC_IDCR", "Memory", 0xfffff124, 4, base=16
-sfr = "AIC_ICCR", "Memory", 0xfffff128, 4, base=16
-sfr = "AIC_ISCR", "Memory", 0xfffff12c, 4, base=16
-sfr = "AIC_EOICR", "Memory", 0xfffff130, 4, base=16
-sfr = "AIC_SPU", "Memory", 0xfffff134, 4, base=16
-sfr = "AIC_DCR", "Memory", 0xfffff138, 4, base=16
-sfr = "AIC_DCR.PROT", "Memory", 0xfffff138, 4, base=16, bitRange=0
-sfr = "AIC_DCR.GMSK", "Memory", 0xfffff138, 4, base=16, bitRange=1
-sfr = "AIC_FFER", "Memory", 0xfffff140, 4, base=16
-sfr = "AIC_FFDR", "Memory", 0xfffff144, 4, base=16
-sfr = "AIC_FFSR", "Memory", 0xfffff148, 4, base=16
-; ========== Register definition for PDC_DBGU peripheral ==========
-sfr = "DBGU_RPR", "Memory", 0xfffff300, 4, base=16
-sfr = "DBGU_RCR", "Memory", 0xfffff304, 4, base=16
-sfr = "DBGU_TPR", "Memory", 0xfffff308, 4, base=16
-sfr = "DBGU_TCR", "Memory", 0xfffff30c, 4, base=16
-sfr = "DBGU_RNPR", "Memory", 0xfffff310, 4, base=16
-sfr = "DBGU_RNCR", "Memory", 0xfffff314, 4, base=16
-sfr = "DBGU_TNPR", "Memory", 0xfffff318, 4, base=16
-sfr = "DBGU_TNCR", "Memory", 0xfffff31c, 4, base=16
-sfr = "DBGU_PTCR", "Memory", 0xfffff320, 4, base=16
-sfr = "DBGU_PTCR.RXTEN", "Memory", 0xfffff320, 4, base=16, bitRange=0
-sfr = "DBGU_PTCR.RXTDIS", "Memory", 0xfffff320, 4, base=16, bitRange=1
-sfr = "DBGU_PTCR.TXTEN", "Memory", 0xfffff320, 4, base=16, bitRange=8
-sfr = "DBGU_PTCR.TXTDIS", "Memory", 0xfffff320, 4, base=16, bitRange=9
-sfr = "DBGU_PTSR", "Memory", 0xfffff324, 4, base=16
-sfr = "DBGU_PTSR.RXTEN", "Memory", 0xfffff324, 4, base=16, bitRange=0
-sfr = "DBGU_PTSR.TXTEN", "Memory", 0xfffff324, 4, base=16, bitRange=8
-; ========== Register definition for DBGU peripheral ==========
-sfr = "DBGU_CR", "Memory", 0xfffff200, 4, base=16
-sfr = "DBGU_CR.RSTRX", "Memory", 0xfffff200, 4, base=16, bitRange=2
-sfr = "DBGU_CR.RSTTX", "Memory", 0xfffff200, 4, base=16, bitRange=3
-sfr = "DBGU_CR.RXEN", "Memory", 0xfffff200, 4, base=16, bitRange=4
-sfr = "DBGU_CR.RXDIS", "Memory", 0xfffff200, 4, base=16, bitRange=5
-sfr = "DBGU_CR.TXEN", "Memory", 0xfffff200, 4, base=16, bitRange=6
-sfr = "DBGU_CR.TXDIS", "Memory", 0xfffff200, 4, base=16, bitRange=7
-sfr = "DBGU_CR.RSTSTA", "Memory", 0xfffff200, 4, base=16, bitRange=8
-sfr = "DBGU_MR", "Memory", 0xfffff204, 4, base=16
-sfr = "DBGU_MR.PAR", "Memory", 0xfffff204, 4, base=16, bitRange=9-11
-sfr = "DBGU_MR.CHMODE", "Memory", 0xfffff204, 4, base=16, bitRange=14-15
-sfr = "DBGU_IER", "Memory", 0xfffff208, 4, base=16
-sfr = "DBGU_IER.RXRDY", "Memory", 0xfffff208, 4, base=16, bitRange=0
-sfr = "DBGU_IER.TXRDY", "Memory", 0xfffff208, 4, base=16, bitRange=1
-sfr = "DBGU_IER.ENDRX", "Memory", 0xfffff208, 4, base=16, bitRange=3
-sfr = "DBGU_IER.ENDTX", "Memory", 0xfffff208, 4, base=16, bitRange=4
-sfr = "DBGU_IER.OVRE", "Memory", 0xfffff208, 4, base=16, bitRange=5
-sfr = "DBGU_IER.FRAME", "Memory", 0xfffff208, 4, base=16, bitRange=6
-sfr = "DBGU_IER.PARE", "Memory", 0xfffff208, 4, base=16, bitRange=7
-sfr = "DBGU_IER.TXEMPTY", "Memory", 0xfffff208, 4, base=16, bitRange=9
-sfr = "DBGU_IER.TXBUFE", "Memory", 0xfffff208, 4, base=16, bitRange=11
-sfr = "DBGU_IER.RXBUFF", "Memory", 0xfffff208, 4, base=16, bitRange=12
-sfr = "DBGU_IER.TX", "Memory", 0xfffff208, 4, base=16, bitRange=30
-sfr = "DBGU_IER.RX", "Memory", 0xfffff208, 4, base=16, bitRange=31
-sfr = "DBGU_IDR", "Memory", 0xfffff20c, 4, base=16
-sfr = "DBGU_IDR.RXRDY", "Memory", 0xfffff20c, 4, base=16, bitRange=0
-sfr = "DBGU_IDR.TXRDY", "Memory", 0xfffff20c, 4, base=16, bitRange=1
-sfr = "DBGU_IDR.ENDRX", "Memory", 0xfffff20c, 4, base=16, bitRange=3
-sfr = "DBGU_IDR.ENDTX", "Memory", 0xfffff20c, 4, base=16, bitRange=4
-sfr = "DBGU_IDR.OVRE", "Memory", 0xfffff20c, 4, base=16, bitRange=5
-sfr = "DBGU_IDR.FRAME", "Memory", 0xfffff20c, 4, base=16, bitRange=6
-sfr = "DBGU_IDR.PARE", "Memory", 0xfffff20c, 4, base=16, bitRange=7
-sfr = "DBGU_IDR.TXEMPTY", "Memory", 0xfffff20c, 4, base=16, bitRange=9
-sfr = "DBGU_IDR.TXBUFE", "Memory", 0xfffff20c, 4, base=16, bitRange=11
-sfr = "DBGU_IDR.RXBUFF", "Memory", 0xfffff20c, 4, base=16, bitRange=12
-sfr = "DBGU_IDR.TX", "Memory", 0xfffff20c, 4, base=16, bitRange=30
-sfr = "DBGU_IDR.RX", "Memory", 0xfffff20c, 4, base=16, bitRange=31
-sfr = "DBGU_IMR", "Memory", 0xfffff210, 4, base=16
-sfr = "DBGU_IMR.RXRDY", "Memory", 0xfffff210, 4, base=16, bitRange=0
-sfr = "DBGU_IMR.TXRDY", "Memory", 0xfffff210, 4, base=16, bitRange=1
-sfr = "DBGU_IMR.ENDRX", "Memory", 0xfffff210, 4, base=16, bitRange=3
-sfr = "DBGU_IMR.ENDTX", "Memory", 0xfffff210, 4, base=16, bitRange=4
-sfr = "DBGU_IMR.OVRE", "Memory", 0xfffff210, 4, base=16, bitRange=5
-sfr = "DBGU_IMR.FRAME", "Memory", 0xfffff210, 4, base=16, bitRange=6
-sfr = "DBGU_IMR.PARE", "Memory", 0xfffff210, 4, base=16, bitRange=7
-sfr = "DBGU_IMR.TXEMPTY", "Memory", 0xfffff210, 4, base=16, bitRange=9
-sfr = "DBGU_IMR.TXBUFE", "Memory", 0xfffff210, 4, base=16, bitRange=11
-sfr = "DBGU_IMR.RXBUFF", "Memory", 0xfffff210, 4, base=16, bitRange=12
-sfr = "DBGU_IMR.TX", "Memory", 0xfffff210, 4, base=16, bitRange=30
-sfr = "DBGU_IMR.RX", "Memory", 0xfffff210, 4, base=16, bitRange=31
-sfr = "DBGU_CSR", "Memory", 0xfffff214, 4, base=16
-sfr = "DBGU_CSR.RXRDY", "Memory", 0xfffff214, 4, base=16, bitRange=0
-sfr = "DBGU_CSR.TXRDY", "Memory", 0xfffff214, 4, base=16, bitRange=1
-sfr = "DBGU_CSR.ENDRX", "Memory", 0xfffff214, 4, base=16, bitRange=3
-sfr = "DBGU_CSR.ENDTX", "Memory", 0xfffff214, 4, base=16, bitRange=4
-sfr = "DBGU_CSR.OVRE", "Memory", 0xfffff214, 4, base=16, bitRange=5
-sfr = "DBGU_CSR.FRAME", "Memory", 0xfffff214, 4, base=16, bitRange=6
-sfr = "DBGU_CSR.PARE", "Memory", 0xfffff214, 4, base=16, bitRange=7
-sfr = "DBGU_CSR.TXEMPTY", "Memory", 0xfffff214, 4, base=16, bitRange=9
-sfr = "DBGU_CSR.TXBUFE", "Memory", 0xfffff214, 4, base=16, bitRange=11
-sfr = "DBGU_CSR.RXBUFF", "Memory", 0xfffff214, 4, base=16, bitRange=12
-sfr = "DBGU_CSR.TX", "Memory", 0xfffff214, 4, base=16, bitRange=30
-sfr = "DBGU_CSR.RX", "Memory", 0xfffff214, 4, base=16, bitRange=31
-sfr = "DBGU_RHR", "Memory", 0xfffff218, 4, base=16
-sfr = "DBGU_THR", "Memory", 0xfffff21c, 4, base=16
-sfr = "DBGU_BRGR", "Memory", 0xfffff220, 4, base=16
-sfr = "DBGU_CIDR", "Memory", 0xfffff240, 4, base=16
-sfr = "DBGU_EXID", "Memory", 0xfffff244, 4, base=16
-sfr = "DBGU_FNTR", "Memory", 0xfffff248, 4, base=16
-sfr = "DBGU_FNTR.NTRST", "Memory", 0xfffff248, 4, base=16, bitRange=0
-; ========== Register definition for PIOA peripheral ==========
-sfr = "PIOA_PER", "Memory", 0xfffff400, 4, base=16
-sfr = "PIOA_PDR", "Memory", 0xfffff404, 4, base=16
-sfr = "PIOA_PSR", "Memory", 0xfffff408, 4, base=16
-sfr = "PIOA_OER", "Memory", 0xfffff410, 4, base=16
-sfr = "PIOA_ODR", "Memory", 0xfffff414, 4, base=16
-sfr = "PIOA_OSR", "Memory", 0xfffff418, 4, base=16
-sfr = "PIOA_IFER", "Memory", 0xfffff420, 4, base=16
-sfr = "PIOA_IFDR", "Memory", 0xfffff424, 4, base=16
-sfr = "PIOA_IFSR", "Memory", 0xfffff428, 4, base=16
-sfr = "PIOA_SODR", "Memory", 0xfffff430, 4, base=16
-sfr = "PIOA_CODR", "Memory", 0xfffff434, 4, base=16
-sfr = "PIOA_ODSR", "Memory", 0xfffff438, 4, base=16
-sfr = "PIOA_PDSR", "Memory", 0xfffff43c, 4, base=16
-sfr = "PIOA_IER", "Memory", 0xfffff440, 4, base=16
-sfr = "PIOA_IDR", "Memory", 0xfffff444, 4, base=16
-sfr = "PIOA_IMR", "Memory", 0xfffff448, 4, base=16
-sfr = "PIOA_ISR", "Memory", 0xfffff44c, 4, base=16
-sfr = "PIOA_MDER", "Memory", 0xfffff450, 4, base=16
-sfr = "PIOA_MDDR", "Memory", 0xfffff454, 4, base=16
-sfr = "PIOA_MDSR", "Memory", 0xfffff458, 4, base=16
-sfr = "PIOA_PPUDR", "Memory", 0xfffff460, 4, base=16
-sfr = "PIOA_PPUER", "Memory", 0xfffff464, 4, base=16
-sfr = "PIOA_PPUSR", "Memory", 0xfffff468, 4, base=16
-sfr = "PIOA_ASR", "Memory", 0xfffff470, 4, base=16
-sfr = "PIOA_BSR", "Memory", 0xfffff474, 4, base=16
-sfr = "PIOA_ABSR", "Memory", 0xfffff478, 4, base=16
-sfr = "PIOA_OWER", "Memory", 0xfffff4a0, 4, base=16
-sfr = "PIOA_OWDR", "Memory", 0xfffff4a4, 4, base=16
-sfr = "PIOA_OWSR", "Memory", 0xfffff4a8, 4, base=16
-; ========== Register definition for CKGR peripheral ==========
-sfr = "CKGR_MOR", "Memory", 0xfffffc20, 4, base=16
-sfr = "CKGR_MOR.MOSCEN", "Memory", 0xfffffc20, 4, base=16, bitRange=0
-sfr = "CKGR_MOR.OSCBYPASS", "Memory", 0xfffffc20, 4, base=16, bitRange=1
-sfr = "CKGR_MOR.OSCOUNT", "Memory", 0xfffffc20, 4, base=16, bitRange=8-15
-sfr = "CKGR_MCFR", "Memory", 0xfffffc24, 4, base=16
-sfr = "CKGR_MCFR.MAINF", "Memory", 0xfffffc24, 4, base=16, bitRange=0-15
-sfr = "CKGR_MCFR.MAINRDY", "Memory", 0xfffffc24, 4, base=16, bitRange=16
-sfr = "CKGR_PLLR", "Memory", 0xfffffc2c, 4, base=16
-sfr = "CKGR_PLLR.DIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=0-7
-sfr = "CKGR_PLLR.PLLCOUNT", "Memory", 0xfffffc2c, 4, base=16, bitRange=8-13
-sfr = "CKGR_PLLR.OUT", "Memory", 0xfffffc2c, 4, base=16, bitRange=14-15
-sfr = "CKGR_PLLR.MUL", "Memory", 0xfffffc2c, 4, base=16, bitRange=16-26
-sfr = "CKGR_PLLR.USBDIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=28-29
-; ========== Register definition for PMC peripheral ==========
-sfr = "PMC_SCER", "Memory", 0xfffffc00, 4, base=16
-sfr = "PMC_SCER.PCK", "Memory", 0xfffffc00, 4, base=16, bitRange=0
-sfr = "PMC_SCER.UDP", "Memory", 0xfffffc00, 4, base=16, bitRange=7
-sfr = "PMC_SCER.PCK0", "Memory", 0xfffffc00, 4, base=16, bitRange=8
-sfr = "PMC_SCER.PCK1", "Memory", 0xfffffc00, 4, base=16, bitRange=9
-sfr = "PMC_SCER.PCK2", "Memory", 0xfffffc00, 4, base=16, bitRange=10
-sfr = "PMC_SCDR", "Memory", 0xfffffc04, 4, base=16
-sfr = "PMC_SCDR.PCK", "Memory", 0xfffffc04, 4, base=16, bitRange=0
-sfr = "PMC_SCDR.UDP", "Memory", 0xfffffc04, 4, base=16, bitRange=7
-sfr = "PMC_SCDR.PCK0", "Memory", 0xfffffc04, 4, base=16, bitRange=8
-sfr = "PMC_SCDR.PCK1", "Memory", 0xfffffc04, 4, base=16, bitRange=9
-sfr = "PMC_SCDR.PCK2", "Memory", 0xfffffc04, 4, base=16, bitRange=10
-sfr = "PMC_SCSR", "Memory", 0xfffffc08, 4, base=16
-sfr = "PMC_SCSR.PCK", "Memory", 0xfffffc08, 4, base=16, bitRange=0
-sfr = "PMC_SCSR.UDP", "Memory", 0xfffffc08, 4, base=16, bitRange=7
-sfr = "PMC_SCSR.PCK0", "Memory", 0xfffffc08, 4, base=16, bitRange=8
-sfr = "PMC_SCSR.PCK1", "Memory", 0xfffffc08, 4, base=16, bitRange=9
-sfr = "PMC_SCSR.PCK2", "Memory", 0xfffffc08, 4, base=16, bitRange=10
-sfr = "PMC_PCER", "Memory", 0xfffffc10, 4, base=16
-sfr = "PMC_PCDR", "Memory", 0xfffffc14, 4, base=16
-sfr = "PMC_PCSR", "Memory", 0xfffffc18, 4, base=16
-sfr = "PMC_MOR", "Memory", 0xfffffc20, 4, base=16
-sfr = "PMC_MOR.MOSCEN", "Memory", 0xfffffc20, 4, base=16, bitRange=0
-sfr = "PMC_MOR.OSCBYPASS", "Memory", 0xfffffc20, 4, base=16, bitRange=1
-sfr = "PMC_MOR.OSCOUNT", "Memory", 0xfffffc20, 4, base=16, bitRange=8-15
-sfr = "PMC_MCFR", "Memory", 0xfffffc24, 4, base=16
-sfr = "PMC_MCFR.MAINF", "Memory", 0xfffffc24, 4, base=16, bitRange=0-15
-sfr = "PMC_MCFR.MAINRDY", "Memory", 0xfffffc24, 4, base=16, bitRange=16
-sfr = "PMC_PLLR", "Memory", 0xfffffc2c, 4, base=16
-sfr = "PMC_PLLR.DIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=0-7
-sfr = "PMC_PLLR.PLLCOUNT", "Memory", 0xfffffc2c, 4, base=16, bitRange=8-13
-sfr = "PMC_PLLR.OUT", "Memory", 0xfffffc2c, 4, base=16, bitRange=14-15
-sfr = "PMC_PLLR.MUL", "Memory", 0xfffffc2c, 4, base=16, bitRange=16-26
-sfr = "PMC_PLLR.USBDIV", "Memory", 0xfffffc2c, 4, base=16, bitRange=28-29
-sfr = "PMC_MCKR", "Memory", 0xfffffc30, 4, base=16
-sfr = "PMC_MCKR.CSS", "Memory", 0xfffffc30, 4, base=16, bitRange=0-1
-sfr = "PMC_MCKR.PRES", "Memory", 0xfffffc30, 4, base=16, bitRange=2-4
-sfr = "PMC_PCKR", "Memory", 0xfffffc40, 4, base=16
-sfr = "PMC_PCKR.CSS", "Memory", 0xfffffc40, 4, base=16, bitRange=0-1
-sfr = "PMC_PCKR.PRES", "Memory", 0xfffffc40, 4, base=16, bitRange=2-4
-sfr = "PMC_IER", "Memory", 0xfffffc60, 4, base=16
-sfr = "PMC_IER.MOSCS", "Memory", 0xfffffc60, 4, base=16, bitRange=0
-sfr = "PMC_IER.LOCK", "Memory", 0xfffffc60, 4, base=16, bitRange=2
-sfr = "PMC_IER.MCKRDY", "Memory", 0xfffffc60, 4, base=16, bitRange=3
-sfr = "PMC_IER.PCK0RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=8
-sfr = "PMC_IER.PCK1RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=9
-sfr = "PMC_IER.PCK2RDY", "Memory", 0xfffffc60, 4, base=16, bitRange=10
-sfr = "PMC_IDR", "Memory", 0xfffffc64, 4, base=16
-sfr = "PMC_IDR.MOSCS", "Memory", 0xfffffc64, 4, base=16, bitRange=0
-sfr = "PMC_IDR.LOCK", "Memory", 0xfffffc64, 4, base=16, bitRange=2
-sfr = "PMC_IDR.MCKRDY", "Memory", 0xfffffc64, 4, base=16, bitRange=3
-sfr = "PMC_IDR.PCK0RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=8
-sfr = "PMC_IDR.PCK1RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=9
-sfr = "PMC_IDR.PCK2RDY", "Memory", 0xfffffc64, 4, base=16, bitRange=10
-sfr = "PMC_SR", "Memory", 0xfffffc68, 4, base=16
-sfr = "PMC_SR.MOSCS", "Memory", 0xfffffc68, 4, base=16, bitRange=0
-sfr = "PMC_SR.LOCK", "Memory", 0xfffffc68, 4, base=16, bitRange=2
-sfr = "PMC_SR.MCKRDY", "Memory", 0xfffffc68, 4, base=16, bitRange=3
-sfr = "PMC_SR.PCK0RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=8
-sfr = "PMC_SR.PCK1RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=9
-sfr = "PMC_SR.PCK2RDY", "Memory", 0xfffffc68, 4, base=16, bitRange=10
-sfr = "PMC_IMR", "Memory", 0xfffffc6c, 4, base=16
-sfr = "PMC_IMR.MOSCS", "Memory", 0xfffffc6c, 4, base=16, bitRange=0
-sfr = "PMC_IMR.LOCK", "Memory", 0xfffffc6c, 4, base=16, bitRange=2
-sfr = "PMC_IMR.MCKRDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=3
-sfr = "PMC_IMR.PCK0RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=8
-sfr = "PMC_IMR.PCK1RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=9
-sfr = "PMC_IMR.PCK2RDY", "Memory", 0xfffffc6c, 4, base=16, bitRange=10
-; ========== Register definition for RSTC peripheral ==========
-sfr = "RSTC_RCR", "Memory", 0xfffffd00, 4, base=16
-sfr = "RSTC_RCR.PROCRST", "Memory", 0xfffffd00, 4, base=16, bitRange=0
-sfr = "RSTC_RCR.PERRST", "Memory", 0xfffffd00, 4, base=16, bitRange=2
-sfr = "RSTC_RCR.EXTRST", "Memory", 0xfffffd00, 4, base=16, bitRange=3
-sfr = "RSTC_RCR.KEY", "Memory", 0xfffffd00, 4, base=16, bitRange=24-31
-sfr = "RSTC_RSR", "Memory", 0xfffffd04, 4, base=16
-sfr = "RSTC_RSR.URSTS", "Memory", 0xfffffd04, 4, base=16, bitRange=0
-sfr = "RSTC_RSR.BODSTS", "Memory", 0xfffffd04, 4, base=16, bitRange=1
-sfr = "RSTC_RSR.RSTTYP", "Memory", 0xfffffd04, 4, base=16, bitRange=8-10
-sfr = "RSTC_RSR.NRSTL", "Memory", 0xfffffd04, 4, base=16, bitRange=16
-sfr = "RSTC_RSR.SRCMP", "Memory", 0xfffffd04, 4, base=16, bitRange=17
-sfr = "RSTC_RMR", "Memory", 0xfffffd08, 4, base=16
-sfr = "RSTC_RMR.URSTEN", "Memory", 0xfffffd08, 4, base=16, bitRange=0
-sfr = "RSTC_RMR.URSTIEN", "Memory", 0xfffffd08, 4, base=16, bitRange=4
-sfr = "RSTC_RMR.ERSTL", "Memory", 0xfffffd08, 4, base=16, bitRange=8-11
-sfr = "RSTC_RMR.BODIEN", "Memory", 0xfffffd08, 4, base=16, bitRange=16
-sfr = "RSTC_RMR.KEY", "Memory", 0xfffffd08, 4, base=16, bitRange=24-31
-; ========== Register definition for RTTC peripheral ==========
-sfr = "RTTC_RTMR", "Memory", 0xfffffd20, 4, base=16
-sfr = "RTTC_RTMR.RTPRES", "Memory", 0xfffffd20, 4, base=16, bitRange=0-15
-sfr = "RTTC_RTMR.ALMIEN", "Memory", 0xfffffd20, 4, base=16, bitRange=16
-sfr = "RTTC_RTMR.RTTINCIEN", "Memory", 0xfffffd20, 4, base=16, bitRange=17
-sfr = "RTTC_RTMR.RTTRST", "Memory", 0xfffffd20, 4, base=16, bitRange=18
-sfr = "RTTC_RTAR", "Memory", 0xfffffd24, 4, base=16
-sfr = "RTTC_RTAR.ALMV", "Memory", 0xfffffd24, 4, base=16, bitRange=0-31
-sfr = "RTTC_RTVR", "Memory", 0xfffffd28, 4, base=16
-sfr = "RTTC_RTVR.CRTV", "Memory", 0xfffffd28, 4, base=16, bitRange=0-31
-sfr = "RTTC_RTSR", "Memory", 0xfffffd2c, 4, base=16
-sfr = "RTTC_RTSR.ALMS", "Memory", 0xfffffd2c, 4, base=16, bitRange=0
-sfr = "RTTC_RTSR.RTTINC", "Memory", 0xfffffd2c, 4, base=16, bitRange=1
-; ========== Register definition for PITC peripheral ==========
-sfr = "PITC_PIMR", "Memory", 0xfffffd30, 4, base=16
-sfr = "PITC_PIMR.PIV", "Memory", 0xfffffd30, 4, base=16, bitRange=0-19
-sfr = "PITC_PIMR.PITEN", "Memory", 0xfffffd30, 4, base=16, bitRange=24
-sfr = "PITC_PIMR.PITIEN", "Memory", 0xfffffd30, 4, base=16, bitRange=25
-sfr = "PITC_PISR", "Memory", 0xfffffd34, 4, base=16
-sfr = "PITC_PISR.PITS", "Memory", 0xfffffd34, 4, base=16, bitRange=0
-sfr = "PITC_PIVR", "Memory", 0xfffffd38, 4, base=16
-sfr = "PITC_PIVR.CPIV", "Memory", 0xfffffd38, 4, base=16, bitRange=0-19
-sfr = "PITC_PIVR.PICNT", "Memory", 0xfffffd38, 4, base=16, bitRange=20-31
-sfr = "PITC_PIIR", "Memory", 0xfffffd3c, 4, base=16
-sfr = "PITC_PIIR.CPIV", "Memory", 0xfffffd3c, 4, base=16, bitRange=0-19
-sfr = "PITC_PIIR.PICNT", "Memory", 0xfffffd3c, 4, base=16, bitRange=20-31
-; ========== Register definition for WDTC peripheral ==========
-sfr = "WDTC_WDCR", "Memory", 0xfffffd40, 4, base=16
-sfr = "WDTC_WDCR.WDRSTT", "Memory", 0xfffffd40, 4, base=16, bitRange=0
-sfr = "WDTC_WDCR.KEY", "Memory", 0xfffffd40, 4, base=16, bitRange=24-31
-sfr = "WDTC_WDMR", "Memory", 0xfffffd44, 4, base=16
-sfr = "WDTC_WDMR.WDV", "Memory", 0xfffffd44, 4, base=16, bitRange=0-11
-sfr = "WDTC_WDMR.WDFIEN", "Memory", 0xfffffd44, 4, base=16, bitRange=12
-sfr = "WDTC_WDMR.WDRSTEN", "Memory", 0xfffffd44, 4, base=16, bitRange=13
-sfr = "WDTC_WDMR.WDRPROC", "Memory", 0xfffffd44, 4, base=16, bitRange=14
-sfr = "WDTC_WDMR.WDDIS", "Memory", 0xfffffd44, 4, base=16, bitRange=15
-sfr = "WDTC_WDMR.WDD", "Memory", 0xfffffd44, 4, base=16, bitRange=16-27
-sfr = "WDTC_WDMR.WDDBGHLT", "Memory", 0xfffffd44, 4, base=16, bitRange=28
-sfr = "WDTC_WDMR.WDIDLEHLT", "Memory", 0xfffffd44, 4, base=16, bitRange=29
-sfr = "WDTC_WDSR", "Memory", 0xfffffd48, 4, base=16
-sfr = "WDTC_WDSR.WDUNF", "Memory", 0xfffffd48, 4, base=16, bitRange=0
-sfr = "WDTC_WDSR.WDERR", "Memory", 0xfffffd48, 4, base=16, bitRange=1
-; ========== Register definition for VREG peripheral ==========
-sfr = "VREG_MR", "Memory", 0xfffffd60, 4, base=16
-sfr = "VREG_MR.PSTDBY", "Memory", 0xfffffd60, 4, base=16, bitRange=0
-; ========== Register definition for MC peripheral ==========
-sfr = "MC_RCR", "Memory", 0xffffff00, 4, base=16
-sfr = "MC_RCR.RCB", "Memory", 0xffffff00, 4, base=16, bitRange=0
-sfr = "MC_ASR", "Memory", 0xffffff04, 4, base=16
-sfr = "MC_ASR.UNDADD", "Memory", 0xffffff04, 4, base=16, bitRange=0
-sfr = "MC_ASR.MISADD", "Memory", 0xffffff04, 4, base=16, bitRange=1
-sfr = "MC_ASR.ABTSZ", "Memory", 0xffffff04, 4, base=16, bitRange=8-9
-sfr = "MC_ASR.ABTTYP", "Memory", 0xffffff04, 4, base=16, bitRange=10-11
-sfr = "MC_ASR.MST0", "Memory", 0xffffff04, 4, base=16, bitRange=16
-sfr = "MC_ASR.MST1", "Memory", 0xffffff04, 4, base=16, bitRange=17
-sfr = "MC_ASR.SVMST0", "Memory", 0xffffff04, 4, base=16, bitRange=24
-sfr = "MC_ASR.SVMST1", "Memory", 0xffffff04, 4, base=16, bitRange=25
-sfr = "MC_AASR", "Memory", 0xffffff08, 4, base=16
-sfr = "MC_FMR", "Memory", 0xffffff60, 4, base=16
-sfr = "MC_FMR.FRDY", "Memory", 0xffffff60, 4, base=16, bitRange=0
-sfr = "MC_FMR.LOCKE", "Memory", 0xffffff60, 4, base=16, bitRange=2
-sfr = "MC_FMR.PROGE", "Memory", 0xffffff60, 4, base=16, bitRange=3
-sfr = "MC_FMR.NEBP", "Memory", 0xffffff60, 4, base=16, bitRange=7
-sfr = "MC_FMR.FWS", "Memory", 0xffffff60, 4, base=16, bitRange=8-9
-sfr = "MC_FMR.FMCN", "Memory", 0xffffff60, 4, base=16, bitRange=16-23
-sfr = "MC_FCR", "Memory", 0xffffff64, 4, base=16
-sfr = "MC_FCR.FCMD", "Memory", 0xffffff64, 4, base=16, bitRange=0-3
-sfr = "MC_FCR.PAGEN", "Memory", 0xffffff64, 4, base=16, bitRange=8-17
-sfr = "MC_FCR.KEY", "Memory", 0xffffff64, 4, base=16, bitRange=24-31
-sfr = "MC_FSR", "Memory", 0xffffff68, 4, base=16
-sfr = "MC_FSR.FRDY", "Memory", 0xffffff68, 4, base=16, bitRange=0
-sfr = "MC_FSR.LOCKE", "Memory", 0xffffff68, 4, base=16, bitRange=2
-sfr = "MC_FSR.PROGE", "Memory", 0xffffff68, 4, base=16, bitRange=3
-sfr = "MC_FSR.SECURITY", "Memory", 0xffffff68, 4, base=16, bitRange=4
-sfr = "MC_FSR.GPNVM0", "Memory", 0xffffff68, 4, base=16, bitRange=8
-sfr = "MC_FSR.GPNVM1", "Memory", 0xffffff68, 4, base=16, bitRange=9
-sfr = "MC_FSR.GPNVM2", "Memory", 0xffffff68, 4, base=16, bitRange=10
-sfr = "MC_FSR.GPNVM3", "Memory", 0xffffff68, 4, base=16, bitRange=11
-sfr = "MC_FSR.GPNVM4", "Memory", 0xffffff68, 4, base=16, bitRange=12
-sfr = "MC_FSR.GPNVM5", "Memory", 0xffffff68, 4, base=16, bitRange=13
-sfr = "MC_FSR.GPNVM6", "Memory", 0xffffff68, 4, base=16, bitRange=14
-sfr = "MC_FSR.GPNVM7", "Memory", 0xffffff68, 4, base=16, bitRange=15
-sfr = "MC_FSR.LOCKS0", "Memory", 0xffffff68, 4, base=16, bitRange=16
-sfr = "MC_FSR.LOCKS1", "Memory", 0xffffff68, 4, base=16, bitRange=17
-sfr = "MC_FSR.LOCKS2", "Memory", 0xffffff68, 4, base=16, bitRange=18
-sfr = "MC_FSR.LOCKS3", "Memory", 0xffffff68, 4, base=16, bitRange=19
-sfr = "MC_FSR.LOCKS4", "Memory", 0xffffff68, 4, base=16, bitRange=20
-sfr = "MC_FSR.LOCKS5", "Memory", 0xffffff68, 4, base=16, bitRange=21
-sfr = "MC_FSR.LOCKS6", "Memory", 0xffffff68, 4, base=16, bitRange=22
-sfr = "MC_FSR.LOCKS7", "Memory", 0xffffff68, 4, base=16, bitRange=23
-sfr = "MC_FSR.LOCKS8", "Memory", 0xffffff68, 4, base=16, bitRange=24
-sfr = "MC_FSR.LOCKS9", "Memory", 0xffffff68, 4, base=16, bitRange=25
-sfr = "MC_FSR.LOCKS10", "Memory", 0xffffff68, 4, base=16, bitRange=26
-sfr = "MC_FSR.LOCKS11", "Memory", 0xffffff68, 4, base=16, bitRange=27
-sfr = "MC_FSR.LOCKS12", "Memory", 0xffffff68, 4, base=16, bitRange=28
-sfr = "MC_FSR.LOCKS13", "Memory", 0xffffff68, 4, base=16, bitRange=29
-sfr = "MC_FSR.LOCKS14", "Memory", 0xffffff68, 4, base=16, bitRange=30
-sfr = "MC_FSR.LOCKS15", "Memory", 0xffffff68, 4, base=16, bitRange=31
-; ========== Register definition for PDC_SPI peripheral ==========
-sfr = "SPI_RPR", "Memory", 0xfffe0100, 4, base=16
-sfr = "SPI_RCR", "Memory", 0xfffe0104, 4, base=16
-sfr = "SPI_TPR", "Memory", 0xfffe0108, 4, base=16
-sfr = "SPI_TCR", "Memory", 0xfffe010c, 4, base=16
-sfr = "SPI_RNPR", "Memory", 0xfffe0110, 4, base=16
-sfr = "SPI_RNCR", "Memory", 0xfffe0114, 4, base=16
-sfr = "SPI_TNPR", "Memory", 0xfffe0118, 4, base=16
-sfr = "SPI_TNCR", "Memory", 0xfffe011c, 4, base=16
-sfr = "SPI_PTCR", "Memory", 0xfffe0120, 4, base=16
-sfr = "SPI_PTCR.RXTEN", "Memory", 0xfffe0120, 4, base=16, bitRange=0
-sfr = "SPI_PTCR.RXTDIS", "Memory", 0xfffe0120, 4, base=16, bitRange=1
-sfr = "SPI_PTCR.TXTEN", "Memory", 0xfffe0120, 4, base=16, bitRange=8
-sfr = "SPI_PTCR.TXTDIS", "Memory", 0xfffe0120, 4, base=16, bitRange=9
-sfr = "SPI_PTSR", "Memory", 0xfffe0124, 4, base=16
-sfr = "SPI_PTSR.RXTEN", "Memory", 0xfffe0124, 4, base=16, bitRange=0
-sfr = "SPI_PTSR.TXTEN", "Memory", 0xfffe0124, 4, base=16, bitRange=8
-; ========== Register definition for SPI peripheral ==========
-sfr = "SPI_CR", "Memory", 0xfffe0000, 4, base=16
-sfr = "SPI_CR.SPIEN", "Memory", 0xfffe0000, 4, base=16, bitRange=0
-sfr = "SPI_CR.SPIDIS", "Memory", 0xfffe0000, 4, base=16, bitRange=1
-sfr = "SPI_CR.SWRST", "Memory", 0xfffe0000, 4, base=16, bitRange=7
-sfr = "SPI_CR.LASTXFER", "Memory", 0xfffe0000, 4, base=16, bitRange=24
-sfr = "SPI_MR", "Memory", 0xfffe0004, 4, base=16
-sfr = "SPI_MR.MSTR", "Memory", 0xfffe0004, 4, base=16, bitRange=0
-sfr = "SPI_MR.PS", "Memory", 0xfffe0004, 4, base=16, bitRange=1
-sfr = "SPI_MR.PCSDEC", "Memory", 0xfffe0004, 4, base=16, bitRange=2
-sfr = "SPI_MR.FDIV", "Memory", 0xfffe0004, 4, base=16, bitRange=3
-sfr = "SPI_MR.MODFDIS", "Memory", 0xfffe0004, 4, base=16, bitRange=4
-sfr = "SPI_MR.LLB", "Memory", 0xfffe0004, 4, base=16, bitRange=7
-sfr = "SPI_MR.PCS", "Memory", 0xfffe0004, 4, base=16, bitRange=16-19
-sfr = "SPI_MR.DLYBCS", "Memory", 0xfffe0004, 4, base=16, bitRange=24-31
-sfr = "SPI_RDR", "Memory", 0xfffe0008, 4, base=16
-sfr = "SPI_RDR.RD", "Memory", 0xfffe0008, 4, base=16, bitRange=0-15
-sfr = "SPI_RDR.RPCS", "Memory", 0xfffe0008, 4, base=16, bitRange=16-19
-sfr = "SPI_TDR", "Memory", 0xfffe000c, 4, base=16
-sfr = "SPI_TDR.TD", "Memory", 0xfffe000c, 4, base=16, bitRange=0-15
-sfr = "SPI_TDR.TPCS", "Memory", 0xfffe000c, 4, base=16, bitRange=16-19
-sfr = "SPI_TDR.LASTXFER", "Memory", 0xfffe000c, 4, base=16, bitRange=24
-sfr = "SPI_SR", "Memory", 0xfffe0010, 4, base=16
-sfr = "SPI_SR.RDRF", "Memory", 0xfffe0010, 4, base=16, bitRange=0
-sfr = "SPI_SR.TDRE", "Memory", 0xfffe0010, 4, base=16, bitRange=1
-sfr = "SPI_SR.MODF", "Memory", 0xfffe0010, 4, base=16, bitRange=2
-sfr = "SPI_SR.OVRES", "Memory", 0xfffe0010, 4, base=16, bitRange=3
-sfr = "SPI_SR.ENDRX", "Memory", 0xfffe0010, 4, base=16, bitRange=4
-sfr = "SPI_SR.ENDTX", "Memory", 0xfffe0010, 4, base=16, bitRange=5
-sfr = "SPI_SR.RXBUFF", "Memory", 0xfffe0010, 4, base=16, bitRange=6
-sfr = "SPI_SR.TXBUFE", "Memory", 0xfffe0010, 4, base=16, bitRange=7
-sfr = "SPI_SR.NSSR", "Memory", 0xfffe0010, 4, base=16, bitRange=8
-sfr = "SPI_SR.TXEMPTY", "Memory", 0xfffe0010, 4, base=16, bitRange=9
-sfr = "SPI_SR.SPIENS", "Memory", 0xfffe0010, 4, base=16, bitRange=16
-sfr = "SPI_IER", "Memory", 0xfffe0014, 4, base=16
-sfr = "SPI_IER.RDRF", "Memory", 0xfffe0014, 4, base=16, bitRange=0
-sfr = "SPI_IER.TDRE", "Memory", 0xfffe0014, 4, base=16, bitRange=1
-sfr = "SPI_IER.MODF", "Memory", 0xfffe0014, 4, base=16, bitRange=2
-sfr = "SPI_IER.OVRES", "Memory", 0xfffe0014, 4, base=16, bitRange=3
-sfr = "SPI_IER.ENDRX", "Memory", 0xfffe0014, 4, base=16, bitRange=4
-sfr = "SPI_IER.ENDTX", "Memory", 0xfffe0014, 4, base=16, bitRange=5
-sfr = "SPI_IER.RXBUFF", "Memory", 0xfffe0014, 4, base=16, bitRange=6
-sfr = "SPI_IER.TXBUFE", "Memory", 0xfffe0014, 4, base=16, bitRange=7
-sfr = "SPI_IER.NSSR", "Memory", 0xfffe0014, 4, base=16, bitRange=8
-sfr = "SPI_IER.TXEMPTY", "Memory", 0xfffe0014, 4, base=16, bitRange=9
-sfr = "SPI_IDR", "Memory", 0xfffe0018, 4, base=16
-sfr = "SPI_IDR.RDRF", "Memory", 0xfffe0018, 4, base=16, bitRange=0
-sfr = "SPI_IDR.TDRE", "Memory", 0xfffe0018, 4, base=16, bitRange=1
-sfr = "SPI_IDR.MODF", "Memory", 0xfffe0018, 4, base=16, bitRange=2
-sfr = "SPI_IDR.OVRES", "Memory", 0xfffe0018, 4, base=16, bitRange=3
-sfr = "SPI_IDR.ENDRX", "Memory", 0xfffe0018, 4, base=16, bitRange=4
-sfr = "SPI_IDR.ENDTX", "Memory", 0xfffe0018, 4, base=16, bitRange=5
-sfr = "SPI_IDR.RXBUFF", "Memory", 0xfffe0018, 4, base=16, bitRange=6
-sfr = "SPI_IDR.TXBUFE", "Memory", 0xfffe0018, 4, base=16, bitRange=7
-sfr = "SPI_IDR.NSSR", "Memory", 0xfffe0018, 4, base=16, bitRange=8
-sfr = "SPI_IDR.TXEMPTY", "Memory", 0xfffe0018, 4, base=16, bitRange=9
-sfr = "SPI_IMR", "Memory", 0xfffe001c, 4, base=16
-sfr = "SPI_IMR.RDRF", "Memory", 0xfffe001c, 4, base=16, bitRange=0
-sfr = "SPI_IMR.TDRE", "Memory", 0xfffe001c, 4, base=16, bitRange=1
-sfr = "SPI_IMR.MODF", "Memory", 0xfffe001c, 4, base=16, bitRange=2
-sfr = "SPI_IMR.OVRES", "Memory", 0xfffe001c, 4, base=16, bitRange=3
-sfr = "SPI_IMR.ENDRX", "Memory", 0xfffe001c, 4, base=16, bitRange=4
-sfr = "SPI_IMR.ENDTX", "Memory", 0xfffe001c, 4, base=16, bitRange=5
-sfr = "SPI_IMR.RXBUFF", "Memory", 0xfffe001c, 4, base=16, bitRange=6
-sfr = "SPI_IMR.TXBUFE", "Memory", 0xfffe001c, 4, base=16, bitRange=7
-sfr = "SPI_IMR.NSSR", "Memory", 0xfffe001c, 4, base=16, bitRange=8
-sfr = "SPI_IMR.TXEMPTY", "Memory", 0xfffe001c, 4, base=16, bitRange=9
-sfr = "SPI_CSR", "Memory", 0xfffe0030, 4, base=16
-sfr = "SPI_CSR.CPOL", "Memory", 0xfffe0030, 4, base=16, bitRange=0
-sfr = "SPI_CSR.NCPHA", "Memory", 0xfffe0030, 4, base=16, bitRange=1
-sfr = "SPI_CSR.CSAAT", "Memory", 0xfffe0030, 4, base=16, bitRange=3
-sfr = "SPI_CSR.BITS", "Memory", 0xfffe0030, 4, base=16, bitRange=4-7
-sfr = "SPI_CSR.SCBR", "Memory", 0xfffe0030, 4, base=16, bitRange=8-15
-sfr = "SPI_CSR.DLYBS", "Memory", 0xfffe0030, 4, base=16, bitRange=16-23
-sfr = "SPI_CSR.DLYBCT", "Memory", 0xfffe0030, 4, base=16, bitRange=24-31
-; ========== Register definition for PDC_ADC peripheral ==========
-sfr = "ADC_RPR", "Memory", 0xfffd8100, 4, base=16
-sfr = "ADC_RCR", "Memory", 0xfffd8104, 4, base=16
-sfr = "ADC_TPR", "Memory", 0xfffd8108, 4, base=16
-sfr = "ADC_TCR", "Memory", 0xfffd810c, 4, base=16
-sfr = "ADC_RNPR", "Memory", 0xfffd8110, 4, base=16
-sfr = "ADC_RNCR", "Memory", 0xfffd8114, 4, base=16
-sfr = "ADC_TNPR", "Memory", 0xfffd8118, 4, base=16
-sfr = "ADC_TNCR", "Memory", 0xfffd811c, 4, base=16
-sfr = "ADC_PTCR", "Memory", 0xfffd8120, 4, base=16
-sfr = "ADC_PTCR.RXTEN", "Memory", 0xfffd8120, 4, base=16, bitRange=0
-sfr = "ADC_PTCR.RXTDIS", "Memory", 0xfffd8120, 4, base=16, bitRange=1
-sfr = "ADC_PTCR.TXTEN", "Memory", 0xfffd8120, 4, base=16, bitRange=8
-sfr = "ADC_PTCR.TXTDIS", "Memory", 0xfffd8120, 4, base=16, bitRange=9
-sfr = "ADC_PTSR", "Memory", 0xfffd8124, 4, base=16
-sfr = "ADC_PTSR.RXTEN", "Memory", 0xfffd8124, 4, base=16, bitRange=0
-sfr = "ADC_PTSR.TXTEN", "Memory", 0xfffd8124, 4, base=16, bitRange=8
-; ========== Register definition for ADC peripheral ==========
-sfr = "ADC_CR", "Memory", 0xfffd8000, 4, base=16
-sfr = "ADC_CR.SWRST", "Memory", 0xfffd8000, 4, base=16, bitRange=0
-sfr = "ADC_CR.START", "Memory", 0xfffd8000, 4, base=16, bitRange=1
-sfr = "ADC_MR", "Memory", 0xfffd8004, 4, base=16
-sfr = "ADC_MR.TRGEN", "Memory", 0xfffd8004, 4, base=16, bitRange=0
-sfr = "ADC_MR.TRGSEL", "Memory", 0xfffd8004, 4, base=16, bitRange=1-3
-sfr = "ADC_MR.LOWRES", "Memory", 0xfffd8004, 4, base=16, bitRange=4
-sfr = "ADC_MR.SLEEP", "Memory", 0xfffd8004, 4, base=16, bitRange=5
-sfr = "ADC_MR.PRESCAL", "Memory", 0xfffd8004, 4, base=16, bitRange=8-13
-sfr = "ADC_MR.STARTUP", "Memory", 0xfffd8004, 4, base=16, bitRange=16-20
-sfr = "ADC_MR.SHTIM", "Memory", 0xfffd8004, 4, base=16, bitRange=24-27
-sfr = "ADC_CHER", "Memory", 0xfffd8010, 4, base=16
-sfr = "ADC_CHER.CH0", "Memory", 0xfffd8010, 4, base=16, bitRange=0
-sfr = "ADC_CHER.CH1", "Memory", 0xfffd8010, 4, base=16, bitRange=1
-sfr = "ADC_CHER.CH2", "Memory", 0xfffd8010, 4, base=16, bitRange=2
-sfr = "ADC_CHER.CH3", "Memory", 0xfffd8010, 4, base=16, bitRange=3
-sfr = "ADC_CHER.CH4", "Memory", 0xfffd8010, 4, base=16, bitRange=4
-sfr = "ADC_CHER.CH5", "Memory", 0xfffd8010, 4, base=16, bitRange=5
-sfr = "ADC_CHER.CH6", "Memory", 0xfffd8010, 4, base=16, bitRange=6
-sfr = "ADC_CHER.CH7", "Memory", 0xfffd8010, 4, base=16, bitRange=7
-sfr = "ADC_CHDR", "Memory", 0xfffd8014, 4, base=16
-sfr = "ADC_CHDR.CH0", "Memory", 0xfffd8014, 4, base=16, bitRange=0
-sfr = "ADC_CHDR.CH1", "Memory", 0xfffd8014, 4, base=16, bitRange=1
-sfr = "ADC_CHDR.CH2", "Memory", 0xfffd8014, 4, base=16, bitRange=2
-sfr = "ADC_CHDR.CH3", "Memory", 0xfffd8014, 4, base=16, bitRange=3
-sfr = "ADC_CHDR.CH4", "Memory", 0xfffd8014, 4, base=16, bitRange=4
-sfr = "ADC_CHDR.CH5", "Memory", 0xfffd8014, 4, base=16, bitRange=5
-sfr = "ADC_CHDR.CH6", "Memory", 0xfffd8014, 4, base=16, bitRange=6
-sfr = "ADC_CHDR.CH7", "Memory", 0xfffd8014, 4, base=16, bitRange=7
-sfr = "ADC_CHSR", "Memory", 0xfffd8018, 4, base=16
-sfr = "ADC_CHSR.CH0", "Memory", 0xfffd8018, 4, base=16, bitRange=0
-sfr = "ADC_CHSR.CH1", "Memory", 0xfffd8018, 4, base=16, bitRange=1
-sfr = "ADC_CHSR.CH2", "Memory", 0xfffd8018, 4, base=16, bitRange=2
-sfr = "ADC_CHSR.CH3", "Memory", 0xfffd8018, 4, base=16, bitRange=3
-sfr = "ADC_CHSR.CH4", "Memory", 0xfffd8018, 4, base=16, bitRange=4
-sfr = "ADC_CHSR.CH5", "Memory", 0xfffd8018, 4, base=16, bitRange=5
-sfr = "ADC_CHSR.CH6", "Memory", 0xfffd8018, 4, base=16, bitRange=6
-sfr = "ADC_CHSR.CH7", "Memory", 0xfffd8018, 4, base=16, bitRange=7
-sfr = "ADC_SR", "Memory", 0xfffd801c, 4, base=16
-sfr = "ADC_SR.EOC0", "Memory", 0xfffd801c, 4, base=16, bitRange=0
-sfr = "ADC_SR.EOC1", "Memory", 0xfffd801c, 4, base=16, bitRange=1
-sfr = "ADC_SR.EOC2", "Memory", 0xfffd801c, 4, base=16, bitRange=2
-sfr = "ADC_SR.EOC3", "Memory", 0xfffd801c, 4, base=16, bitRange=3
-sfr = "ADC_SR.EOC4", "Memory", 0xfffd801c, 4, base=16, bitRange=4
-sfr = "ADC_SR.EOC5", "Memory", 0xfffd801c, 4, base=16, bitRange=5
-sfr = "ADC_SR.EOC6", "Memory", 0xfffd801c, 4, base=16, bitRange=6
-sfr = "ADC_SR.EOC7", "Memory", 0xfffd801c, 4, base=16, bitRange=7
-sfr = "ADC_SR.OVRE0", "Memory", 0xfffd801c, 4, base=16, bitRange=8
-sfr = "ADC_SR.OVRE1", "Memory", 0xfffd801c, 4, base=16, bitRange=9
-sfr = "ADC_SR.OVRE2", "Memory", 0xfffd801c, 4, base=16, bitRange=10
-sfr = "ADC_SR.OVRE3", "Memory", 0xfffd801c, 4, base=16, bitRange=11
-sfr = "ADC_SR.OVRE4", "Memory", 0xfffd801c, 4, base=16, bitRange=12
-sfr = "ADC_SR.OVRE5", "Memory", 0xfffd801c, 4, base=16, bitRange=13
-sfr = "ADC_SR.OVRE6", "Memory", 0xfffd801c, 4, base=16, bitRange=14
-sfr = "ADC_SR.OVRE7", "Memory", 0xfffd801c, 4, base=16, bitRange=15
-sfr = "ADC_SR.DRDY", "Memory", 0xfffd801c, 4, base=16, bitRange=16
-sfr = "ADC_SR.GOVRE", "Memory", 0xfffd801c, 4, base=16, bitRange=17
-sfr = "ADC_SR.ENDRX", "Memory", 0xfffd801c, 4, base=16, bitRange=18
-sfr = "ADC_SR.RXBUFF", "Memory", 0xfffd801c, 4, base=16, bitRange=19
-sfr = "ADC_LCDR", "Memory", 0xfffd8020, 4, base=16
-sfr = "ADC_LCDR.LDATA", "Memory", 0xfffd8020, 4, base=16, bitRange=0-9
-sfr = "ADC_IER", "Memory", 0xfffd8024, 4, base=16
-sfr = "ADC_IER.EOC0", "Memory", 0xfffd8024, 4, base=16, bitRange=0
-sfr = "ADC_IER.EOC1", "Memory", 0xfffd8024, 4, base=16, bitRange=1
-sfr = "ADC_IER.EOC2", "Memory", 0xfffd8024, 4, base=16, bitRange=2
-sfr = "ADC_IER.EOC3", "Memory", 0xfffd8024, 4, base=16, bitRange=3
-sfr = "ADC_IER.EOC4", "Memory", 0xfffd8024, 4, base=16, bitRange=4
-sfr = "ADC_IER.EOC5", "Memory", 0xfffd8024, 4, base=16, bitRange=5
-sfr = "ADC_IER.EOC6", "Memory", 0xfffd8024, 4, base=16, bitRange=6
-sfr = "ADC_IER.EOC7", "Memory", 0xfffd8024, 4, base=16, bitRange=7
-sfr = "ADC_IER.OVRE0", "Memory", 0xfffd8024, 4, base=16, bitRange=8
-sfr = "ADC_IER.OVRE1", "Memory", 0xfffd8024, 4, base=16, bitRange=9
-sfr = "ADC_IER.OVRE2", "Memory", 0xfffd8024, 4, base=16, bitRange=10
-sfr = "ADC_IER.OVRE3", "Memory", 0xfffd8024, 4, base=16, bitRange=11
-sfr = "ADC_IER.OVRE4", "Memory", 0xfffd8024, 4, base=16, bitRange=12
-sfr = "ADC_IER.OVRE5", "Memory", 0xfffd8024, 4, base=16, bitRange=13
-sfr = "ADC_IER.OVRE6", "Memory", 0xfffd8024, 4, base=16, bitRange=14
-sfr = "ADC_IER.OVRE7", "Memory", 0xfffd8024, 4, base=16, bitRange=15
-sfr = "ADC_IER.DRDY", "Memory", 0xfffd8024, 4, base=16, bitRange=16
-sfr = "ADC_IER.GOVRE", "Memory", 0xfffd8024, 4, base=16, bitRange=17
-sfr = "ADC_IER.ENDRX", "Memory", 0xfffd8024, 4, base=16, bitRange=18
-sfr = "ADC_IER.RXBUFF", "Memory", 0xfffd8024, 4, base=16, bitRange=19
-sfr = "ADC_IDR", "Memory", 0xfffd8028, 4, base=16
-sfr = "ADC_IDR.EOC0", "Memory", 0xfffd8028, 4, base=16, bitRange=0
-sfr = "ADC_IDR.EOC1", "Memory", 0xfffd8028, 4, base=16, bitRange=1
-sfr = "ADC_IDR.EOC2", "Memory", 0xfffd8028, 4, base=16, bitRange=2
-sfr = "ADC_IDR.EOC3", "Memory", 0xfffd8028, 4, base=16, bitRange=3
-sfr = "ADC_IDR.EOC4", "Memory", 0xfffd8028, 4, base=16, bitRange=4
-sfr = "ADC_IDR.EOC5", "Memory", 0xfffd8028, 4, base=16, bitRange=5
-sfr = "ADC_IDR.EOC6", "Memory", 0xfffd8028, 4, base=16, bitRange=6
-sfr = "ADC_IDR.EOC7", "Memory", 0xfffd8028, 4, base=16, bitRange=7
-sfr = "ADC_IDR.OVRE0", "Memory", 0xfffd8028, 4, base=16, bitRange=8
-sfr = "ADC_IDR.OVRE1", "Memory", 0xfffd8028, 4, base=16, bitRange=9
-sfr = "ADC_IDR.OVRE2", "Memory", 0xfffd8028, 4, base=16, bitRange=10
-sfr = "ADC_IDR.OVRE3", "Memory", 0xfffd8028, 4, base=16, bitRange=11
-sfr = "ADC_IDR.OVRE4", "Memory", 0xfffd8028, 4, base=16, bitRange=12
-sfr = "ADC_IDR.OVRE5", "Memory", 0xfffd8028, 4, base=16, bitRange=13
-sfr = "ADC_IDR.OVRE6", "Memory", 0xfffd8028, 4, base=16, bitRange=14
-sfr = "ADC_IDR.OVRE7", "Memory", 0xfffd8028, 4, base=16, bitRange=15
-sfr = "ADC_IDR.DRDY", "Memory", 0xfffd8028, 4, base=16, bitRange=16
-sfr = "ADC_IDR.GOVRE", "Memory", 0xfffd8028, 4, base=16, bitRange=17
-sfr = "ADC_IDR.ENDRX", "Memory", 0xfffd8028, 4, base=16, bitRange=18
-sfr = "ADC_IDR.RXBUFF", "Memory", 0xfffd8028, 4, base=16, bitRange=19
-sfr = "ADC_IMR", "Memory", 0xfffd802c, 4, base=16
-sfr = "ADC_IMR.EOC0", "Memory", 0xfffd802c, 4, base=16, bitRange=0
-sfr = "ADC_IMR.EOC1", "Memory", 0xfffd802c, 4, base=16, bitRange=1
-sfr = "ADC_IMR.EOC2", "Memory", 0xfffd802c, 4, base=16, bitRange=2
-sfr = "ADC_IMR.EOC3", "Memory", 0xfffd802c, 4, base=16, bitRange=3
-sfr = "ADC_IMR.EOC4", "Memory", 0xfffd802c, 4, base=16, bitRange=4
-sfr = "ADC_IMR.EOC5", "Memory", 0xfffd802c, 4, base=16, bitRange=5
-sfr = "ADC_IMR.EOC6", "Memory", 0xfffd802c, 4, base=16, bitRange=6
-sfr = "ADC_IMR.EOC7", "Memory", 0xfffd802c, 4, base=16, bitRange=7
-sfr = "ADC_IMR.OVRE0", "Memory", 0xfffd802c, 4, base=16, bitRange=8
-sfr = "ADC_IMR.OVRE1", "Memory", 0xfffd802c, 4, base=16, bitRange=9
-sfr = "ADC_IMR.OVRE2", "Memory", 0xfffd802c, 4, base=16, bitRange=10
-sfr = "ADC_IMR.OVRE3", "Memory", 0xfffd802c, 4, base=16, bitRange=11
-sfr = "ADC_IMR.OVRE4", "Memory", 0xfffd802c, 4, base=16, bitRange=12
-sfr = "ADC_IMR.OVRE5", "Memory", 0xfffd802c, 4, base=16, bitRange=13
-sfr = "ADC_IMR.OVRE6", "Memory", 0xfffd802c, 4, base=16, bitRange=14
-sfr = "ADC_IMR.OVRE7", "Memory", 0xfffd802c, 4, base=16, bitRange=15
-sfr = "ADC_IMR.DRDY", "Memory", 0xfffd802c, 4, base=16, bitRange=16
-sfr = "ADC_IMR.GOVRE", "Memory", 0xfffd802c, 4, base=16, bitRange=17
-sfr = "ADC_IMR.ENDRX", "Memory", 0xfffd802c, 4, base=16, bitRange=18
-sfr = "ADC_IMR.RXBUFF", "Memory", 0xfffd802c, 4, base=16, bitRange=19
-sfr = "ADC_CDR0", "Memory", 0xfffd8030, 4, base=16
-sfr = "ADC_CDR0.DATA", "Memory", 0xfffd8030, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR1", "Memory", 0xfffd8034, 4, base=16
-sfr = "ADC_CDR1.DATA", "Memory", 0xfffd8034, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR2", "Memory", 0xfffd8038, 4, base=16
-sfr = "ADC_CDR2.DATA", "Memory", 0xfffd8038, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR3", "Memory", 0xfffd803c, 4, base=16
-sfr = "ADC_CDR3.DATA", "Memory", 0xfffd803c, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR4", "Memory", 0xfffd8040, 4, base=16
-sfr = "ADC_CDR4.DATA", "Memory", 0xfffd8040, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR5", "Memory", 0xfffd8044, 4, base=16
-sfr = "ADC_CDR5.DATA", "Memory", 0xfffd8044, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR6", "Memory", 0xfffd8048, 4, base=16
-sfr = "ADC_CDR6.DATA", "Memory", 0xfffd8048, 4, base=16, bitRange=0-9
-sfr = "ADC_CDR7", "Memory", 0xfffd804c, 4, base=16
-sfr = "ADC_CDR7.DATA", "Memory", 0xfffd804c, 4, base=16, bitRange=0-9
-; ========== Register definition for PDC_SSC peripheral ==========
-sfr = "SSC_RPR", "Memory", 0xfffd4100, 4, base=16
-sfr = "SSC_RCR", "Memory", 0xfffd4104, 4, base=16
-sfr = "SSC_TPR", "Memory", 0xfffd4108, 4, base=16
-sfr = "SSC_TCR", "Memory", 0xfffd410c, 4, base=16
-sfr = "SSC_RNPR", "Memory", 0xfffd4110, 4, base=16
-sfr = "SSC_RNCR", "Memory", 0xfffd4114, 4, base=16
-sfr = "SSC_TNPR", "Memory", 0xfffd4118, 4, base=16
-sfr = "SSC_TNCR", "Memory", 0xfffd411c, 4, base=16
-sfr = "SSC_PTCR", "Memory", 0xfffd4120, 4, base=16
-sfr = "SSC_PTCR.RXTEN", "Memory", 0xfffd4120, 4, base=16, bitRange=0
-sfr = "SSC_PTCR.RXTDIS", "Memory", 0xfffd4120, 4, base=16, bitRange=1
-sfr = "SSC_PTCR.TXTEN", "Memory", 0xfffd4120, 4, base=16, bitRange=8
-sfr = "SSC_PTCR.TXTDIS", "Memory", 0xfffd4120, 4, base=16, bitRange=9
-sfr = "SSC_PTSR", "Memory", 0xfffd4124, 4, base=16
-sfr = "SSC_PTSR.RXTEN", "Memory", 0xfffd4124, 4, base=16, bitRange=0
-sfr = "SSC_PTSR.TXTEN", "Memory", 0xfffd4124, 4, base=16, bitRange=8
-; ========== Register definition for SSC peripheral ==========
-sfr = "SSC_CR", "Memory", 0xfffd4000, 4, base=16
-sfr = "SSC_CR.RXEN", "Memory", 0xfffd4000, 4, base=16, bitRange=0
-sfr = "SSC_CR.RXDIS", "Memory", 0xfffd4000, 4, base=16, bitRange=1
-sfr = "SSC_CR.TXEN", "Memory", 0xfffd4000, 4, base=16, bitRange=8
-sfr = "SSC_CR.TXDIS", "Memory", 0xfffd4000, 4, base=16, bitRange=9
-sfr = "SSC_CR.SWRST", "Memory", 0xfffd4000, 4, base=16, bitRange=15
-sfr = "SSC_CMR", "Memory", 0xfffd4004, 4, base=16
-sfr = "SSC_RCMR", "Memory", 0xfffd4010, 4, base=16
-sfr = "SSC_RCMR.CKS", "Memory", 0xfffd4010, 4, base=16, bitRange=0-1
-sfr = "SSC_RCMR.CKO", "Memory", 0xfffd4010, 4, base=16, bitRange=2-4
-sfr = "SSC_RCMR.CKI", "Memory", 0xfffd4010, 4, base=16, bitRange=5
-sfr = "SSC_RCMR.START", "Memory", 0xfffd4010, 4, base=16, bitRange=8-11
-sfr = "SSC_RCMR.STTDLY", "Memory", 0xfffd4010, 4, base=16, bitRange=16-23
-sfr = "SSC_RCMR.PERIOD", "Memory", 0xfffd4010, 4, base=16, bitRange=24-31
-sfr = "SSC_RFMR", "Memory", 0xfffd4014, 4, base=16
-sfr = "SSC_RFMR.DATLEN", "Memory", 0xfffd4014, 4, base=16, bitRange=0-4
-sfr = "SSC_RFMR.LOOP", "Memory", 0xfffd4014, 4, base=16, bitRange=5
-sfr = "SSC_RFMR.MSBF", "Memory", 0xfffd4014, 4, base=16, bitRange=7
-sfr = "SSC_RFMR.DATNB", "Memory", 0xfffd4014, 4, base=16, bitRange=8-11
-sfr = "SSC_RFMR.FSLEN", "Memory", 0xfffd4014, 4, base=16, bitRange=16-19
-sfr = "SSC_RFMR.FSOS", "Memory", 0xfffd4014, 4, base=16, bitRange=20-22
-sfr = "SSC_RFMR.FSEDGE", "Memory", 0xfffd4014, 4, base=16, bitRange=24
-sfr = "SSC_TCMR", "Memory", 0xfffd4018, 4, base=16
-sfr = "SSC_TCMR.CKS", "Memory", 0xfffd4018, 4, base=16, bitRange=0-1
-sfr = "SSC_TCMR.CKO", "Memory", 0xfffd4018, 4, base=16, bitRange=2-4
-sfr = "SSC_TCMR.CKI", "Memory", 0xfffd4018, 4, base=16, bitRange=5
-sfr = "SSC_TCMR.START", "Memory", 0xfffd4018, 4, base=16, bitRange=8-11
-sfr = "SSC_TCMR.STTDLY", "Memory", 0xfffd4018, 4, base=16, bitRange=16-23
-sfr = "SSC_TCMR.PERIOD", "Memory", 0xfffd4018, 4, base=16, bitRange=24-31
-sfr = "SSC_TFMR", "Memory", 0xfffd401c, 4, base=16
-sfr = "SSC_TFMR.DATLEN", "Memory", 0xfffd401c, 4, base=16, bitRange=0-4
-sfr = "SSC_TFMR.DATDEF", "Memory", 0xfffd401c, 4, base=16, bitRange=5
-sfr = "SSC_TFMR.MSBF", "Memory", 0xfffd401c, 4, base=16, bitRange=7
-sfr = "SSC_TFMR.DATNB", "Memory", 0xfffd401c, 4, base=16, bitRange=8-11
-sfr = "SSC_TFMR.FSLEN", "Memory", 0xfffd401c, 4, base=16, bitRange=16-19
-sfr = "SSC_TFMR.FSOS", "Memory", 0xfffd401c, 4, base=16, bitRange=20-22
-sfr = "SSC_TFMR.FSDEN", "Memory", 0xfffd401c, 4, base=16, bitRange=23
-sfr = "SSC_TFMR.FSEDGE", "Memory", 0xfffd401c, 4, base=16, bitRange=24
-sfr = "SSC_RHR", "Memory", 0xfffd4020, 4, base=16
-sfr = "SSC_THR", "Memory", 0xfffd4024, 4, base=16
-sfr = "SSC_RSHR", "Memory", 0xfffd4030, 4, base=16
-sfr = "SSC_TSHR", "Memory", 0xfffd4034, 4, base=16
-sfr = "SSC_SR", "Memory", 0xfffd4040, 4, base=16
-sfr = "SSC_SR.TXRDY", "Memory", 0xfffd4040, 4, base=16, bitRange=0
-sfr = "SSC_SR.TXEMPTY", "Memory", 0xfffd4040, 4, base=16, bitRange=1
-sfr = "SSC_SR.ENDTX", "Memory", 0xfffd4040, 4, base=16, bitRange=2
-sfr = "SSC_SR.TXBUFE", "Memory", 0xfffd4040, 4, base=16, bitRange=3
-sfr = "SSC_SR.RXRDY", "Memory", 0xfffd4040, 4, base=16, bitRange=4
-sfr = "SSC_SR.OVRUN", "Memory", 0xfffd4040, 4, base=16, bitRange=5
-sfr = "SSC_SR.ENDRX", "Memory", 0xfffd4040, 4, base=16, bitRange=6
-sfr = "SSC_SR.RXBUFF", "Memory", 0xfffd4040, 4, base=16, bitRange=7
-sfr = "SSC_SR.TXSYN", "Memory", 0xfffd4040, 4, base=16, bitRange=10
-sfr = "SSC_SR.RXSYN", "Memory", 0xfffd4040, 4, base=16, bitRange=11
-sfr = "SSC_SR.TXENA", "Memory", 0xfffd4040, 4, base=16, bitRange=16
-sfr = "SSC_SR.RXENA", "Memory", 0xfffd4040, 4, base=16, bitRange=17
-sfr = "SSC_IER", "Memory", 0xfffd4044, 4, base=16
-sfr = "SSC_IER.TXRDY", "Memory", 0xfffd4044, 4, base=16, bitRange=0
-sfr = "SSC_IER.TXEMPTY", "Memory", 0xfffd4044, 4, base=16, bitRange=1
-sfr = "SSC_IER.ENDTX", "Memory", 0xfffd4044, 4, base=16, bitRange=2
-sfr = "SSC_IER.TXBUFE", "Memory", 0xfffd4044, 4, base=16, bitRange=3
-sfr = "SSC_IER.RXRDY", "Memory", 0xfffd4044, 4, base=16, bitRange=4
-sfr = "SSC_IER.OVRUN", "Memory", 0xfffd4044, 4, base=16, bitRange=5
-sfr = "SSC_IER.ENDRX", "Memory", 0xfffd4044, 4, base=16, bitRange=6
-sfr = "SSC_IER.RXBUFF", "Memory", 0xfffd4044, 4, base=16, bitRange=7
-sfr = "SSC_IER.TXSYN", "Memory", 0xfffd4044, 4, base=16, bitRange=10
-sfr = "SSC_IER.RXSYN", "Memory", 0xfffd4044, 4, base=16, bitRange=11
-sfr = "SSC_IDR", "Memory", 0xfffd4048, 4, base=16
-sfr = "SSC_IDR.TXRDY", "Memory", 0xfffd4048, 4, base=16, bitRange=0
-sfr = "SSC_IDR.TXEMPTY", "Memory", 0xfffd4048, 4, base=16, bitRange=1
-sfr = "SSC_IDR.ENDTX", "Memory", 0xfffd4048, 4, base=16, bitRange=2
-sfr = "SSC_IDR.TXBUFE", "Memory", 0xfffd4048, 4, base=16, bitRange=3
-sfr = "SSC_IDR.RXRDY", "Memory", 0xfffd4048, 4, base=16, bitRange=4
-sfr = "SSC_IDR.OVRUN", "Memory", 0xfffd4048, 4, base=16, bitRange=5
-sfr = "SSC_IDR.ENDRX", "Memory", 0xfffd4048, 4, base=16, bitRange=6
-sfr = "SSC_IDR.RXBUFF", "Memory", 0xfffd4048, 4, base=16, bitRange=7
-sfr = "SSC_IDR.TXSYN", "Memory", 0xfffd4048, 4, base=16, bitRange=10
-sfr = "SSC_IDR.RXSYN", "Memory", 0xfffd4048, 4, base=16, bitRange=11
-sfr = "SSC_IMR", "Memory", 0xfffd404c, 4, base=16
-sfr = "SSC_IMR.TXRDY", "Memory", 0xfffd404c, 4, base=16, bitRange=0
-sfr = "SSC_IMR.TXEMPTY", "Memory", 0xfffd404c, 4, base=16, bitRange=1
-sfr = "SSC_IMR.ENDTX", "Memory", 0xfffd404c, 4, base=16, bitRange=2
-sfr = "SSC_IMR.TXBUFE", "Memory", 0xfffd404c, 4, base=16, bitRange=3
-sfr = "SSC_IMR.RXRDY", "Memory", 0xfffd404c, 4, base=16, bitRange=4
-sfr = "SSC_IMR.OVRUN", "Memory", 0xfffd404c, 4, base=16, bitRange=5
-sfr = "SSC_IMR.ENDRX", "Memory", 0xfffd404c, 4, base=16, bitRange=6
-sfr = "SSC_IMR.RXBUFF", "Memory", 0xfffd404c, 4, base=16, bitRange=7
-sfr = "SSC_IMR.TXSYN", "Memory", 0xfffd404c, 4, base=16, bitRange=10
-sfr = "SSC_IMR.RXSYN", "Memory", 0xfffd404c, 4, base=16, bitRange=11
-; ========== Register definition for PDC_US1 peripheral ==========
-sfr = "US1_RPR", "Memory", 0xfffc4100, 4, base=16
-sfr = "US1_RCR", "Memory", 0xfffc4104, 4, base=16
-sfr = "US1_TPR", "Memory", 0xfffc4108, 4, base=16
-sfr = "US1_TCR", "Memory", 0xfffc410c, 4, base=16
-sfr = "US1_RNPR", "Memory", 0xfffc4110, 4, base=16
-sfr = "US1_RNCR", "Memory", 0xfffc4114, 4, base=16
-sfr = "US1_TNPR", "Memory", 0xfffc4118, 4, base=16
-sfr = "US1_TNCR", "Memory", 0xfffc411c, 4, base=16
-sfr = "US1_PTCR", "Memory", 0xfffc4120, 4, base=16
-sfr = "US1_PTCR.RXTEN", "Memory", 0xfffc4120, 4, base=16, bitRange=0
-sfr = "US1_PTCR.RXTDIS", "Memory", 0xfffc4120, 4, base=16, bitRange=1
-sfr = "US1_PTCR.TXTEN", "Memory", 0xfffc4120, 4, base=16, bitRange=8
-sfr = "US1_PTCR.TXTDIS", "Memory", 0xfffc4120, 4, base=16, bitRange=9
-sfr = "US1_PTSR", "Memory", 0xfffc4124, 4, base=16
-sfr = "US1_PTSR.RXTEN", "Memory", 0xfffc4124, 4, base=16, bitRange=0
-sfr = "US1_PTSR.TXTEN", "Memory", 0xfffc4124, 4, base=16, bitRange=8
-; ========== Register definition for US1 peripheral ==========
-sfr = "US1_CR", "Memory", 0xfffc4000, 4, base=16
-sfr = "US1_CR.RSTRX", "Memory", 0xfffc4000, 4, base=16, bitRange=2
-sfr = "US1_CR.RSTTX", "Memory", 0xfffc4000, 4, base=16, bitRange=3
-sfr = "US1_CR.RXEN", "Memory", 0xfffc4000, 4, base=16, bitRange=4
-sfr = "US1_CR.RXDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=5
-sfr = "US1_CR.TXEN", "Memory", 0xfffc4000, 4, base=16, bitRange=6
-sfr = "US1_CR.TXDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=7
-sfr = "US1_CR.RSTSTA", "Memory", 0xfffc4000, 4, base=16, bitRange=8
-sfr = "US1_CR.STTBRK", "Memory", 0xfffc4000, 4, base=16, bitRange=9
-sfr = "US1_CR.STPBRK", "Memory", 0xfffc4000, 4, base=16, bitRange=10
-sfr = "US1_CR.STTTO", "Memory", 0xfffc4000, 4, base=16, bitRange=11
-sfr = "US1_CR.SENDA", "Memory", 0xfffc4000, 4, base=16, bitRange=12
-sfr = "US1_CR.RSTIT", "Memory", 0xfffc4000, 4, base=16, bitRange=13
-sfr = "US1_CR.RSTNACK", "Memory", 0xfffc4000, 4, base=16, bitRange=14
-sfr = "US1_CR.RETTO", "Memory", 0xfffc4000, 4, base=16, bitRange=15
-sfr = "US1_CR.DTREN", "Memory", 0xfffc4000, 4, base=16, bitRange=16
-sfr = "US1_CR.DTRDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=17
-sfr = "US1_CR.RTSEN", "Memory", 0xfffc4000, 4, base=16, bitRange=18
-sfr = "US1_CR.RTSDIS", "Memory", 0xfffc4000, 4, base=16, bitRange=19
-sfr = "US1_MR", "Memory", 0xfffc4004, 4, base=16
-sfr = "US1_MR.USMODE", "Memory", 0xfffc4004, 4, base=16, bitRange=0-3
-sfr = "US1_MR.CLKS", "Memory", 0xfffc4004, 4, base=16, bitRange=4-5
-sfr = "US1_MR.CHRL", "Memory", 0xfffc4004, 4, base=16, bitRange=6-7
-sfr = "US1_MR.SYNC", "Memory", 0xfffc4004, 4, base=16, bitRange=8
-sfr = "US1_MR.PAR", "Memory", 0xfffc4004, 4, base=16, bitRange=9-11
-sfr = "US1_MR.NBSTOP", "Memory", 0xfffc4004, 4, base=16, bitRange=12-13
-sfr = "US1_MR.CHMODE", "Memory", 0xfffc4004, 4, base=16, bitRange=14-15
-sfr = "US1_MR.MSBF", "Memory", 0xfffc4004, 4, base=16, bitRange=16
-sfr = "US1_MR.MODE9", "Memory", 0xfffc4004, 4, base=16, bitRange=17
-sfr = "US1_MR.CKLO", "Memory", 0xfffc4004, 4, base=16, bitRange=18
-sfr = "US1_MR.OVER", "Memory", 0xfffc4004, 4, base=16, bitRange=19
-sfr = "US1_MR.INACK", "Memory", 0xfffc4004, 4, base=16, bitRange=20
-sfr = "US1_MR.DSNACK", "Memory", 0xfffc4004, 4, base=16, bitRange=21
-sfr = "US1_MR.ITER", "Memory", 0xfffc4004, 4, base=16, bitRange=24
-sfr = "US1_MR.FILTER", "Memory", 0xfffc4004, 4, base=16, bitRange=28
-sfr = "US1_IER", "Memory", 0xfffc4008, 4, base=16
-sfr = "US1_IER.RXRDY", "Memory", 0xfffc4008, 4, base=16, bitRange=0
-sfr = "US1_IER.TXRDY", "Memory", 0xfffc4008, 4, base=16, bitRange=1
-sfr = "US1_IER.RXBRK", "Memory", 0xfffc4008, 4, base=16, bitRange=2
-sfr = "US1_IER.ENDRX", "Memory", 0xfffc4008, 4, base=16, bitRange=3
-sfr = "US1_IER.ENDTX", "Memory", 0xfffc4008, 4, base=16, bitRange=4
-sfr = "US1_IER.OVRE", "Memory", 0xfffc4008, 4, base=16, bitRange=5
-sfr = "US1_IER.FRAME", "Memory", 0xfffc4008, 4, base=16, bitRange=6
-sfr = "US1_IER.PARE", "Memory", 0xfffc4008, 4, base=16, bitRange=7
-sfr = "US1_IER.TIMEOUT", "Memory", 0xfffc4008, 4, base=16, bitRange=8
-sfr = "US1_IER.TXEMPTY", "Memory", 0xfffc4008, 4, base=16, bitRange=9
-sfr = "US1_IER.ITERATION", "Memory", 0xfffc4008, 4, base=16, bitRange=10
-sfr = "US1_IER.TXBUFE", "Memory", 0xfffc4008, 4, base=16, bitRange=11
-sfr = "US1_IER.RXBUFF", "Memory", 0xfffc4008, 4, base=16, bitRange=12
-sfr = "US1_IER.NACK", "Memory", 0xfffc4008, 4, base=16, bitRange=13
-sfr = "US1_IER.RIIC", "Memory", 0xfffc4008, 4, base=16, bitRange=16
-sfr = "US1_IER.DSRIC", "Memory", 0xfffc4008, 4, base=16, bitRange=17
-sfr = "US1_IER.DCDIC", "Memory", 0xfffc4008, 4, base=16, bitRange=18
-sfr = "US1_IER.CTSIC", "Memory", 0xfffc4008, 4, base=16, bitRange=19
-sfr = "US1_IDR", "Memory", 0xfffc400c, 4, base=16
-sfr = "US1_IDR.RXRDY", "Memory", 0xfffc400c, 4, base=16, bitRange=0
-sfr = "US1_IDR.TXRDY", "Memory", 0xfffc400c, 4, base=16, bitRange=1
-sfr = "US1_IDR.RXBRK", "Memory", 0xfffc400c, 4, base=16, bitRange=2
-sfr = "US1_IDR.ENDRX", "Memory", 0xfffc400c, 4, base=16, bitRange=3
-sfr = "US1_IDR.ENDTX", "Memory", 0xfffc400c, 4, base=16, bitRange=4
-sfr = "US1_IDR.OVRE", "Memory", 0xfffc400c, 4, base=16, bitRange=5
-sfr = "US1_IDR.FRAME", "Memory", 0xfffc400c, 4, base=16, bitRange=6
-sfr = "US1_IDR.PARE", "Memory", 0xfffc400c, 4, base=16, bitRange=7
-sfr = "US1_IDR.TIMEOUT", "Memory", 0xfffc400c, 4, base=16, bitRange=8
-sfr = "US1_IDR.TXEMPTY", "Memory", 0xfffc400c, 4, base=16, bitRange=9
-sfr = "US1_IDR.ITERATION", "Memory", 0xfffc400c, 4, base=16, bitRange=10
-sfr = "US1_IDR.TXBUFE", "Memory", 0xfffc400c, 4, base=16, bitRange=11
-sfr = "US1_IDR.RXBUFF", "Memory", 0xfffc400c, 4, base=16, bitRange=12
-sfr = "US1_IDR.NACK", "Memory", 0xfffc400c, 4, base=16, bitRange=13
-sfr = "US1_IDR.RIIC", "Memory", 0xfffc400c, 4, base=16, bitRange=16
-sfr = "US1_IDR.DSRIC", "Memory", 0xfffc400c, 4, base=16, bitRange=17
-sfr = "US1_IDR.DCDIC", "Memory", 0xfffc400c, 4, base=16, bitRange=18
-sfr = "US1_IDR.CTSIC", "Memory", 0xfffc400c, 4, base=16, bitRange=19
-sfr = "US1_IMR", "Memory", 0xfffc4010, 4, base=16
-sfr = "US1_IMR.RXRDY", "Memory", 0xfffc4010, 4, base=16, bitRange=0
-sfr = "US1_IMR.TXRDY", "Memory", 0xfffc4010, 4, base=16, bitRange=1
-sfr = "US1_IMR.RXBRK", "Memory", 0xfffc4010, 4, base=16, bitRange=2
-sfr = "US1_IMR.ENDRX", "Memory", 0xfffc4010, 4, base=16, bitRange=3
-sfr = "US1_IMR.ENDTX", "Memory", 0xfffc4010, 4, base=16, bitRange=4
-sfr = "US1_IMR.OVRE", "Memory", 0xfffc4010, 4, base=16, bitRange=5
-sfr = "US1_IMR.FRAME", "Memory", 0xfffc4010, 4, base=16, bitRange=6
-sfr = "US1_IMR.PARE", "Memory", 0xfffc4010, 4, base=16, bitRange=7
-sfr = "US1_IMR.TIMEOUT", "Memory", 0xfffc4010, 4, base=16, bitRange=8
-sfr = "US1_IMR.TXEMPTY", "Memory", 0xfffc4010, 4, base=16, bitRange=9
-sfr = "US1_IMR.ITERATION", "Memory", 0xfffc4010, 4, base=16, bitRange=10
-sfr = "US1_IMR.TXBUFE", "Memory", 0xfffc4010, 4, base=16, bitRange=11
-sfr = "US1_IMR.RXBUFF", "Memory", 0xfffc4010, 4, base=16, bitRange=12
-sfr = "US1_IMR.NACK", "Memory", 0xfffc4010, 4, base=16, bitRange=13
-sfr = "US1_IMR.RIIC", "Memory", 0xfffc4010, 4, base=16, bitRange=16
-sfr = "US1_IMR.DSRIC", "Memory", 0xfffc4010, 4, base=16, bitRange=17
-sfr = "US1_IMR.DCDIC", "Memory", 0xfffc4010, 4, base=16, bitRange=18
-sfr = "US1_IMR.CTSIC", "Memory", 0xfffc4010, 4, base=16, bitRange=19
-sfr = "US1_CSR", "Memory", 0xfffc4014, 4, base=16
-sfr = "US1_CSR.RXRDY", "Memory", 0xfffc4014, 4, base=16, bitRange=0
-sfr = "US1_CSR.TXRDY", "Memory", 0xfffc4014, 4, base=16, bitRange=1
-sfr = "US1_CSR.RXBRK", "Memory", 0xfffc4014, 4, base=16, bitRange=2
-sfr = "US1_CSR.ENDRX", "Memory", 0xfffc4014, 4, base=16, bitRange=3
-sfr = "US1_CSR.ENDTX", "Memory", 0xfffc4014, 4, base=16, bitRange=4
-sfr = "US1_CSR.OVRE", "Memory", 0xfffc4014, 4, base=16, bitRange=5
-sfr = "US1_CSR.FRAME", "Memory", 0xfffc4014, 4, base=16, bitRange=6
-sfr = "US1_CSR.PARE", "Memory", 0xfffc4014, 4, base=16, bitRange=7
-sfr = "US1_CSR.TIMEOUT", "Memory", 0xfffc4014, 4, base=16, bitRange=8
-sfr = "US1_CSR.TXEMPTY", "Memory", 0xfffc4014, 4, base=16, bitRange=9
-sfr = "US1_CSR.ITERATION", "Memory", 0xfffc4014, 4, base=16, bitRange=10
-sfr = "US1_CSR.TXBUFE", "Memory", 0xfffc4014, 4, base=16, bitRange=11
-sfr = "US1_CSR.RXBUFF", "Memory", 0xfffc4014, 4, base=16, bitRange=12
-sfr = "US1_CSR.NACK", "Memory", 0xfffc4014, 4, base=16, bitRange=13
-sfr = "US1_CSR.RIIC", "Memory", 0xfffc4014, 4, base=16, bitRange=16
-sfr = "US1_CSR.DSRIC", "Memory", 0xfffc4014, 4, base=16, bitRange=17
-sfr = "US1_CSR.DCDIC", "Memory", 0xfffc4014, 4, base=16, bitRange=18
-sfr = "US1_CSR.CTSIC", "Memory", 0xfffc4014, 4, base=16, bitRange=19
-sfr = "US1_CSR.RI", "Memory", 0xfffc4014, 4, base=16, bitRange=20
-sfr = "US1_CSR.DSR", "Memory", 0xfffc4014, 4, base=16, bitRange=21
-sfr = "US1_CSR.DCD", "Memory", 0xfffc4014, 4, base=16, bitRange=22
-sfr = "US1_CSR.CTS", "Memory", 0xfffc4014, 4, base=16, bitRange=23
-sfr = "US1_RHR", "Memory", 0xfffc4018, 4, base=16
-sfr = "US1_THR", "Memory", 0xfffc401c, 4, base=16
-sfr = "US1_BRGR", "Memory", 0xfffc4020, 4, base=16
-sfr = "US1_RTOR", "Memory", 0xfffc4024, 4, base=16
-sfr = "US1_TTGR", "Memory", 0xfffc4028, 4, base=16
-sfr = "US1_FIDI", "Memory", 0xfffc4040, 4, base=16
-sfr = "US1_NER", "Memory", 0xfffc4044, 4, base=16
-sfr = "US1_IF", "Memory", 0xfffc404c, 4, base=16
-; ========== Register definition for PDC_US0 peripheral ==========
-sfr = "US0_RPR", "Memory", 0xfffc0100, 4, base=16
-sfr = "US0_RCR", "Memory", 0xfffc0104, 4, base=16
-sfr = "US0_TPR", "Memory", 0xfffc0108, 4, base=16
-sfr = "US0_TCR", "Memory", 0xfffc010c, 4, base=16
-sfr = "US0_RNPR", "Memory", 0xfffc0110, 4, base=16
-sfr = "US0_RNCR", "Memory", 0xfffc0114, 4, base=16
-sfr = "US0_TNPR", "Memory", 0xfffc0118, 4, base=16
-sfr = "US0_TNCR", "Memory", 0xfffc011c, 4, base=16
-sfr = "US0_PTCR", "Memory", 0xfffc0120, 4, base=16
-sfr = "US0_PTCR.RXTEN", "Memory", 0xfffc0120, 4, base=16, bitRange=0
-sfr = "US0_PTCR.RXTDIS", "Memory", 0xfffc0120, 4, base=16, bitRange=1
-sfr = "US0_PTCR.TXTEN", "Memory", 0xfffc0120, 4, base=16, bitRange=8
-sfr = "US0_PTCR.TXTDIS", "Memory", 0xfffc0120, 4, base=16, bitRange=9
-sfr = "US0_PTSR", "Memory", 0xfffc0124, 4, base=16
-sfr = "US0_PTSR.RXTEN", "Memory", 0xfffc0124, 4, base=16, bitRange=0
-sfr = "US0_PTSR.TXTEN", "Memory", 0xfffc0124, 4, base=16, bitRange=8
-; ========== Register definition for US0 peripheral ==========
-sfr = "US0_CR", "Memory", 0xfffc0000, 4, base=16
-sfr = "US0_CR.RSTRX", "Memory", 0xfffc0000, 4, base=16, bitRange=2
-sfr = "US0_CR.RSTTX", "Memory", 0xfffc0000, 4, base=16, bitRange=3
-sfr = "US0_CR.RXEN", "Memory", 0xfffc0000, 4, base=16, bitRange=4
-sfr = "US0_CR.RXDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=5
-sfr = "US0_CR.TXEN", "Memory", 0xfffc0000, 4, base=16, bitRange=6
-sfr = "US0_CR.TXDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=7
-sfr = "US0_CR.RSTSTA", "Memory", 0xfffc0000, 4, base=16, bitRange=8
-sfr = "US0_CR.STTBRK", "Memory", 0xfffc0000, 4, base=16, bitRange=9
-sfr = "US0_CR.STPBRK", "Memory", 0xfffc0000, 4, base=16, bitRange=10
-sfr = "US0_CR.STTTO", "Memory", 0xfffc0000, 4, base=16, bitRange=11
-sfr = "US0_CR.SENDA", "Memory", 0xfffc0000, 4, base=16, bitRange=12
-sfr = "US0_CR.RSTIT", "Memory", 0xfffc0000, 4, base=16, bitRange=13
-sfr = "US0_CR.RSTNACK", "Memory", 0xfffc0000, 4, base=16, bitRange=14
-sfr = "US0_CR.RETTO", "Memory", 0xfffc0000, 4, base=16, bitRange=15
-sfr = "US0_CR.DTREN", "Memory", 0xfffc0000, 4, base=16, bitRange=16
-sfr = "US0_CR.DTRDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=17
-sfr = "US0_CR.RTSEN", "Memory", 0xfffc0000, 4, base=16, bitRange=18
-sfr = "US0_CR.RTSDIS", "Memory", 0xfffc0000, 4, base=16, bitRange=19
-sfr = "US0_MR", "Memory", 0xfffc0004, 4, base=16
-sfr = "US0_MR.USMODE", "Memory", 0xfffc0004, 4, base=16, bitRange=0-3
-sfr = "US0_MR.CLKS", "Memory", 0xfffc0004, 4, base=16, bitRange=4-5
-sfr = "US0_MR.CHRL", "Memory", 0xfffc0004, 4, base=16, bitRange=6-7
-sfr = "US0_MR.SYNC", "Memory", 0xfffc0004, 4, base=16, bitRange=8
-sfr = "US0_MR.PAR", "Memory", 0xfffc0004, 4, base=16, bitRange=9-11
-sfr = "US0_MR.NBSTOP", "Memory", 0xfffc0004, 4, base=16, bitRange=12-13
-sfr = "US0_MR.CHMODE", "Memory", 0xfffc0004, 4, base=16, bitRange=14-15
-sfr = "US0_MR.MSBF", "Memory", 0xfffc0004, 4, base=16, bitRange=16
-sfr = "US0_MR.MODE9", "Memory", 0xfffc0004, 4, base=16, bitRange=17
-sfr = "US0_MR.CKLO", "Memory", 0xfffc0004, 4, base=16, bitRange=18
-sfr = "US0_MR.OVER", "Memory", 0xfffc0004, 4, base=16, bitRange=19
-sfr = "US0_MR.INACK", "Memory", 0xfffc0004, 4, base=16, bitRange=20
-sfr = "US0_MR.DSNACK", "Memory", 0xfffc0004, 4, base=16, bitRange=21
-sfr = "US0_MR.ITER", "Memory", 0xfffc0004, 4, base=16, bitRange=24
-sfr = "US0_MR.FILTER", "Memory", 0xfffc0004, 4, base=16, bitRange=28
-sfr = "US0_IER", "Memory", 0xfffc0008, 4, base=16
-sfr = "US0_IER.RXRDY", "Memory", 0xfffc0008, 4, base=16, bitRange=0
-sfr = "US0_IER.TXRDY", "Memory", 0xfffc0008, 4, base=16, bitRange=1
-sfr = "US0_IER.RXBRK", "Memory", 0xfffc0008, 4, base=16, bitRange=2
-sfr = "US0_IER.ENDRX", "Memory", 0xfffc0008, 4, base=16, bitRange=3
-sfr = "US0_IER.ENDTX", "Memory", 0xfffc0008, 4, base=16, bitRange=4
-sfr = "US0_IER.OVRE", "Memory", 0xfffc0008, 4, base=16, bitRange=5
-sfr = "US0_IER.FRAME", "Memory", 0xfffc0008, 4, base=16, bitRange=6
-sfr = "US0_IER.PARE", "Memory", 0xfffc0008, 4, base=16, bitRange=7
-sfr = "US0_IER.TIMEOUT", "Memory", 0xfffc0008, 4, base=16, bitRange=8
-sfr = "US0_IER.TXEMPTY", "Memory", 0xfffc0008, 4, base=16, bitRange=9
-sfr = "US0_IER.ITERATION", "Memory", 0xfffc0008, 4, base=16, bitRange=10
-sfr = "US0_IER.TXBUFE", "Memory", 0xfffc0008, 4, base=16, bitRange=11
-sfr = "US0_IER.RXBUFF", "Memory", 0xfffc0008, 4, base=16, bitRange=12
-sfr = "US0_IER.NACK", "Memory", 0xfffc0008, 4, base=16, bitRange=13
-sfr = "US0_IER.RIIC", "Memory", 0xfffc0008, 4, base=16, bitRange=16
-sfr = "US0_IER.DSRIC", "Memory", 0xfffc0008, 4, base=16, bitRange=17
-sfr = "US0_IER.DCDIC", "Memory", 0xfffc0008, 4, base=16, bitRange=18
-sfr = "US0_IER.CTSIC", "Memory", 0xfffc0008, 4, base=16, bitRange=19
-sfr = "US0_IDR", "Memory", 0xfffc000c, 4, base=16
-sfr = "US0_IDR.RXRDY", "Memory", 0xfffc000c, 4, base=16, bitRange=0
-sfr = "US0_IDR.TXRDY", "Memory", 0xfffc000c, 4, base=16, bitRange=1
-sfr = "US0_IDR.RXBRK", "Memory", 0xfffc000c, 4, base=16, bitRange=2
-sfr = "US0_IDR.ENDRX", "Memory", 0xfffc000c, 4, base=16, bitRange=3
-sfr = "US0_IDR.ENDTX", "Memory", 0xfffc000c, 4, base=16, bitRange=4
-sfr = "US0_IDR.OVRE", "Memory", 0xfffc000c, 4, base=16, bitRange=5
-sfr = "US0_IDR.FRAME", "Memory", 0xfffc000c, 4, base=16, bitRange=6
-sfr = "US0_IDR.PARE", "Memory", 0xfffc000c, 4, base=16, bitRange=7
-sfr = "US0_IDR.TIMEOUT", "Memory", 0xfffc000c, 4, base=16, bitRange=8
-sfr = "US0_IDR.TXEMPTY", "Memory", 0xfffc000c, 4, base=16, bitRange=9
-sfr = "US0_IDR.ITERATION", "Memory", 0xfffc000c, 4, base=16, bitRange=10
-sfr = "US0_IDR.TXBUFE", "Memory", 0xfffc000c, 4, base=16, bitRange=11
-sfr = "US0_IDR.RXBUFF", "Memory", 0xfffc000c, 4, base=16, bitRange=12
-sfr = "US0_IDR.NACK", "Memory", 0xfffc000c, 4, base=16, bitRange=13
-sfr = "US0_IDR.RIIC", "Memory", 0xfffc000c, 4, base=16, bitRange=16
-sfr = "US0_IDR.DSRIC", "Memory", 0xfffc000c, 4, base=16, bitRange=17
-sfr = "US0_IDR.DCDIC", "Memory", 0xfffc000c, 4, base=16, bitRange=18
-sfr = "US0_IDR.CTSIC", "Memory", 0xfffc000c, 4, base=16, bitRange=19
-sfr = "US0_IMR", "Memory", 0xfffc0010, 4, base=16
-sfr = "US0_IMR.RXRDY", "Memory", 0xfffc0010, 4, base=16, bitRange=0
-sfr = "US0_IMR.TXRDY", "Memory", 0xfffc0010, 4, base=16, bitRange=1
-sfr = "US0_IMR.RXBRK", "Memory", 0xfffc0010, 4, base=16, bitRange=2
-sfr = "US0_IMR.ENDRX", "Memory", 0xfffc0010, 4, base=16, bitRange=3
-sfr = "US0_IMR.ENDTX", "Memory", 0xfffc0010, 4, base=16, bitRange=4
-sfr = "US0_IMR.OVRE", "Memory", 0xfffc0010, 4, base=16, bitRange=5
-sfr = "US0_IMR.FRAME", "Memory", 0xfffc0010, 4, base=16, bitRange=6
-sfr = "US0_IMR.PARE", "Memory", 0xfffc0010, 4, base=16, bitRange=7
-sfr = "US0_IMR.TIMEOUT", "Memory", 0xfffc0010, 4, base=16, bitRange=8
-sfr = "US0_IMR.TXEMPTY", "Memory", 0xfffc0010, 4, base=16, bitRange=9
-sfr = "US0_IMR.ITERATION", "Memory", 0xfffc0010, 4, base=16, bitRange=10
-sfr = "US0_IMR.TXBUFE", "Memory", 0xfffc0010, 4, base=16, bitRange=11
-sfr = "US0_IMR.RXBUFF", "Memory", 0xfffc0010, 4, base=16, bitRange=12
-sfr = "US0_IMR.NACK", "Memory", 0xfffc0010, 4, base=16, bitRange=13
-sfr = "US0_IMR.RIIC", "Memory", 0xfffc0010, 4, base=16, bitRange=16
-sfr = "US0_IMR.DSRIC", "Memory", 0xfffc0010, 4, base=16, bitRange=17
-sfr = "US0_IMR.DCDIC", "Memory", 0xfffc0010, 4, base=16, bitRange=18
-sfr = "US0_IMR.CTSIC", "Memory", 0xfffc0010, 4, base=16, bitRange=19
-sfr = "US0_CSR", "Memory", 0xfffc0014, 4, base=16
-sfr = "US0_CSR.RXRDY", "Memory", 0xfffc0014, 4, base=16, bitRange=0
-sfr = "US0_CSR.TXRDY", "Memory", 0xfffc0014, 4, base=16, bitRange=1
-sfr = "US0_CSR.RXBRK", "Memory", 0xfffc0014, 4, base=16, bitRange=2
-sfr = "US0_CSR.ENDRX", "Memory", 0xfffc0014, 4, base=16, bitRange=3
-sfr = "US0_CSR.ENDTX", "Memory", 0xfffc0014, 4, base=16, bitRange=4
-sfr = "US0_CSR.OVRE", "Memory", 0xfffc0014, 4, base=16, bitRange=5
-sfr = "US0_CSR.FRAME", "Memory", 0xfffc0014, 4, base=16, bitRange=6
-sfr = "US0_CSR.PARE", "Memory", 0xfffc0014, 4, base=16, bitRange=7
-sfr = "US0_CSR.TIMEOUT", "Memory", 0xfffc0014, 4, base=16, bitRange=8
-sfr = "US0_CSR.TXEMPTY", "Memory", 0xfffc0014, 4, base=16, bitRange=9
-sfr = "US0_CSR.ITERATION", "Memory", 0xfffc0014, 4, base=16, bitRange=10
-sfr = "US0_CSR.TXBUFE", "Memory", 0xfffc0014, 4, base=16, bitRange=11
-sfr = "US0_CSR.RXBUFF", "Memory", 0xfffc0014, 4, base=16, bitRange=12
-sfr = "US0_CSR.NACK", "Memory", 0xfffc0014, 4, base=16, bitRange=13
-sfr = "US0_CSR.RIIC", "Memory", 0xfffc0014, 4, base=16, bitRange=16
-sfr = "US0_CSR.DSRIC", "Memory", 0xfffc0014, 4, base=16, bitRange=17
-sfr = "US0_CSR.DCDIC", "Memory", 0xfffc0014, 4, base=16, bitRange=18
-sfr = "US0_CSR.CTSIC", "Memory", 0xfffc0014, 4, base=16, bitRange=19
-sfr = "US0_CSR.RI", "Memory", 0xfffc0014, 4, base=16, bitRange=20
-sfr = "US0_CSR.DSR", "Memory", 0xfffc0014, 4, base=16, bitRange=21
-sfr = "US0_CSR.DCD", "Memory", 0xfffc0014, 4, base=16, bitRange=22
-sfr = "US0_CSR.CTS", "Memory", 0xfffc0014, 4, base=16, bitRange=23
-sfr = "US0_RHR", "Memory", 0xfffc0018, 4, base=16
-sfr = "US0_THR", "Memory", 0xfffc001c, 4, base=16
-sfr = "US0_BRGR", "Memory", 0xfffc0020, 4, base=16
-sfr = "US0_RTOR", "Memory", 0xfffc0024, 4, base=16
-sfr = "US0_TTGR", "Memory", 0xfffc0028, 4, base=16
-sfr = "US0_FIDI", "Memory", 0xfffc0040, 4, base=16
-sfr = "US0_NER", "Memory", 0xfffc0044, 4, base=16
-sfr = "US0_IF", "Memory", 0xfffc004c, 4, base=16
-; ========== Register definition for TWI peripheral ==========
-sfr = "TWI_CR", "Memory", 0xfffb8000, 4, base=16
-sfr = "TWI_CR.START", "Memory", 0xfffb8000, 4, base=16, bitRange=0
-sfr = "TWI_CR.STOP", "Memory", 0xfffb8000, 4, base=16, bitRange=1
-sfr = "TWI_CR.MSEN", "Memory", 0xfffb8000, 4, base=16, bitRange=2
-sfr = "TWI_CR.MSDIS", "Memory", 0xfffb8000, 4, base=16, bitRange=3
-sfr = "TWI_CR.SWRST", "Memory", 0xfffb8000, 4, base=16, bitRange=7
-sfr = "TWI_MMR", "Memory", 0xfffb8004, 4, base=16
-sfr = "TWI_MMR.IADRSZ", "Memory", 0xfffb8004, 4, base=16, bitRange=8-9
-sfr = "TWI_MMR.MREAD", "Memory", 0xfffb8004, 4, base=16, bitRange=12
-sfr = "TWI_MMR.DADR", "Memory", 0xfffb8004, 4, base=16, bitRange=16-22
-sfr = "TWI_IADR", "Memory", 0xfffb800c, 4, base=16
-sfr = "TWI_CWGR", "Memory", 0xfffb8010, 4, base=16
-sfr = "TWI_CWGR.CLDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=0-7
-sfr = "TWI_CWGR.CHDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=8-15
-sfr = "TWI_CWGR.CKDIV", "Memory", 0xfffb8010, 4, base=16, bitRange=16-18
-sfr = "TWI_SR", "Memory", 0xfffb8020, 4, base=16
-sfr = "TWI_SR.TXCOMP", "Memory", 0xfffb8020, 4, base=16, bitRange=0
-sfr = "TWI_SR.RXRDY", "Memory", 0xfffb8020, 4, base=16, bitRange=1
-sfr = "TWI_SR.TXRDY", "Memory", 0xfffb8020, 4, base=16, bitRange=2
-sfr = "TWI_SR.OVRE", "Memory", 0xfffb8020, 4, base=16, bitRange=6
-sfr = "TWI_SR.UNRE", "Memory", 0xfffb8020, 4, base=16, bitRange=7
-sfr = "TWI_SR.NACK", "Memory", 0xfffb8020, 4, base=16, bitRange=8
-sfr = "TWI_IER", "Memory", 0xfffb8024, 4, base=16
-sfr = "TWI_IER.TXCOMP", "Memory", 0xfffb8024, 4, base=16, bitRange=0
-sfr = "TWI_IER.RXRDY", "Memory", 0xfffb8024, 4, base=16, bitRange=1
-sfr = "TWI_IER.TXRDY", "Memory", 0xfffb8024, 4, base=16, bitRange=2
-sfr = "TWI_IER.OVRE", "Memory", 0xfffb8024, 4, base=16, bitRange=6
-sfr = "TWI_IER.UNRE", "Memory", 0xfffb8024, 4, base=16, bitRange=7
-sfr = "TWI_IER.NACK", "Memory", 0xfffb8024, 4, base=16, bitRange=8
-sfr = "TWI_IDR", "Memory", 0xfffb8028, 4, base=16
-sfr = "TWI_IDR.TXCOMP", "Memory", 0xfffb8028, 4, base=16, bitRange=0
-sfr = "TWI_IDR.RXRDY", "Memory", 0xfffb8028, 4, base=16, bitRange=1
-sfr = "TWI_IDR.TXRDY", "Memory", 0xfffb8028, 4, base=16, bitRange=2
-sfr = "TWI_IDR.OVRE", "Memory", 0xfffb8028, 4, base=16, bitRange=6
-sfr = "TWI_IDR.UNRE", "Memory", 0xfffb8028, 4, base=16, bitRange=7
-sfr = "TWI_IDR.NACK", "Memory", 0xfffb8028, 4, base=16, bitRange=8
-sfr = "TWI_IMR", "Memory", 0xfffb802c, 4, base=16
-sfr = "TWI_IMR.TXCOMP", "Memory", 0xfffb802c, 4, base=16, bitRange=0
-sfr = "TWI_IMR.RXRDY", "Memory", 0xfffb802c, 4, base=16, bitRange=1
-sfr = "TWI_IMR.TXRDY", "Memory", 0xfffb802c, 4, base=16, bitRange=2
-sfr = "TWI_IMR.OVRE", "Memory", 0xfffb802c, 4, base=16, bitRange=6
-sfr = "TWI_IMR.UNRE", "Memory", 0xfffb802c, 4, base=16, bitRange=7
-sfr = "TWI_IMR.NACK", "Memory", 0xfffb802c, 4, base=16, bitRange=8
-sfr = "TWI_RHR", "Memory", 0xfffb8030, 4, base=16
-sfr = "TWI_THR", "Memory", 0xfffb8034, 4, base=16
-; ========== Register definition for TC0 peripheral ==========
-sfr = "TC0_CCR", "Memory", 0xfffa0000, 4, base=16
-sfr = "TC0_CCR.CLKEN", "Memory", 0xfffa0000, 4, base=16, bitRange=0
-sfr = "TC0_CCR.CLKDIS", "Memory", 0xfffa0000, 4, base=16, bitRange=1
-sfr = "TC0_CCR.SWTRG", "Memory", 0xfffa0000, 4, base=16, bitRange=2
-sfr = "TC0_CMR", "Memory", 0xfffa0004, 4, base=16
-sfr = "TC0_CMR.CLKS", "Memory", 0xfffa0004, 4, base=16, bitRange=0-2
-sfr = "TC0_CMR.CLKI", "Memory", 0xfffa0004, 4, base=16, bitRange=3
-sfr = "TC0_CMR.BURST", "Memory", 0xfffa0004, 4, base=16, bitRange=4-5
-sfr = "TC0_CMR.CPCSTOP", "Memory", 0xfffa0004, 4, base=16, bitRange=6
-sfr = "TC0_CMR.LDBSTOP", "Memory", 0xfffa0004, 4, base=16, bitRange=6
-sfr = "TC0_CMR.CPCDIS", "Memory", 0xfffa0004, 4, base=16, bitRange=7
-sfr = "TC0_CMR.LDBDIS", "Memory", 0xfffa0004, 4, base=16, bitRange=7
-sfr = "TC0_CMR.ETRGEDG", "Memory", 0xfffa0004, 4, base=16, bitRange=8-9
-sfr = "TC0_CMR.EEVTEDG", "Memory", 0xfffa0004, 4, base=16, bitRange=8-9
-sfr = "TC0_CMR.EEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=10-11
-sfr = "TC0_CMR.ABETRG", "Memory", 0xfffa0004, 4, base=16, bitRange=10
-sfr = "TC0_CMR.ENETRG", "Memory", 0xfffa0004, 4, base=16, bitRange=12
-sfr = "TC0_CMR.WAVESEL", "Memory", 0xfffa0004, 4, base=16, bitRange=13-14
-sfr = "TC0_CMR.CPCTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=14
-sfr = "TC0_CMR.WAVE", "Memory", 0xfffa0004, 4, base=16, bitRange=15
-sfr = "TC0_CMR.ACPA", "Memory", 0xfffa0004, 4, base=16, bitRange=16-17
-sfr = "TC0_CMR.LDRA", "Memory", 0xfffa0004, 4, base=16, bitRange=16-17
-sfr = "TC0_CMR.ACPC", "Memory", 0xfffa0004, 4, base=16, bitRange=18-19
-sfr = "TC0_CMR.LDRB", "Memory", 0xfffa0004, 4, base=16, bitRange=18-19
-sfr = "TC0_CMR.AEEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=20-21
-sfr = "TC0_CMR.ASWTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=22-23
-sfr = "TC0_CMR.BCPB", "Memory", 0xfffa0004, 4, base=16, bitRange=24-25
-sfr = "TC0_CMR.BCPC", "Memory", 0xfffa0004, 4, base=16, bitRange=26-27
-sfr = "TC0_CMR.BEEVT", "Memory", 0xfffa0004, 4, base=16, bitRange=28-29
-sfr = "TC0_CMR.BSWTRG", "Memory", 0xfffa0004, 4, base=16, bitRange=30-31
-sfr = "TC0_CV", "Memory", 0xfffa0010, 4, base=16
-sfr = "TC0_RA", "Memory", 0xfffa0014, 4, base=16
-sfr = "TC0_RB", "Memory", 0xfffa0018, 4, base=16
-sfr = "TC0_RC", "Memory", 0xfffa001c, 4, base=16
-sfr = "TC0_SR", "Memory", 0xfffa0020, 4, base=16
-sfr = "TC0_SR.COVFS", "Memory", 0xfffa0020, 4, base=16, bitRange=0
-sfr = "TC0_SR.LOVRS", "Memory", 0xfffa0020, 4, base=16, bitRange=1
-sfr = "TC0_SR.CPAS", "Memory", 0xfffa0020, 4, base=16, bitRange=2
-sfr = "TC0_SR.CPBS", "Memory", 0xfffa0020, 4, base=16, bitRange=3
-sfr = "TC0_SR.CPCS", "Memory", 0xfffa0020, 4, base=16, bitRange=4
-sfr = "TC0_SR.LDRAS", "Memory", 0xfffa0020, 4, base=16, bitRange=5
-sfr = "TC0_SR.LDRBS", "Memory", 0xfffa0020, 4, base=16, bitRange=6
-sfr = "TC0_SR.ETRGS", "Memory", 0xfffa0020, 4, base=16, bitRange=7
-sfr = "TC0_SR.CLKSTA", "Memory", 0xfffa0020, 4, base=16, bitRange=16
-sfr = "TC0_SR.MTIOA", "Memory", 0xfffa0020, 4, base=16, bitRange=17
-sfr = "TC0_SR.MTIOB", "Memory", 0xfffa0020, 4, base=16, bitRange=18
-sfr = "TC0_IER", "Memory", 0xfffa0024, 4, base=16
-sfr = "TC0_IER.COVFS", "Memory", 0xfffa0024, 4, base=16, bitRange=0
-sfr = "TC0_IER.LOVRS", "Memory", 0xfffa0024, 4, base=16, bitRange=1
-sfr = "TC0_IER.CPAS", "Memory", 0xfffa0024, 4, base=16, bitRange=2
-sfr = "TC0_IER.CPBS", "Memory", 0xfffa0024, 4, base=16, bitRange=3
-sfr = "TC0_IER.CPCS", "Memory", 0xfffa0024, 4, base=16, bitRange=4
-sfr = "TC0_IER.LDRAS", "Memory", 0xfffa0024, 4, base=16, bitRange=5
-sfr = "TC0_IER.LDRBS", "Memory", 0xfffa0024, 4, base=16, bitRange=6
-sfr = "TC0_IER.ETRGS", "Memory", 0xfffa0024, 4, base=16, bitRange=7
-sfr = "TC0_IDR", "Memory", 0xfffa0028, 4, base=16
-sfr = "TC0_IDR.COVFS", "Memory", 0xfffa0028, 4, base=16, bitRange=0
-sfr = "TC0_IDR.LOVRS", "Memory", 0xfffa0028, 4, base=16, bitRange=1
-sfr = "TC0_IDR.CPAS", "Memory", 0xfffa0028, 4, base=16, bitRange=2
-sfr = "TC0_IDR.CPBS", "Memory", 0xfffa0028, 4, base=16, bitRange=3
-sfr = "TC0_IDR.CPCS", "Memory", 0xfffa0028, 4, base=16, bitRange=4
-sfr = "TC0_IDR.LDRAS", "Memory", 0xfffa0028, 4, base=16, bitRange=5
-sfr = "TC0_IDR.LDRBS", "Memory", 0xfffa0028, 4, base=16, bitRange=6
-sfr = "TC0_IDR.ETRGS", "Memory", 0xfffa0028, 4, base=16, bitRange=7
-sfr = "TC0_IMR", "Memory", 0xfffa002c, 4, base=16
-sfr = "TC0_IMR.COVFS", "Memory", 0xfffa002c, 4, base=16, bitRange=0
-sfr = "TC0_IMR.LOVRS", "Memory", 0xfffa002c, 4, base=16, bitRange=1
-sfr = "TC0_IMR.CPAS", "Memory", 0xfffa002c, 4, base=16, bitRange=2
-sfr = "TC0_IMR.CPBS", "Memory", 0xfffa002c, 4, base=16, bitRange=3
-sfr = "TC0_IMR.CPCS", "Memory", 0xfffa002c, 4, base=16, bitRange=4
-sfr = "TC0_IMR.LDRAS", "Memory", 0xfffa002c, 4, base=16, bitRange=5
-sfr = "TC0_IMR.LDRBS", "Memory", 0xfffa002c, 4, base=16, bitRange=6
-sfr = "TC0_IMR.ETRGS", "Memory", 0xfffa002c, 4, base=16, bitRange=7
-; ========== Register definition for TC1 peripheral ==========
-sfr = "TC1_CCR", "Memory", 0xfffa0040, 4, base=16
-sfr = "TC1_CCR.CLKEN", "Memory", 0xfffa0040, 4, base=16, bitRange=0
-sfr = "TC1_CCR.CLKDIS", "Memory", 0xfffa0040, 4, base=16, bitRange=1
-sfr = "TC1_CCR.SWTRG", "Memory", 0xfffa0040, 4, base=16, bitRange=2
-sfr = "TC1_CMR", "Memory", 0xfffa0044, 4, base=16
-sfr = "TC1_CMR.CLKS", "Memory", 0xfffa0044, 4, base=16, bitRange=0-2
-sfr = "TC1_CMR.CLKI", "Memory", 0xfffa0044, 4, base=16, bitRange=3
-sfr = "TC1_CMR.BURST", "Memory", 0xfffa0044, 4, base=16, bitRange=4-5
-sfr = "TC1_CMR.CPCSTOP", "Memory", 0xfffa0044, 4, base=16, bitRange=6
-sfr = "TC1_CMR.LDBSTOP", "Memory", 0xfffa0044, 4, base=16, bitRange=6
-sfr = "TC1_CMR.CPCDIS", "Memory", 0xfffa0044, 4, base=16, bitRange=7
-sfr = "TC1_CMR.LDBDIS", "Memory", 0xfffa0044, 4, base=16, bitRange=7
-sfr = "TC1_CMR.ETRGEDG", "Memory", 0xfffa0044, 4, base=16, bitRange=8-9
-sfr = "TC1_CMR.EEVTEDG", "Memory", 0xfffa0044, 4, base=16, bitRange=8-9
-sfr = "TC1_CMR.EEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=10-11
-sfr = "TC1_CMR.ABETRG", "Memory", 0xfffa0044, 4, base=16, bitRange=10
-sfr = "TC1_CMR.ENETRG", "Memory", 0xfffa0044, 4, base=16, bitRange=12
-sfr = "TC1_CMR.WAVESEL", "Memory", 0xfffa0044, 4, base=16, bitRange=13-14
-sfr = "TC1_CMR.CPCTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=14
-sfr = "TC1_CMR.WAVE", "Memory", 0xfffa0044, 4, base=16, bitRange=15
-sfr = "TC1_CMR.ACPA", "Memory", 0xfffa0044, 4, base=16, bitRange=16-17
-sfr = "TC1_CMR.LDRA", "Memory", 0xfffa0044, 4, base=16, bitRange=16-17
-sfr = "TC1_CMR.ACPC", "Memory", 0xfffa0044, 4, base=16, bitRange=18-19
-sfr = "TC1_CMR.LDRB", "Memory", 0xfffa0044, 4, base=16, bitRange=18-19
-sfr = "TC1_CMR.AEEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=20-21
-sfr = "TC1_CMR.ASWTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=22-23
-sfr = "TC1_CMR.BCPB", "Memory", 0xfffa0044, 4, base=16, bitRange=24-25
-sfr = "TC1_CMR.BCPC", "Memory", 0xfffa0044, 4, base=16, bitRange=26-27
-sfr = "TC1_CMR.BEEVT", "Memory", 0xfffa0044, 4, base=16, bitRange=28-29
-sfr = "TC1_CMR.BSWTRG", "Memory", 0xfffa0044, 4, base=16, bitRange=30-31
-sfr = "TC1_CV", "Memory", 0xfffa0050, 4, base=16
-sfr = "TC1_RA", "Memory", 0xfffa0054, 4, base=16
-sfr = "TC1_RB", "Memory", 0xfffa0058, 4, base=16
-sfr = "TC1_RC", "Memory", 0xfffa005c, 4, base=16
-sfr = "TC1_SR", "Memory", 0xfffa0060, 4, base=16
-sfr = "TC1_SR.COVFS", "Memory", 0xfffa0060, 4, base=16, bitRange=0
-sfr = "TC1_SR.LOVRS", "Memory", 0xfffa0060, 4, base=16, bitRange=1
-sfr = "TC1_SR.CPAS", "Memory", 0xfffa0060, 4, base=16, bitRange=2
-sfr = "TC1_SR.CPBS", "Memory", 0xfffa0060, 4, base=16, bitRange=3
-sfr = "TC1_SR.CPCS", "Memory", 0xfffa0060, 4, base=16, bitRange=4
-sfr = "TC1_SR.LDRAS", "Memory", 0xfffa0060, 4, base=16, bitRange=5
-sfr = "TC1_SR.LDRBS", "Memory", 0xfffa0060, 4, base=16, bitRange=6
-sfr = "TC1_SR.ETRGS", "Memory", 0xfffa0060, 4, base=16, bitRange=7
-sfr = "TC1_SR.CLKSTA", "Memory", 0xfffa0060, 4, base=16, bitRange=16
-sfr = "TC1_SR.MTIOA", "Memory", 0xfffa0060, 4, base=16, bitRange=17
-sfr = "TC1_SR.MTIOB", "Memory", 0xfffa0060, 4, base=16, bitRange=18
-sfr = "TC1_IER", "Memory", 0xfffa0064, 4, base=16
-sfr = "TC1_IER.COVFS", "Memory", 0xfffa0064, 4, base=16, bitRange=0
-sfr = "TC1_IER.LOVRS", "Memory", 0xfffa0064, 4, base=16, bitRange=1
-sfr = "TC1_IER.CPAS", "Memory", 0xfffa0064, 4, base=16, bitRange=2
-sfr = "TC1_IER.CPBS", "Memory", 0xfffa0064, 4, base=16, bitRange=3
-sfr = "TC1_IER.CPCS", "Memory", 0xfffa0064, 4, base=16, bitRange=4
-sfr = "TC1_IER.LDRAS", "Memory", 0xfffa0064, 4, base=16, bitRange=5
-sfr = "TC1_IER.LDRBS", "Memory", 0xfffa0064, 4, base=16, bitRange=6
-sfr = "TC1_IER.ETRGS", "Memory", 0xfffa0064, 4, base=16, bitRange=7
-sfr = "TC1_IDR", "Memory", 0xfffa0068, 4, base=16
-sfr = "TC1_IDR.COVFS", "Memory", 0xfffa0068, 4, base=16, bitRange=0
-sfr = "TC1_IDR.LOVRS", "Memory", 0xfffa0068, 4, base=16, bitRange=1
-sfr = "TC1_IDR.CPAS", "Memory", 0xfffa0068, 4, base=16, bitRange=2
-sfr = "TC1_IDR.CPBS", "Memory", 0xfffa0068, 4, base=16, bitRange=3
-sfr = "TC1_IDR.CPCS", "Memory", 0xfffa0068, 4, base=16, bitRange=4
-sfr = "TC1_IDR.LDRAS", "Memory", 0xfffa0068, 4, base=16, bitRange=5
-sfr = "TC1_IDR.LDRBS", "Memory", 0xfffa0068, 4, base=16, bitRange=6
-sfr = "TC1_IDR.ETRGS", "Memory", 0xfffa0068, 4, base=16, bitRange=7
-sfr = "TC1_IMR", "Memory", 0xfffa006c, 4, base=16
-sfr = "TC1_IMR.COVFS", "Memory", 0xfffa006c, 4, base=16, bitRange=0
-sfr = "TC1_IMR.LOVRS", "Memory", 0xfffa006c, 4, base=16, bitRange=1
-sfr = "TC1_IMR.CPAS", "Memory", 0xfffa006c, 4, base=16, bitRange=2
-sfr = "TC1_IMR.CPBS", "Memory", 0xfffa006c, 4, base=16, bitRange=3
-sfr = "TC1_IMR.CPCS", "Memory", 0xfffa006c, 4, base=16, bitRange=4
-sfr = "TC1_IMR.LDRAS", "Memory", 0xfffa006c, 4, base=16, bitRange=5
-sfr = "TC1_IMR.LDRBS", "Memory", 0xfffa006c, 4, base=16, bitRange=6
-sfr = "TC1_IMR.ETRGS", "Memory", 0xfffa006c, 4, base=16, bitRange=7
-; ========== Register definition for TC2 peripheral ==========
-sfr = "TC2_CCR", "Memory", 0xfffa0080, 4, base=16
-sfr = "TC2_CCR.CLKEN", "Memory", 0xfffa0080, 4, base=16, bitRange=0
-sfr = "TC2_CCR.CLKDIS", "Memory", 0xfffa0080, 4, base=16, bitRange=1
-sfr = "TC2_CCR.SWTRG", "Memory", 0xfffa0080, 4, base=16, bitRange=2
-sfr = "TC2_CMR", "Memory", 0xfffa0084, 4, base=16
-sfr = "TC2_CMR.CLKS", "Memory", 0xfffa0084, 4, base=16, bitRange=0-2
-sfr = "TC2_CMR.CLKI", "Memory", 0xfffa0084, 4, base=16, bitRange=3
-sfr = "TC2_CMR.BURST", "Memory", 0xfffa0084, 4, base=16, bitRange=4-5
-sfr = "TC2_CMR.CPCSTOP", "Memory", 0xfffa0084, 4, base=16, bitRange=6
-sfr = "TC2_CMR.LDBSTOP", "Memory", 0xfffa0084, 4, base=16, bitRange=6
-sfr = "TC2_CMR.CPCDIS", "Memory", 0xfffa0084, 4, base=16, bitRange=7
-sfr = "TC2_CMR.LDBDIS", "Memory", 0xfffa0084, 4, base=16, bitRange=7
-sfr = "TC2_CMR.ETRGEDG", "Memory", 0xfffa0084, 4, base=16, bitRange=8-9
-sfr = "TC2_CMR.EEVTEDG", "Memory", 0xfffa0084, 4, base=16, bitRange=8-9
-sfr = "TC2_CMR.EEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=10-11
-sfr = "TC2_CMR.ABETRG", "Memory", 0xfffa0084, 4, base=16, bitRange=10
-sfr = "TC2_CMR.ENETRG", "Memory", 0xfffa0084, 4, base=16, bitRange=12
-sfr = "TC2_CMR.WAVESEL", "Memory", 0xfffa0084, 4, base=16, bitRange=13-14
-sfr = "TC2_CMR.CPCTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=14
-sfr = "TC2_CMR.WAVE", "Memory", 0xfffa0084, 4, base=16, bitRange=15
-sfr = "TC2_CMR.ACPA", "Memory", 0xfffa0084, 4, base=16, bitRange=16-17
-sfr = "TC2_CMR.LDRA", "Memory", 0xfffa0084, 4, base=16, bitRange=16-17
-sfr = "TC2_CMR.ACPC", "Memory", 0xfffa0084, 4, base=16, bitRange=18-19
-sfr = "TC2_CMR.LDRB", "Memory", 0xfffa0084, 4, base=16, bitRange=18-19
-sfr = "TC2_CMR.AEEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=20-21
-sfr = "TC2_CMR.ASWTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=22-23
-sfr = "TC2_CMR.BCPB", "Memory", 0xfffa0084, 4, base=16, bitRange=24-25
-sfr = "TC2_CMR.BCPC", "Memory", 0xfffa0084, 4, base=16, bitRange=26-27
-sfr = "TC2_CMR.BEEVT", "Memory", 0xfffa0084, 4, base=16, bitRange=28-29
-sfr = "TC2_CMR.BSWTRG", "Memory", 0xfffa0084, 4, base=16, bitRange=30-31
-sfr = "TC2_CV", "Memory", 0xfffa0090, 4, base=16
-sfr = "TC2_RA", "Memory", 0xfffa0094, 4, base=16
-sfr = "TC2_RB", "Memory", 0xfffa0098, 4, base=16
-sfr = "TC2_RC", "Memory", 0xfffa009c, 4, base=16
-sfr = "TC2_SR", "Memory", 0xfffa00a0, 4, base=16
-sfr = "TC2_SR.COVFS", "Memory", 0xfffa00a0, 4, base=16, bitRange=0
-sfr = "TC2_SR.LOVRS", "Memory", 0xfffa00a0, 4, base=16, bitRange=1
-sfr = "TC2_SR.CPAS", "Memory", 0xfffa00a0, 4, base=16, bitRange=2
-sfr = "TC2_SR.CPBS", "Memory", 0xfffa00a0, 4, base=16, bitRange=3
-sfr = "TC2_SR.CPCS", "Memory", 0xfffa00a0, 4, base=16, bitRange=4
-sfr = "TC2_SR.LDRAS", "Memory", 0xfffa00a0, 4, base=16, bitRange=5
-sfr = "TC2_SR.LDRBS", "Memory", 0xfffa00a0, 4, base=16, bitRange=6
-sfr = "TC2_SR.ETRGS", "Memory", 0xfffa00a0, 4, base=16, bitRange=7
-sfr = "TC2_SR.CLKSTA", "Memory", 0xfffa00a0, 4, base=16, bitRange=16
-sfr = "TC2_SR.MTIOA", "Memory", 0xfffa00a0, 4, base=16, bitRange=17
-sfr = "TC2_SR.MTIOB", "Memory", 0xfffa00a0, 4, base=16, bitRange=18
-sfr = "TC2_IER", "Memory", 0xfffa00a4, 4, base=16
-sfr = "TC2_IER.COVFS", "Memory", 0xfffa00a4, 4, base=16, bitRange=0
-sfr = "TC2_IER.LOVRS", "Memory", 0xfffa00a4, 4, base=16, bitRange=1
-sfr = "TC2_IER.CPAS", "Memory", 0xfffa00a4, 4, base=16, bitRange=2
-sfr = "TC2_IER.CPBS", "Memory", 0xfffa00a4, 4, base=16, bitRange=3
-sfr = "TC2_IER.CPCS", "Memory", 0xfffa00a4, 4, base=16, bitRange=4
-sfr = "TC2_IER.LDRAS", "Memory", 0xfffa00a4, 4, base=16, bitRange=5
-sfr = "TC2_IER.LDRBS", "Memory", 0xfffa00a4, 4, base=16, bitRange=6
-sfr = "TC2_IER.ETRGS", "Memory", 0xfffa00a4, 4, base=16, bitRange=7
-sfr = "TC2_IDR", "Memory", 0xfffa00a8, 4, base=16
-sfr = "TC2_IDR.COVFS", "Memory", 0xfffa00a8, 4, base=16, bitRange=0
-sfr = "TC2_IDR.LOVRS", "Memory", 0xfffa00a8, 4, base=16, bitRange=1
-sfr = "TC2_IDR.CPAS", "Memory", 0xfffa00a8, 4, base=16, bitRange=2
-sfr = "TC2_IDR.CPBS", "Memory", 0xfffa00a8, 4, base=16, bitRange=3
-sfr = "TC2_IDR.CPCS", "Memory", 0xfffa00a8, 4, base=16, bitRange=4
-sfr = "TC2_IDR.LDRAS", "Memory", 0xfffa00a8, 4, base=16, bitRange=5
-sfr = "TC2_IDR.LDRBS", "Memory", 0xfffa00a8, 4, base=16, bitRange=6
-sfr = "TC2_IDR.ETRGS", "Memory", 0xfffa00a8, 4, base=16, bitRange=7
-sfr = "TC2_IMR", "Memory", 0xfffa00ac, 4, base=16
-sfr = "TC2_IMR.COVFS", "Memory", 0xfffa00ac, 4, base=16, bitRange=0
-sfr = "TC2_IMR.LOVRS", "Memory", 0xfffa00ac, 4, base=16, bitRange=1
-sfr = "TC2_IMR.CPAS", "Memory", 0xfffa00ac, 4, base=16, bitRange=2
-sfr = "TC2_IMR.CPBS", "Memory", 0xfffa00ac, 4, base=16, bitRange=3
-sfr = "TC2_IMR.CPCS", "Memory", 0xfffa00ac, 4, base=16, bitRange=4
-sfr = "TC2_IMR.LDRAS", "Memory", 0xfffa00ac, 4, base=16, bitRange=5
-sfr = "TC2_IMR.LDRBS", "Memory", 0xfffa00ac, 4, base=16, bitRange=6
-sfr = "TC2_IMR.ETRGS", "Memory", 0xfffa00ac, 4, base=16, bitRange=7
-; ========== Register definition for TCB peripheral ==========
-sfr = "TCB_BCR", "Memory", 0xfffa00c0, 4, base=16
-sfr = "TCB_BCR.SYNC", "Memory", 0xfffa00c0, 4, base=16, bitRange=0
-sfr = "TCB_BMR", "Memory", 0xfffa00c4, 4, base=16
-sfr = "TCB_BMR.TC0XC0S", "Memory", 0xfffa00c4, 4, base=16, bitRange=0-1
-sfr = "TCB_BMR.TC1XC1S", "Memory", 0xfffa00c4, 4, base=16, bitRange=2-3
-sfr = "TCB_BMR.TC2XC2S", "Memory", 0xfffa00c4, 4, base=16, bitRange=4-5
-; ========== Register definition for PWMC_CH3 peripheral ==========
-sfr = "PWMC_CH3_CMR", "Memory", 0xfffcc260, 4, base=16
-sfr = "PWMC_CH3_CMR.CPRE", "Memory", 0xfffcc260, 4, base=16, bitRange=0-3
-sfr = "PWMC_CH3_CMR.CALG", "Memory", 0xfffcc260, 4, base=16, bitRange=8
-sfr = "PWMC_CH3_CMR.CPOL", "Memory", 0xfffcc260, 4, base=16, bitRange=9
-sfr = "PWMC_CH3_CMR.CPD", "Memory", 0xfffcc260, 4, base=16, bitRange=10
-sfr = "PWMC_CH3_CDTYR", "Memory", 0xfffcc264, 4, base=16
-sfr = "PWMC_CH3_CDTYR.CDTY", "Memory", 0xfffcc264, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH3_CPRDR", "Memory", 0xfffcc268, 4, base=16
-sfr = "PWMC_CH3_CPRDR.CPRD", "Memory", 0xfffcc268, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH3_CCNTR", "Memory", 0xfffcc26c, 4, base=16
-sfr = "PWMC_CH3_CCNTR.CCNT", "Memory", 0xfffcc26c, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH3_CUPDR", "Memory", 0xfffcc270, 4, base=16
-sfr = "PWMC_CH3_CUPDR.CUPD", "Memory", 0xfffcc270, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH3_Reserved", "Memory", 0xfffcc274, 4, base=16
-; ========== Register definition for PWMC_CH2 peripheral ==========
-sfr = "PWMC_CH2_CMR", "Memory", 0xfffcc240, 4, base=16
-sfr = "PWMC_CH2_CMR.CPRE", "Memory", 0xfffcc240, 4, base=16, bitRange=0-3
-sfr = "PWMC_CH2_CMR.CALG", "Memory", 0xfffcc240, 4, base=16, bitRange=8
-sfr = "PWMC_CH2_CMR.CPOL", "Memory", 0xfffcc240, 4, base=16, bitRange=9
-sfr = "PWMC_CH2_CMR.CPD", "Memory", 0xfffcc240, 4, base=16, bitRange=10
-sfr = "PWMC_CH2_CDTYR", "Memory", 0xfffcc244, 4, base=16
-sfr = "PWMC_CH2_CDTYR.CDTY", "Memory", 0xfffcc244, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH2_CPRDR", "Memory", 0xfffcc248, 4, base=16
-sfr = "PWMC_CH2_CPRDR.CPRD", "Memory", 0xfffcc248, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH2_CCNTR", "Memory", 0xfffcc24c, 4, base=16
-sfr = "PWMC_CH2_CCNTR.CCNT", "Memory", 0xfffcc24c, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH2_CUPDR", "Memory", 0xfffcc250, 4, base=16
-sfr = "PWMC_CH2_CUPDR.CUPD", "Memory", 0xfffcc250, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH2_Reserved", "Memory", 0xfffcc254, 4, base=16
-; ========== Register definition for PWMC_CH1 peripheral ==========
-sfr = "PWMC_CH1_CMR", "Memory", 0xfffcc220, 4, base=16
-sfr = "PWMC_CH1_CMR.CPRE", "Memory", 0xfffcc220, 4, base=16, bitRange=0-3
-sfr = "PWMC_CH1_CMR.CALG", "Memory", 0xfffcc220, 4, base=16, bitRange=8
-sfr = "PWMC_CH1_CMR.CPOL", "Memory", 0xfffcc220, 4, base=16, bitRange=9
-sfr = "PWMC_CH1_CMR.CPD", "Memory", 0xfffcc220, 4, base=16, bitRange=10
-sfr = "PWMC_CH1_CDTYR", "Memory", 0xfffcc224, 4, base=16
-sfr = "PWMC_CH1_CDTYR.CDTY", "Memory", 0xfffcc224, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH1_CPRDR", "Memory", 0xfffcc228, 4, base=16
-sfr = "PWMC_CH1_CPRDR.CPRD", "Memory", 0xfffcc228, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH1_CCNTR", "Memory", 0xfffcc22c, 4, base=16
-sfr = "PWMC_CH1_CCNTR.CCNT", "Memory", 0xfffcc22c, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH1_CUPDR", "Memory", 0xfffcc230, 4, base=16
-sfr = "PWMC_CH1_CUPDR.CUPD", "Memory", 0xfffcc230, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH1_Reserved", "Memory", 0xfffcc234, 4, base=16
-; ========== Register definition for PWMC_CH0 peripheral ==========
-sfr = "PWMC_CH0_CMR", "Memory", 0xfffcc200, 4, base=16
-sfr = "PWMC_CH0_CMR.CPRE", "Memory", 0xfffcc200, 4, base=16, bitRange=0-3
-sfr = "PWMC_CH0_CMR.CALG", "Memory", 0xfffcc200, 4, base=16, bitRange=8
-sfr = "PWMC_CH0_CMR.CPOL", "Memory", 0xfffcc200, 4, base=16, bitRange=9
-sfr = "PWMC_CH0_CMR.CPD", "Memory", 0xfffcc200, 4, base=16, bitRange=10
-sfr = "PWMC_CH0_CDTYR", "Memory", 0xfffcc204, 4, base=16
-sfr = "PWMC_CH0_CDTYR.CDTY", "Memory", 0xfffcc204, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH0_CPRDR", "Memory", 0xfffcc208, 4, base=16
-sfr = "PWMC_CH0_CPRDR.CPRD", "Memory", 0xfffcc208, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH0_CCNTR", "Memory", 0xfffcc20c, 4, base=16
-sfr = "PWMC_CH0_CCNTR.CCNT", "Memory", 0xfffcc20c, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH0_CUPDR", "Memory", 0xfffcc210, 4, base=16
-sfr = "PWMC_CH0_CUPDR.CUPD", "Memory", 0xfffcc210, 4, base=16, bitRange=0-31
-sfr = "PWMC_CH0_Reserved", "Memory", 0xfffcc214, 4, base=16
-; ========== Register definition for PWMC peripheral ==========
-sfr = "PWMC_MR", "Memory", 0xfffcc000, 4, base=16
-sfr = "PWMC_MR.DIVA", "Memory", 0xfffcc000, 4, base=16, bitRange=0-7
-sfr = "PWMC_MR.PREA", "Memory", 0xfffcc000, 4, base=16, bitRange=8-11
-sfr = "PWMC_MR.DIVB", "Memory", 0xfffcc000, 4, base=16, bitRange=16-23
-sfr = "PWMC_MR.PREB", "Memory", 0xfffcc000, 4, base=16, bitRange=24-27
-sfr = "PWMC_ENA", "Memory", 0xfffcc004, 4, base=16
-sfr = "PWMC_ENA.CHID0", "Memory", 0xfffcc004, 4, base=16, bitRange=0
-sfr = "PWMC_ENA.CHID1", "Memory", 0xfffcc004, 4, base=16, bitRange=1
-sfr = "PWMC_ENA.CHID2", "Memory", 0xfffcc004, 4, base=16, bitRange=2
-sfr = "PWMC_ENA.CHID3", "Memory", 0xfffcc004, 4, base=16, bitRange=3
-sfr = "PWMC_DIS", "Memory", 0xfffcc008, 4, base=16
-sfr = "PWMC_DIS.CHID0", "Memory", 0xfffcc008, 4, base=16, bitRange=0
-sfr = "PWMC_DIS.CHID1", "Memory", 0xfffcc008, 4, base=16, bitRange=1
-sfr = "PWMC_DIS.CHID2", "Memory", 0xfffcc008, 4, base=16, bitRange=2
-sfr = "PWMC_DIS.CHID3", "Memory", 0xfffcc008, 4, base=16, bitRange=3
-sfr = "PWMC_SR", "Memory", 0xfffcc00c, 4, base=16
-sfr = "PWMC_SR.CHID0", "Memory", 0xfffcc00c, 4, base=16, bitRange=0
-sfr = "PWMC_SR.CHID1", "Memory", 0xfffcc00c, 4, base=16, bitRange=1
-sfr = "PWMC_SR.CHID2", "Memory", 0xfffcc00c, 4, base=16, bitRange=2
-sfr = "PWMC_SR.CHID3", "Memory", 0xfffcc00c, 4, base=16, bitRange=3
-sfr = "PWMC_IER", "Memory", 0xfffcc010, 4, base=16
-sfr = "PWMC_IER.CHID0", "Memory", 0xfffcc010, 4, base=16, bitRange=0
-sfr = "PWMC_IER.CHID1", "Memory", 0xfffcc010, 4, base=16, bitRange=1
-sfr = "PWMC_IER.CHID2", "Memory", 0xfffcc010, 4, base=16, bitRange=2
-sfr = "PWMC_IER.CHID3", "Memory", 0xfffcc010, 4, base=16, bitRange=3
-sfr = "PWMC_IDR", "Memory", 0xfffcc014, 4, base=16
-sfr = "PWMC_IDR.CHID0", "Memory", 0xfffcc014, 4, base=16, bitRange=0
-sfr = "PWMC_IDR.CHID1", "Memory", 0xfffcc014, 4, base=16, bitRange=1
-sfr = "PWMC_IDR.CHID2", "Memory", 0xfffcc014, 4, base=16, bitRange=2
-sfr = "PWMC_IDR.CHID3", "Memory", 0xfffcc014, 4, base=16, bitRange=3
-sfr = "PWMC_IMR", "Memory", 0xfffcc018, 4, base=16
-sfr = "PWMC_IMR.CHID0", "Memory", 0xfffcc018, 4, base=16, bitRange=0
-sfr = "PWMC_IMR.CHID1", "Memory", 0xfffcc018, 4, base=16, bitRange=1
-sfr = "PWMC_IMR.CHID2", "Memory", 0xfffcc018, 4, base=16, bitRange=2
-sfr = "PWMC_IMR.CHID3", "Memory", 0xfffcc018, 4, base=16, bitRange=3
-sfr = "PWMC_ISR", "Memory", 0xfffcc01c, 4, base=16
-sfr = "PWMC_ISR.CHID0", "Memory", 0xfffcc01c, 4, base=16, bitRange=0
-sfr = "PWMC_ISR.CHID1", "Memory", 0xfffcc01c, 4, base=16, bitRange=1
-sfr = "PWMC_ISR.CHID2", "Memory", 0xfffcc01c, 4, base=16, bitRange=2
-sfr = "PWMC_ISR.CHID3", "Memory", 0xfffcc01c, 4, base=16, bitRange=3
-sfr = "PWMC_VR", "Memory", 0xfffcc0fc, 4, base=16
-; ========== Register definition for UDP peripheral ==========
-sfr = "UDP_NUM", "Memory", 0xfffb0000, 4, base=16
-sfr = "UDP_NUM.NUM", "Memory", 0xfffb0000, 4, base=16, bitRange=0-10
-sfr = "UDP_NUM.ERR", "Memory", 0xfffb0000, 4, base=16, bitRange=16
-sfr = "UDP_NUM.OK", "Memory", 0xfffb0000, 4, base=16, bitRange=17
-sfr = "UDP_GLBSTATE", "Memory", 0xfffb0004, 4, base=16
-sfr = "UDP_GLBSTATE.FADDEN", "Memory", 0xfffb0004, 4, base=16, bitRange=0
-sfr = "UDP_GLBSTATE.CONFG", "Memory", 0xfffb0004, 4, base=16, bitRange=1
-sfr = "UDP_GLBSTATE.ESR", "Memory", 0xfffb0004, 4, base=16, bitRange=2
-sfr = "UDP_GLBSTATE.RSMINPR", "Memory", 0xfffb0004, 4, base=16, bitRange=3
-sfr = "UDP_GLBSTATE.RMWUPE", "Memory", 0xfffb0004, 4, base=16, bitRange=4
-sfr = "UDP_FADDR", "Memory", 0xfffb0008, 4, base=16
-sfr = "UDP_FADDR.FADD", "Memory", 0xfffb0008, 4, base=16, bitRange=0-7
-sfr = "UDP_FADDR.FEN", "Memory", 0xfffb0008, 4, base=16, bitRange=8
-sfr = "UDP_IER", "Memory", 0xfffb0010, 4, base=16
-sfr = "UDP_IER.EPINT0", "Memory", 0xfffb0010, 4, base=16, bitRange=0
-sfr = "UDP_IER.EPINT1", "Memory", 0xfffb0010, 4, base=16, bitRange=1
-sfr = "UDP_IER.EPINT2", "Memory", 0xfffb0010, 4, base=16, bitRange=2
-sfr = "UDP_IER.EPINT3", "Memory", 0xfffb0010, 4, base=16, bitRange=3
-sfr = "UDP_IER.RXSUSP", "Memory", 0xfffb0010, 4, base=16, bitRange=8
-sfr = "UDP_IER.RXRSM", "Memory", 0xfffb0010, 4, base=16, bitRange=9
-sfr = "UDP_IER.EXTRSM", "Memory", 0xfffb0010, 4, base=16, bitRange=10
-sfr = "UDP_IER.SOFINT", "Memory", 0xfffb0010, 4, base=16, bitRange=11
-sfr = "UDP_IER.WAKEUP", "Memory", 0xfffb0010, 4, base=16, bitRange=13
-sfr = "UDP_IDR", "Memory", 0xfffb0014, 4, base=16
-sfr = "UDP_IDR.EPINT0", "Memory", 0xfffb0014, 4, base=16, bitRange=0
-sfr = "UDP_IDR.EPINT1", "Memory", 0xfffb0014, 4, base=16, bitRange=1
-sfr = "UDP_IDR.EPINT2", "Memory", 0xfffb0014, 4, base=16, bitRange=2
-sfr = "UDP_IDR.EPINT3", "Memory", 0xfffb0014, 4, base=16, bitRange=3
-sfr = "UDP_IDR.RXSUSP", "Memory", 0xfffb0014, 4, base=16, bitRange=8
-sfr = "UDP_IDR.RXRSM", "Memory", 0xfffb0014, 4, base=16, bitRange=9
-sfr = "UDP_IDR.EXTRSM", "Memory", 0xfffb0014, 4, base=16, bitRange=10
-sfr = "UDP_IDR.SOFINT", "Memory", 0xfffb0014, 4, base=16, bitRange=11
-sfr = "UDP_IDR.WAKEUP", "Memory", 0xfffb0014, 4, base=16, bitRange=13
-sfr = "UDP_IMR", "Memory", 0xfffb0018, 4, base=16
-sfr = "UDP_IMR.EPINT0", "Memory", 0xfffb0018, 4, base=16, bitRange=0
-sfr = "UDP_IMR.EPINT1", "Memory", 0xfffb0018, 4, base=16, bitRange=1
-sfr = "UDP_IMR.EPINT2", "Memory", 0xfffb0018, 4, base=16, bitRange=2
-sfr = "UDP_IMR.EPINT3", "Memory", 0xfffb0018, 4, base=16, bitRange=3
-sfr = "UDP_IMR.RXSUSP", "Memory", 0xfffb0018, 4, base=16, bitRange=8
-sfr = "UDP_IMR.RXRSM", "Memory", 0xfffb0018, 4, base=16, bitRange=9
-sfr = "UDP_IMR.EXTRSM", "Memory", 0xfffb0018, 4, base=16, bitRange=10
-sfr = "UDP_IMR.SOFINT", "Memory", 0xfffb0018, 4, base=16, bitRange=11
-sfr = "UDP_IMR.WAKEUP", "Memory", 0xfffb0018, 4, base=16, bitRange=13
-sfr = "UDP_ISR", "Memory", 0xfffb001c, 4, base=16
-sfr = "UDP_ISR.EPINT0", "Memory", 0xfffb001c, 4, base=16, bitRange=0
-sfr = "UDP_ISR.EPINT1", "Memory", 0xfffb001c, 4, base=16, bitRange=1
-sfr = "UDP_ISR.EPINT2", "Memory", 0xfffb001c, 4, base=16, bitRange=2
-sfr = "UDP_ISR.EPINT3", "Memory", 0xfffb001c, 4, base=16, bitRange=3
-sfr = "UDP_ISR.RXSUSP", "Memory", 0xfffb001c, 4, base=16, bitRange=8
-sfr = "UDP_ISR.RXRSM", "Memory", 0xfffb001c, 4, base=16, bitRange=9
-sfr = "UDP_ISR.EXTRSM", "Memory", 0xfffb001c, 4, base=16, bitRange=10
-sfr = "UDP_ISR.SOFINT", "Memory", 0xfffb001c, 4, base=16, bitRange=11
-sfr = "UDP_ISR.ENDBUSRES", "Memory", 0xfffb001c, 4, base=16, bitRange=12
-sfr = "UDP_ISR.WAKEUP", "Memory", 0xfffb001c, 4, base=16, bitRange=13
-sfr = "UDP_ICR", "Memory", 0xfffb0020, 4, base=16
-sfr = "UDP_ICR.EPINT0", "Memory", 0xfffb0020, 4, base=16, bitRange=0
-sfr = "UDP_ICR.EPINT1", "Memory", 0xfffb0020, 4, base=16, bitRange=1
-sfr = "UDP_ICR.EPINT2", "Memory", 0xfffb0020, 4, base=16, bitRange=2
-sfr = "UDP_ICR.EPINT3", "Memory", 0xfffb0020, 4, base=16, bitRange=3
-sfr = "UDP_ICR.RXSUSP", "Memory", 0xfffb0020, 4, base=16, bitRange=8
-sfr = "UDP_ICR.RXRSM", "Memory", 0xfffb0020, 4, base=16, bitRange=9
-sfr = "UDP_ICR.EXTRSM", "Memory", 0xfffb0020, 4, base=16, bitRange=10
-sfr = "UDP_ICR.SOFINT", "Memory", 0xfffb0020, 4, base=16, bitRange=11
-sfr = "UDP_ICR.WAKEUP", "Memory", 0xfffb0020, 4, base=16, bitRange=13
-sfr = "UDP_RSTEP", "Memory", 0xfffb0028, 4, base=16
-sfr = "UDP_RSTEP.EP0", "Memory", 0xfffb0028, 4, base=16, bitRange=0
-sfr = "UDP_RSTEP.EP1", "Memory", 0xfffb0028, 4, base=16, bitRange=1
-sfr = "UDP_RSTEP.EP2", "Memory", 0xfffb0028, 4, base=16, bitRange=2
-sfr = "UDP_RSTEP.EP3", "Memory", 0xfffb0028, 4, base=16, bitRange=3
-sfr = "UDP_CSR", "Memory", 0xfffb0030, 4, base=16
-sfr = "UDP_CSR.TXCOMP", "Memory", 0xfffb0030, 4, base=16, bitRange=0
-sfr = "UDP_CSR.BK0", "Memory", 0xfffb0030, 4, base=16, bitRange=1
-sfr = "UDP_CSR.RXSETUP", "Memory", 0xfffb0030, 4, base=16, bitRange=2
-sfr = "UDP_CSR.ISOERROR", "Memory", 0xfffb0030, 4, base=16, bitRange=3
-sfr = "UDP_CSR.TXPKTRDY", "Memory", 0xfffb0030, 4, base=16, bitRange=4
-sfr = "UDP_CSR.FORCESTALL", "Memory", 0xfffb0030, 4, base=16, bitRange=5
-sfr = "UDP_CSR.BK1", "Memory", 0xfffb0030, 4, base=16, bitRange=6
-sfr = "UDP_CSR.DIR", "Memory", 0xfffb0030, 4, base=16, bitRange=7
-sfr = "UDP_CSR.EPTYPE", "Memory", 0xfffb0030, 4, base=16, bitRange=8-10
-sfr = "UDP_CSR.DTGLE", "Memory", 0xfffb0030, 4, base=16, bitRange=11
-sfr = "UDP_CSR.EPEDS", "Memory", 0xfffb0030, 4, base=16, bitRange=15
-sfr = "UDP_CSR.RXBYTECNT", "Memory", 0xfffb0030, 4, base=16, bitRange=16-26
-sfr = "UDP_FDR", "Memory", 0xfffb0050, 4, base=16
-sfr = "UDP_TXVC", "Memory", 0xfffb0074, 4, base=16
-sfr = "UDP_TXVC.TXVDIS", "Memory", 0xfffb0074, 4, base=16, bitRange=8
-
-
-[SfrGroupInfo]
-group = "TC0", "TC0_CCR", "TC0_CMR", "TC0_CV", "TC0_RA", "TC0_RB", "TC0_RC", "TC0_SR", "TC0_IER", "TC0_IDR", "TC0_IMR"
-group = "TCB", "TCB_BCR", "TCB_BMR"
-group = "TC1", "TC1_CCR", "TC1_CMR", "TC1_CV", "TC1_RA", "TC1_RB", "TC1_RC", "TC1_SR", "TC1_IER", "TC1_IDR", "TC1_IMR"
-group = "TC2", "TC2_CCR", "TC2_CMR", "TC2_CV", "TC2_RA", "TC2_RB", "TC2_RC", "TC2_SR", "TC2_IER", "TC2_IDR", "TC2_IMR"
-group = "UDP", "UDP_NUM", "UDP_GLBSTATE", "UDP_FADDR", "UDP_IER", "UDP_IDR", "UDP_IMR", "UDP_ISR", "UDP_ICR", "UDP_RSTEP", "UDP_CSR", "UDP_FDR", "UDP_TXVC"
-group = "TWI", "TWI_CR", "TWI_MMR", "TWI_IADR", "TWI_CWGR", "TWI_SR", "TWI_IER", "TWI_IDR", "TWI_IMR", "TWI_RHR", "TWI_THR"
-group = "US0", "US0_CR", "US0_MR", "US0_IER", "US0_IDR", "US0_IMR", "US0_CSR", "US0_RHR", "US0_THR", "US0_BRGR", "US0_RTOR", "US0_TTGR", "US0_FIDI", "US0_NER", "US0_IF"
-group = "PDC_US0", "US0_RPR", "US0_RCR", "US0_TPR", "US0_TCR", "US0_RNPR", "US0_RNCR", "US0_TNPR", "US0_TNCR", "US0_PTCR", "US0_PTSR"
-group = "US1", "US1_CR", "US1_MR", "US1_IER", "US1_IDR", "US1_IMR", "US1_CSR", "US1_RHR", "US1_THR", "US1_BRGR", "US1_RTOR", "US1_TTGR", "US1_FIDI", "US1_NER", "US1_IF"
-group = "PDC_US1", "US1_RPR", "US1_RCR", "US1_TPR", "US1_TCR", "US1_RNPR", "US1_RNCR", "US1_TNPR", "US1_TNCR", "US1_PTCR", "US1_PTSR"
-group = "PWMC", "PWMC_MR", "PWMC_ENA", "PWMC_DIS", "PWMC_SR", "PWMC_IER", "PWMC_IDR", "PWMC_IMR", "PWMC_ISR", "PWMC_VR"
-group = "PWMC_CH0", "PWMC_CH0_CMR", "PWMC_CH0_CDTYR", "PWMC_CH0_CPRDR", "PWMC_CH0_CCNTR", "PWMC_CH0_CUPDR", "PWMC_CH0_Reserved"
-group = "PWMC_CH1", "PWMC_CH1_CMR", "PWMC_CH1_CDTYR", "PWMC_CH1_CPRDR", "PWMC_CH1_CCNTR", "PWMC_CH1_CUPDR", "PWMC_CH1_Reserved"
-group = "PWMC_CH2", "PWMC_CH2_CMR", "PWMC_CH2_CDTYR", "PWMC_CH2_CPRDR", "PWMC_CH2_CCNTR", "PWMC_CH2_CUPDR", "PWMC_CH2_Reserved"
-group = "PWMC_CH3", "PWMC_CH3_CMR", "PWMC_CH3_CDTYR", "PWMC_CH3_CPRDR", "PWMC_CH3_CCNTR", "PWMC_CH3_CUPDR", "PWMC_CH3_Reserved"
-group = "SSC", "SSC_CR", "SSC_CMR", "SSC_RCMR", "SSC_RFMR", "SSC_TCMR", "SSC_TFMR", "SSC_RHR", "SSC_THR", "SSC_RSHR", "SSC_TSHR", "SSC_SR", "SSC_IER", "SSC_IDR", "SSC_IMR"
-group = "PDC_SSC", "SSC_RPR", "SSC_RCR", "SSC_TPR", "SSC_TCR", "SSC_RNPR", "SSC_RNCR", "SSC_TNPR", "SSC_TNCR", "SSC_PTCR", "SSC_PTSR"
-group = "ADC", "ADC_CR", "ADC_MR", "ADC_CHER", "ADC_CHDR", "ADC_CHSR", "ADC_SR", "ADC_LCDR", "ADC_IER", "ADC_IDR", "ADC_IMR", "ADC_CDR0", "ADC_CDR1", "ADC_CDR2", "ADC_CDR3", "ADC_CDR4", "ADC_CDR5", "ADC_CDR6", "ADC_CDR7"
-group = "PDC_ADC", "ADC_RPR", "ADC_RCR", "ADC_TPR", "ADC_TCR", "ADC_RNPR", "ADC_RNCR", "ADC_TNPR", "ADC_TNCR", "ADC_PTCR", "ADC_PTSR"
-group = "SPI", "SPI_CR", "SPI_MR", "SPI_RDR", "SPI_TDR", "SPI_SR", "SPI_IER", "SPI_IDR", "SPI_IMR", "SPI_CSR"
-group = "PDC_SPI", "SPI_RPR", "SPI_RCR", "SPI_TPR", "SPI_TCR", "SPI_RNPR", "SPI_RNCR", "SPI_TNPR", "SPI_TNCR", "SPI_PTCR", "SPI_PTSR"
-group = "SYS"
-group = "AIC", "AIC_SMR", "AIC_SVR", "AIC_IVR", "AIC_FVR", "AIC_ISR", "AIC_IPR", "AIC_IMR", "AIC_CISR", "AIC_IECR", "AIC_IDCR", "AIC_ICCR", "AIC_ISCR", "AIC_EOICR", "AIC_SPU", "AIC_DCR", "AIC_FFER", "AIC_FFDR", "AIC_FFSR"
-group = "DBGU", "DBGU_CR", "DBGU_MR", "DBGU_IER", "DBGU_IDR", "DBGU_IMR", "DBGU_CSR", "DBGU_RHR", "DBGU_THR", "DBGU_BRGR", "DBGU_CIDR", "DBGU_EXID", "DBGU_FNTR"
-group = "PDC_DBGU", "DBGU_RPR", "DBGU_RCR", "DBGU_TPR", "DBGU_TCR", "DBGU_RNPR", "DBGU_RNCR", "DBGU_TNPR", "DBGU_TNCR", "DBGU_PTCR", "DBGU_PTSR"
-group = "PIOA", "PIOA_PER", "PIOA_PDR", "PIOA_PSR", "PIOA_OER", "PIOA_ODR", "PIOA_OSR", "PIOA_IFER", "PIOA_IFDR", "PIOA_IFSR", "PIOA_SODR", "PIOA_CODR", "PIOA_ODSR", "PIOA_PDSR", "PIOA_IER", "PIOA_IDR", "PIOA_IMR", "PIOA_ISR", "PIOA_MDER", "PIOA_MDDR", "PIOA_MDSR", "PIOA_PPUDR", "PIOA_PPUER", "PIOA_PPUSR", "PIOA_ASR", "PIOA_BSR", "PIOA_ABSR", "PIOA_OWER", "PIOA_OWDR", "PIOA_OWSR"
-group = "PMC", "PMC_SCER", "PMC_SCDR", "PMC_SCSR", "PMC_PCER", "PMC_PCDR", "PMC_PCSR", "PMC_MOR", "PMC_MCFR", "PMC_PLLR", "PMC_MCKR", "PMC_PCKR", "PMC_IER", "PMC_IDR", "PMC_SR", "PMC_IMR"
-group = "CKGR", "CKGR_MOR", "CKGR_MCFR", "CKGR_PLLR"
-group = "RSTC", "RSTC_RCR", "RSTC_RSR", "RSTC_RMR"
-group = "RTTC", "RTTC_RTMR", "RTTC_RTAR", "RTTC_RTVR", "RTTC_RTSR"
-group = "PITC", "PITC_PIMR", "PITC_PISR", "PITC_PIVR", "PITC_PIIR"
-group = "WDTC", "WDTC_WDCR", "WDTC_WDMR", "WDTC_WDSR"
-group = "VREG", "VREG_MR"
-group = "MC", "MC_RCR", "MC_ASR", "MC_AASR", "MC_FMR", "MC_FCR", "MC_FSR"
diff --git a/openpcd/firmware/include/old/ioat91sam7s64.h b/openpcd/firmware/include/old/ioat91sam7s64.h deleted file mode 100644 index 5ac6ef6..0000000 --- a/openpcd/firmware/include/old/ioat91sam7s64.h +++ /dev/null @@ -1,3300 +0,0 @@ -// - ---------------------------------------------------------------------------- -// - ATMEL Microcontroller Software Support - ROUSSET - -// - ---------------------------------------------------------------------------- -// - DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -// - IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -// - MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -// - DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -// - INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -// - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -// - OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -// - LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -// - NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -// - EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -// - ---------------------------------------------------------------------------- -// - File Name : AT91SAM7S64.h -// - Object : AT91SAM7S64 definitions -// - Generated : AT91 SW Application Group 08/30/2005 (15:52:59) -// - -// - CVS Reference : /AT91SAM7S64.pl/1.21/Tue Aug 30 11:55:03 2005// -// - CVS Reference : /SYS_SAM7S.pl/1.2/Tue Feb 1 17:01:52 2005// -// - CVS Reference : /MC_SAM7S.pl/1.3/Fri May 20 14:12:30 2005// -// - CVS Reference : /PMC_SAM7S_USB.pl/1.4/Tue Feb 8 13:58:22 2005// -// - CVS Reference : /RSTC_SAM7S.pl/1.2/Wed Jul 13 14:57:40 2005// -// - CVS Reference : /UDP_SAM7S.pl/1.1/Tue May 10 11:34:52 2005// -// - CVS Reference : /PWM_SAM7S.pl/1.1/Tue May 10 11:53:07 2005// -// - CVS Reference : /RTTC_6081A.pl/1.2/Tue Nov 9 14:43:58 2004// -// - CVS Reference : /PITC_6079A.pl/1.2/Tue Nov 9 14:43:56 2004// -// - CVS Reference : /WDTC_6080A.pl/1.3/Tue Nov 9 14:44:00 2004// -// - CVS Reference : /VREG_6085B.pl/1.1/Tue Feb 1 16:05:48 2005// -// - CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005// -// - CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:18:28 2005// -// - CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005// -// - CVS Reference : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004// -// - CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005// -// - CVS Reference : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004// -// - CVS Reference : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005// -// - CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004// -// - CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 08:48:54 2005// -// - CVS Reference : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003// -// - ---------------------------------------------------------------------------- - -#ifndef AT91SAM7S64_H -#define AT91SAM7S64_H - -#ifdef __IAR_SYSTEMS_ICC__ - -typedef volatile unsigned int AT91_REG;// Hardware register definition - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR System Peripherals -// ***************************************************************************** -typedef struct _AT91S_SYS { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register - AT91_REG Reserved2[45]; // - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved3[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved4[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register - AT91_REG Reserved5[54]; // - AT91_REG PIOA_PER; // PIO Enable Register - AT91_REG PIOA_PDR; // PIO Disable Register - AT91_REG PIOA_PSR; // PIO Status Register - AT91_REG Reserved6[1]; // - AT91_REG PIOA_OER; // Output Enable Register - AT91_REG PIOA_ODR; // Output Disable Registerr - AT91_REG PIOA_OSR; // Output Status Register - AT91_REG Reserved7[1]; // - AT91_REG PIOA_IFER; // Input Filter Enable Register - AT91_REG PIOA_IFDR; // Input Filter Disable Register - AT91_REG PIOA_IFSR; // Input Filter Status Register - AT91_REG Reserved8[1]; // - AT91_REG PIOA_SODR; // Set Output Data Register - AT91_REG PIOA_CODR; // Clear Output Data Register - AT91_REG PIOA_ODSR; // Output Data Status Register - AT91_REG PIOA_PDSR; // Pin Data Status Register - AT91_REG PIOA_IER; // Interrupt Enable Register - AT91_REG PIOA_IDR; // Interrupt Disable Register - AT91_REG PIOA_IMR; // Interrupt Mask Register - AT91_REG PIOA_ISR; // Interrupt Status Register - AT91_REG PIOA_MDER; // Multi-driver Enable Register - AT91_REG PIOA_MDDR; // Multi-driver Disable Register - AT91_REG PIOA_MDSR; // Multi-driver Status Register - AT91_REG Reserved9[1]; // - AT91_REG PIOA_PPUDR; // Pull-up Disable Register - AT91_REG PIOA_PPUER; // Pull-up Enable Register - AT91_REG PIOA_PPUSR; // Pull-up Status Register - AT91_REG Reserved10[1]; // - AT91_REG PIOA_ASR; // Select A Register - AT91_REG PIOA_BSR; // Select B Register - AT91_REG PIOA_ABSR; // AB Select Status Register - AT91_REG Reserved11[9]; // - AT91_REG PIOA_OWER; // Output Write Enable Register - AT91_REG PIOA_OWDR; // Output Write Disable Register - AT91_REG PIOA_OWSR; // Output Write Status Register - AT91_REG Reserved12[469]; // - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved13[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved14[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved15[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved16[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved17[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register - AT91_REG Reserved18[36]; // - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register - AT91_REG Reserved19[5]; // - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register - AT91_REG Reserved20[5]; // - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_SYS, *AT91PS_SYS; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// ***************************************************************************** -typedef struct _AT91S_AIC { - AT91_REG AIC_SMR[32]; // Source Mode Register - AT91_REG AIC_SVR[32]; // Source Vector Register - AT91_REG AIC_IVR; // IRQ Vector Register - AT91_REG AIC_FVR; // FIQ Vector Register - AT91_REG AIC_ISR; // Interrupt Status Register - AT91_REG AIC_IPR; // Interrupt Pending Register - AT91_REG AIC_IMR; // Interrupt Mask Register - AT91_REG AIC_CISR; // Core Interrupt Status Register - AT91_REG Reserved0[2]; // - AT91_REG AIC_IECR; // Interrupt Enable Command Register - AT91_REG AIC_IDCR; // Interrupt Disable Command Register - AT91_REG AIC_ICCR; // Interrupt Clear Command Register - AT91_REG AIC_ISCR; // Interrupt Set Command Register - AT91_REG AIC_EOICR; // End of Interrupt Command Register - AT91_REG AIC_SPU; // Spurious Vector Register - AT91_REG AIC_DCR; // Debug Control Register (Protect) - AT91_REG Reserved1[1]; // - AT91_REG AIC_FFER; // Fast Forcing Enable Register - AT91_REG AIC_FFDR; // Fast Forcing Disable Register - AT91_REG AIC_FFSR; // Fast Forcing Status Register -} AT91S_AIC, *AT91PS_AIC; - -// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level -#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level -#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level -#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type -#define AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL ((unsigned int) 0x0 << 5) // (AIC) External Sources Code Label Low-level Sensitive -#define AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Positive Edge triggered -#define AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE ((unsigned int) 0x1 << 5) // (AIC) External Sources Code Label Negative Edge triggered -#define AT91C_AIC_SRCTYPE_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) Internal Or External Sources Code Label High-level Sensitive -#define AT91C_AIC_SRCTYPE_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered -// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status -#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status -// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -#define AT91C_AIC_DCR_PROT ((unsigned int) 0x1 << 0) // (AIC) Protection Mode -#define AT91C_AIC_DCR_GMSK ((unsigned int) 0x1 << 1) // (AIC) General Mask - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// ***************************************************************************** -typedef struct _AT91S_PDC { - AT91_REG PDC_RPR; // Receive Pointer Register - AT91_REG PDC_RCR; // Receive Counter Register - AT91_REG PDC_TPR; // Transmit Pointer Register - AT91_REG PDC_TCR; // Transmit Counter Register - AT91_REG PDC_RNPR; // Receive Next Pointer Register - AT91_REG PDC_RNCR; // Receive Next Counter Register - AT91_REG PDC_TNPR; // Transmit Next Pointer Register - AT91_REG PDC_TNCR; // Transmit Next Counter Register - AT91_REG PDC_PTCR; // PDC Transfer Control Register - AT91_REG PDC_PTSR; // PDC Transfer Status Register -} AT91S_PDC, *AT91PS_PDC; - -// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -#define AT91C_PDC_RXTEN ((unsigned int) 0x1 << 0) // (PDC) Receiver Transfer Enable -#define AT91C_PDC_RXTDIS ((unsigned int) 0x1 << 1) // (PDC) Receiver Transfer Disable -#define AT91C_PDC_TXTEN ((unsigned int) 0x1 << 8) // (PDC) Transmitter Transfer Enable -#define AT91C_PDC_TXTDIS ((unsigned int) 0x1 << 9) // (PDC) Transmitter Transfer Disable -// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Debug Unit -// ***************************************************************************** -typedef struct _AT91S_DBGU { - AT91_REG DBGU_CR; // Control Register - AT91_REG DBGU_MR; // Mode Register - AT91_REG DBGU_IER; // Interrupt Enable Register - AT91_REG DBGU_IDR; // Interrupt Disable Register - AT91_REG DBGU_IMR; // Interrupt Mask Register - AT91_REG DBGU_CSR; // Channel Status Register - AT91_REG DBGU_RHR; // Receiver Holding Register - AT91_REG DBGU_THR; // Transmitter Holding Register - AT91_REG DBGU_BRGR; // Baud Rate Generator Register - AT91_REG Reserved0[7]; // - AT91_REG DBGU_CIDR; // Chip ID Register - AT91_REG DBGU_EXID; // Chip ID Extension Register - AT91_REG DBGU_FNTR; // Force NTRST Register - AT91_REG Reserved1[45]; // - AT91_REG DBGU_RPR; // Receive Pointer Register - AT91_REG DBGU_RCR; // Receive Counter Register - AT91_REG DBGU_TPR; // Transmit Pointer Register - AT91_REG DBGU_TCR; // Transmit Counter Register - AT91_REG DBGU_RNPR; // Receive Next Pointer Register - AT91_REG DBGU_RNCR; // Receive Next Counter Register - AT91_REG DBGU_TNPR; // Transmit Next Pointer Register - AT91_REG DBGU_TNCR; // Transmit Next Counter Register - AT91_REG DBGU_PTCR; // PDC Transfer Control Register - AT91_REG DBGU_PTSR; // PDC Transfer Status Register -} AT91S_DBGU, *AT91PS_DBGU; - -// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (DBGU) Reset Receiver -#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (DBGU) Reset Transmitter -#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (DBGU) Receiver Enable -#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (DBGU) Receiver Disable -#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (DBGU) Transmitter Enable -#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (DBGU) Transmitter Disable -#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits -// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (DBGU) Parity type -#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (DBGU) Even Parity -#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (DBGU) Odd Parity -#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (DBGU) Parity forced to 0 (Space) -#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (DBGU) Parity forced to 1 (Mark) -#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (DBGU) No Parity -#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (DBGU) Multi-drop mode -#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode -#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (DBGU) RXRDY Interrupt -#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (DBGU) TXRDY Interrupt -#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (DBGU) End of Receive Transfer Interrupt -#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (DBGU) End of Transmit Interrupt -#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (DBGU) Overrun Interrupt -#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (DBGU) Framing Error Interrupt -#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (DBGU) Parity Error Interrupt -#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (DBGU) TXEMPTY Interrupt -#define AT91C_US_TXBUFE ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt -#define AT91C_US_RXBUFF ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt -#define AT91C_US_COMM_TX ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt -#define AT91C_US_COMM_RX ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt -// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -#define AT91C_US_FORCE_NTRST ((unsigned int) 0x1 << 0) // (DBGU) Force NTRST in JTAG - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// ***************************************************************************** -typedef struct _AT91S_PIO { - AT91_REG PIO_PER; // PIO Enable Register - AT91_REG PIO_PDR; // PIO Disable Register - AT91_REG PIO_PSR; // PIO Status Register - AT91_REG Reserved0[1]; // - AT91_REG PIO_OER; // Output Enable Register - AT91_REG PIO_ODR; // Output Disable Registerr - AT91_REG PIO_OSR; // Output Status Register - AT91_REG Reserved1[1]; // - AT91_REG PIO_IFER; // Input Filter Enable Register - AT91_REG PIO_IFDR; // Input Filter Disable Register - AT91_REG PIO_IFSR; // Input Filter Status Register - AT91_REG Reserved2[1]; // - AT91_REG PIO_SODR; // Set Output Data Register - AT91_REG PIO_CODR; // Clear Output Data Register - AT91_REG PIO_ODSR; // Output Data Status Register - AT91_REG PIO_PDSR; // Pin Data Status Register - AT91_REG PIO_IER; // Interrupt Enable Register - AT91_REG PIO_IDR; // Interrupt Disable Register - AT91_REG PIO_IMR; // Interrupt Mask Register - AT91_REG PIO_ISR; // Interrupt Status Register - AT91_REG PIO_MDER; // Multi-driver Enable Register - AT91_REG PIO_MDDR; // Multi-driver Disable Register - AT91_REG PIO_MDSR; // Multi-driver Status Register - AT91_REG Reserved3[1]; // - AT91_REG PIO_PPUDR; // Pull-up Disable Register - AT91_REG PIO_PPUER; // Pull-up Enable Register - AT91_REG PIO_PPUSR; // Pull-up Status Register - AT91_REG Reserved4[1]; // - AT91_REG PIO_ASR; // Select A Register - AT91_REG PIO_BSR; // Select B Register - AT91_REG PIO_ABSR; // AB Select Status Register - AT91_REG Reserved5[9]; // - AT91_REG PIO_OWER; // Output Write Enable Register - AT91_REG PIO_OWDR; // Output Write Disable Register - AT91_REG PIO_OWSR; // Output Write Status Register -} AT91S_PIO, *AT91PS_PIO; - - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Clock Generator Controler -// ***************************************************************************** -typedef struct _AT91S_CKGR { - AT91_REG CKGR_MOR; // Main Oscillator Register - AT91_REG CKGR_MCFR; // Main Clock Frequency Register - AT91_REG Reserved0[1]; // - AT91_REG CKGR_PLLR; // PLL Register -} AT91S_CKGR, *AT91PS_CKGR; - -// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -#define AT91C_CKGR_MOSCEN ((unsigned int) 0x1 << 0) // (CKGR) Main Oscillator Enable -#define AT91C_CKGR_OSCBYPASS ((unsigned int) 0x1 << 1) // (CKGR) Main Oscillator Bypass -#define AT91C_CKGR_OSCOUNT ((unsigned int) 0xFF << 8) // (CKGR) Main Oscillator Start-up Time -// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -#define AT91C_CKGR_MAINF ((unsigned int) 0xFFFF << 0) // (CKGR) Main Clock Frequency -#define AT91C_CKGR_MAINRDY ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready -// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -#define AT91C_CKGR_DIV ((unsigned int) 0xFF << 0) // (CKGR) Divider Selected -#define AT91C_CKGR_DIV_0 ((unsigned int) 0x0) // (CKGR) Divider output is 0 -#define AT91C_CKGR_DIV_BYPASS ((unsigned int) 0x1) // (CKGR) Divider is bypassed -#define AT91C_CKGR_PLLCOUNT ((unsigned int) 0x3F << 8) // (CKGR) PLL Counter -#define AT91C_CKGR_OUT ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range -#define AT91C_CKGR_OUT_0 ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_1 ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_2 ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_OUT_3 ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet -#define AT91C_CKGR_MUL ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier -#define AT91C_CKGR_USBDIV ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks -#define AT91C_CKGR_USBDIV_0 ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output -#define AT91C_CKGR_USBDIV_1 ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2 -#define AT91C_CKGR_USBDIV_2 ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Power Management Controler -// ***************************************************************************** -typedef struct _AT91S_PMC { - AT91_REG PMC_SCER; // System Clock Enable Register - AT91_REG PMC_SCDR; // System Clock Disable Register - AT91_REG PMC_SCSR; // System Clock Status Register - AT91_REG Reserved0[1]; // - AT91_REG PMC_PCER; // Peripheral Clock Enable Register - AT91_REG PMC_PCDR; // Peripheral Clock Disable Register - AT91_REG PMC_PCSR; // Peripheral Clock Status Register - AT91_REG Reserved1[1]; // - AT91_REG PMC_MOR; // Main Oscillator Register - AT91_REG PMC_MCFR; // Main Clock Frequency Register - AT91_REG Reserved2[1]; // - AT91_REG PMC_PLLR; // PLL Register - AT91_REG PMC_MCKR; // Master Clock Register - AT91_REG Reserved3[3]; // - AT91_REG PMC_PCKR[3]; // Programmable Clock Register - AT91_REG Reserved4[5]; // - AT91_REG PMC_IER; // Interrupt Enable Register - AT91_REG PMC_IDR; // Interrupt Disable Register - AT91_REG PMC_SR; // Status Register - AT91_REG PMC_IMR; // Interrupt Mask Register -} AT91S_PMC, *AT91PS_PMC; - -// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -#define AT91C_PMC_PCK ((unsigned int) 0x1 << 0) // (PMC) Processor Clock -#define AT91C_PMC_UDP ((unsigned int) 0x1 << 7) // (PMC) USB Device Port Clock -#define AT91C_PMC_PCK0 ((unsigned int) 0x1 << 8) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK1 ((unsigned int) 0x1 << 9) // (PMC) Programmable Clock Output -#define AT91C_PMC_PCK2 ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output -// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -#define AT91C_PMC_CSS ((unsigned int) 0x3 << 0) // (PMC) Programmable Clock Selection -#define AT91C_PMC_CSS_SLOW_CLK ((unsigned int) 0x0) // (PMC) Slow Clock is selected -#define AT91C_PMC_CSS_MAIN_CLK ((unsigned int) 0x1) // (PMC) Main Clock is selected -#define AT91C_PMC_CSS_PLL_CLK ((unsigned int) 0x3) // (PMC) Clock from PLL is selected -#define AT91C_PMC_PRES ((unsigned int) 0x7 << 2) // (PMC) Programmable Clock Prescaler -#define AT91C_PMC_PRES_CLK ((unsigned int) 0x0 << 2) // (PMC) Selected clock -#define AT91C_PMC_PRES_CLK_2 ((unsigned int) 0x1 << 2) // (PMC) Selected clock divided by 2 -#define AT91C_PMC_PRES_CLK_4 ((unsigned int) 0x2 << 2) // (PMC) Selected clock divided by 4 -#define AT91C_PMC_PRES_CLK_8 ((unsigned int) 0x3 << 2) // (PMC) Selected clock divided by 8 -#define AT91C_PMC_PRES_CLK_16 ((unsigned int) 0x4 << 2) // (PMC) Selected clock divided by 16 -#define AT91C_PMC_PRES_CLK_32 ((unsigned int) 0x5 << 2) // (PMC) Selected clock divided by 32 -#define AT91C_PMC_PRES_CLK_64 ((unsigned int) 0x6 << 2) // (PMC) Selected clock divided by 64 -// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -#define AT91C_PMC_MOSCS ((unsigned int) 0x1 << 0) // (PMC) MOSC Status/Enable/Disable/Mask -#define AT91C_PMC_LOCK ((unsigned int) 0x1 << 2) // (PMC) PLL Status/Enable/Disable/Mask -#define AT91C_PMC_MCKRDY ((unsigned int) 0x1 << 3) // (PMC) MCK_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK0RDY ((unsigned int) 0x1 << 8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK1RDY ((unsigned int) 0x1 << 9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask -#define AT91C_PMC_PCK2RDY ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask -// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Reset Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RSTC { - AT91_REG RSTC_RCR; // Reset Control Register - AT91_REG RSTC_RSR; // Reset Status Register - AT91_REG RSTC_RMR; // Reset Mode Register -} AT91S_RSTC, *AT91PS_RSTC; - -// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -#define AT91C_RSTC_PROCRST ((unsigned int) 0x1 << 0) // (RSTC) Processor Reset -#define AT91C_RSTC_PERRST ((unsigned int) 0x1 << 2) // (RSTC) Peripheral Reset -#define AT91C_RSTC_EXTRST ((unsigned int) 0x1 << 3) // (RSTC) External Reset -#define AT91C_RSTC_KEY ((unsigned int) 0xFF << 24) // (RSTC) Password -// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -#define AT91C_RSTC_URSTS ((unsigned int) 0x1 << 0) // (RSTC) User Reset Status -#define AT91C_RSTC_BODSTS ((unsigned int) 0x1 << 1) // (RSTC) Brownout Detection Status -#define AT91C_RSTC_RSTTYP ((unsigned int) 0x7 << 8) // (RSTC) Reset Type -#define AT91C_RSTC_RSTTYP_POWERUP ((unsigned int) 0x0 << 8) // (RSTC) Power-up Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WAKEUP ((unsigned int) 0x1 << 8) // (RSTC) WakeUp Reset. VDDCORE rising. -#define AT91C_RSTC_RSTTYP_WATCHDOG ((unsigned int) 0x2 << 8) // (RSTC) Watchdog Reset. Watchdog overflow occured. -#define AT91C_RSTC_RSTTYP_SOFTWARE ((unsigned int) 0x3 << 8) // (RSTC) Software Reset. Processor reset required by the software. -#define AT91C_RSTC_RSTTYP_USER ((unsigned int) 0x4 << 8) // (RSTC) User Reset. NRST pin detected low. -#define AT91C_RSTC_RSTTYP_BROWNOUT ((unsigned int) 0x5 << 8) // (RSTC) Brownout Reset occured. -#define AT91C_RSTC_NRSTL ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level -#define AT91C_RSTC_SRCMP ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress. -// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -#define AT91C_RSTC_URSTEN ((unsigned int) 0x1 << 0) // (RSTC) User Reset Enable -#define AT91C_RSTC_URSTIEN ((unsigned int) 0x1 << 4) // (RSTC) User Reset Interrupt Enable -#define AT91C_RSTC_ERSTL ((unsigned int) 0xF << 8) // (RSTC) User Reset Length -#define AT91C_RSTC_BODIEN ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_RTTC { - AT91_REG RTTC_RTMR; // Real-time Mode Register - AT91_REG RTTC_RTAR; // Real-time Alarm Register - AT91_REG RTTC_RTVR; // Real-time Value Register - AT91_REG RTTC_RTSR; // Real-time Status Register -} AT91S_RTTC, *AT91PS_RTTC; - -// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -#define AT91C_RTTC_RTPRES ((unsigned int) 0xFFFF << 0) // (RTTC) Real-time Timer Prescaler Value -#define AT91C_RTTC_ALMIEN ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable -#define AT91C_RTTC_RTTINCIEN ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable -#define AT91C_RTTC_RTTRST ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart -// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -#define AT91C_RTTC_ALMV ((unsigned int) 0x0 << 0) // (RTTC) Alarm Value -// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -#define AT91C_RTTC_CRTV ((unsigned int) 0x0 << 0) // (RTTC) Current Real-time Value -// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -#define AT91C_RTTC_ALMS ((unsigned int) 0x1 << 0) // (RTTC) Real-time Alarm Status -#define AT91C_RTTC_RTTINC ((unsigned int) 0x1 << 1) // (RTTC) Real-time Timer Increment - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PITC { - AT91_REG PITC_PIMR; // Period Interval Mode Register - AT91_REG PITC_PISR; // Period Interval Status Register - AT91_REG PITC_PIVR; // Period Interval Value Register - AT91_REG PITC_PIIR; // Period Interval Image Register -} AT91S_PITC, *AT91PS_PITC; - -// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -#define AT91C_PITC_PIV ((unsigned int) 0xFFFFF << 0) // (PITC) Periodic Interval Value -#define AT91C_PITC_PITEN ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled -#define AT91C_PITC_PITIEN ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable -// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -#define AT91C_PITC_PITS ((unsigned int) 0x1 << 0) // (PITC) Periodic Interval Timer Status -// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -#define AT91C_PITC_CPIV ((unsigned int) 0xFFFFF << 0) // (PITC) Current Periodic Interval Value -#define AT91C_PITC_PICNT ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter -// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// ***************************************************************************** -typedef struct _AT91S_WDTC { - AT91_REG WDTC_WDCR; // Watchdog Control Register - AT91_REG WDTC_WDMR; // Watchdog Mode Register - AT91_REG WDTC_WDSR; // Watchdog Status Register -} AT91S_WDTC, *AT91PS_WDTC; - -// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -#define AT91C_WDTC_WDRSTT ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Restart -#define AT91C_WDTC_KEY ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password -// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -#define AT91C_WDTC_WDV ((unsigned int) 0xFFF << 0) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDFIEN ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable -#define AT91C_WDTC_WDRSTEN ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable -#define AT91C_WDTC_WDRPROC ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart -#define AT91C_WDTC_WDDIS ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable -#define AT91C_WDTC_WDD ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value -#define AT91C_WDTC_WDDBGHLT ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt -#define AT91C_WDTC_WDIDLEHLT ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt -// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -#define AT91C_WDTC_WDUNF ((unsigned int) 0x1 << 0) // (WDTC) Watchdog Underflow -#define AT91C_WDTC_WDERR ((unsigned int) 0x1 << 1) // (WDTC) Watchdog Error - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// ***************************************************************************** -typedef struct _AT91S_VREG { - AT91_REG VREG_MR; // Voltage Regulator Mode Register -} AT91S_VREG, *AT91PS_VREG; - -// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -#define AT91C_VREG_PSTDBY ((unsigned int) 0x1 << 0) // (VREG) Voltage Regulator Power Standby Mode - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Memory Controller Interface -// ***************************************************************************** -typedef struct _AT91S_MC { - AT91_REG MC_RCR; // MC Remap Control Register - AT91_REG MC_ASR; // MC Abort Status Register - AT91_REG MC_AASR; // MC Abort Address Status Register - AT91_REG Reserved0[21]; // - AT91_REG MC_FMR; // MC Flash Mode Register - AT91_REG MC_FCR; // MC Flash Command Register - AT91_REG MC_FSR; // MC Flash Status Register -} AT91S_MC, *AT91PS_MC; - -// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -#define AT91C_MC_RCB ((unsigned int) 0x1 << 0) // (MC) Remap Command Bit -// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -#define AT91C_MC_UNDADD ((unsigned int) 0x1 << 0) // (MC) Undefined Addess Abort Status -#define AT91C_MC_MISADD ((unsigned int) 0x1 << 1) // (MC) Misaligned Addess Abort Status -#define AT91C_MC_ABTSZ ((unsigned int) 0x3 << 8) // (MC) Abort Size Status -#define AT91C_MC_ABTSZ_BYTE ((unsigned int) 0x0 << 8) // (MC) Byte -#define AT91C_MC_ABTSZ_HWORD ((unsigned int) 0x1 << 8) // (MC) Half-word -#define AT91C_MC_ABTSZ_WORD ((unsigned int) 0x2 << 8) // (MC) Word -#define AT91C_MC_ABTTYP ((unsigned int) 0x3 << 10) // (MC) Abort Type Status -#define AT91C_MC_ABTTYP_DATAR ((unsigned int) 0x0 << 10) // (MC) Data Read -#define AT91C_MC_ABTTYP_DATAW ((unsigned int) 0x1 << 10) // (MC) Data Write -#define AT91C_MC_ABTTYP_FETCH ((unsigned int) 0x2 << 10) // (MC) Code Fetch -#define AT91C_MC_MST0 ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source -#define AT91C_MC_MST1 ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source -#define AT91C_MC_SVMST0 ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source -#define AT91C_MC_SVMST1 ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source -// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -#define AT91C_MC_FRDY ((unsigned int) 0x1 << 0) // (MC) Flash Ready -#define AT91C_MC_LOCKE ((unsigned int) 0x1 << 2) // (MC) Lock Error -#define AT91C_MC_PROGE ((unsigned int) 0x1 << 3) // (MC) Programming Error -#define AT91C_MC_NEBP ((unsigned int) 0x1 << 7) // (MC) No Erase Before Programming -#define AT91C_MC_FWS ((unsigned int) 0x3 << 8) // (MC) Flash Wait State -#define AT91C_MC_FWS_0FWS ((unsigned int) 0x0 << 8) // (MC) 1 cycle for Read, 2 for Write operations -#define AT91C_MC_FWS_1FWS ((unsigned int) 0x1 << 8) // (MC) 2 cycles for Read, 3 for Write operations -#define AT91C_MC_FWS_2FWS ((unsigned int) 0x2 << 8) // (MC) 3 cycles for Read, 4 for Write operations -#define AT91C_MC_FWS_3FWS ((unsigned int) 0x3 << 8) // (MC) 4 cycles for Read, 4 for Write operations -#define AT91C_MC_FMCN ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number -// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -#define AT91C_MC_FCMD ((unsigned int) 0xF << 0) // (MC) Flash Command -#define AT91C_MC_FCMD_START_PROG ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN. -#define AT91C_MC_FCMD_LOCK ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_PROG_AND_LOCK ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed. -#define AT91C_MC_FCMD_UNLOCK ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -#define AT91C_MC_FCMD_ERASE_ALL ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -#define AT91C_MC_FCMD_SET_GP_NVM ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits. -#define AT91C_MC_FCMD_CLR_GP_NVM ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits. -#define AT91C_MC_FCMD_SET_SECURITY ((unsigned int) 0xF) // (MC) Set Security Bit. -#define AT91C_MC_PAGEN ((unsigned int) 0x3FF << 8) // (MC) Page Number -#define AT91C_MC_KEY ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key -// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -#define AT91C_MC_SECURITY ((unsigned int) 0x1 << 4) // (MC) Security Bit Status -#define AT91C_MC_GPNVM0 ((unsigned int) 0x1 << 8) // (MC) Sector 0 Lock Status -#define AT91C_MC_GPNVM1 ((unsigned int) 0x1 << 9) // (MC) Sector 1 Lock Status -#define AT91C_MC_GPNVM2 ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status -#define AT91C_MC_GPNVM3 ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status -#define AT91C_MC_GPNVM4 ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status -#define AT91C_MC_GPNVM5 ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status -#define AT91C_MC_GPNVM6 ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status -#define AT91C_MC_GPNVM7 ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS0 ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status -#define AT91C_MC_LOCKS1 ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status -#define AT91C_MC_LOCKS2 ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status -#define AT91C_MC_LOCKS3 ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status -#define AT91C_MC_LOCKS4 ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status -#define AT91C_MC_LOCKS5 ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status -#define AT91C_MC_LOCKS6 ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status -#define AT91C_MC_LOCKS7 ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status -#define AT91C_MC_LOCKS8 ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status -#define AT91C_MC_LOCKS9 ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status -#define AT91C_MC_LOCKS10 ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status -#define AT91C_MC_LOCKS11 ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status -#define AT91C_MC_LOCKS12 ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status -#define AT91C_MC_LOCKS13 ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status -#define AT91C_MC_LOCKS14 ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status -#define AT91C_MC_LOCKS15 ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Serial Parallel Interface -// ***************************************************************************** -typedef struct _AT91S_SPI { - AT91_REG SPI_CR; // Control Register - AT91_REG SPI_MR; // Mode Register - AT91_REG SPI_RDR; // Receive Data Register - AT91_REG SPI_TDR; // Transmit Data Register - AT91_REG SPI_SR; // Status Register - AT91_REG SPI_IER; // Interrupt Enable Register - AT91_REG SPI_IDR; // Interrupt Disable Register - AT91_REG SPI_IMR; // Interrupt Mask Register - AT91_REG Reserved0[4]; // - AT91_REG SPI_CSR[4]; // Chip Select Register - AT91_REG Reserved1[48]; // - AT91_REG SPI_RPR; // Receive Pointer Register - AT91_REG SPI_RCR; // Receive Counter Register - AT91_REG SPI_TPR; // Transmit Pointer Register - AT91_REG SPI_TCR; // Transmit Counter Register - AT91_REG SPI_RNPR; // Receive Next Pointer Register - AT91_REG SPI_RNCR; // Receive Next Counter Register - AT91_REG SPI_TNPR; // Transmit Next Pointer Register - AT91_REG SPI_TNCR; // Transmit Next Counter Register - AT91_REG SPI_PTCR; // PDC Transfer Control Register - AT91_REG SPI_PTSR; // PDC Transfer Status Register -} AT91S_SPI, *AT91PS_SPI; - -// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -#define AT91C_SPI_SPIEN ((unsigned int) 0x1 << 0) // (SPI) SPI Enable -#define AT91C_SPI_SPIDIS ((unsigned int) 0x1 << 1) // (SPI) SPI Disable -#define AT91C_SPI_SWRST ((unsigned int) 0x1 << 7) // (SPI) SPI Software reset -#define AT91C_SPI_LASTXFER ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer -// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -#define AT91C_SPI_MSTR ((unsigned int) 0x1 << 0) // (SPI) Master/Slave Mode -#define AT91C_SPI_PS ((unsigned int) 0x1 << 1) // (SPI) Peripheral Select -#define AT91C_SPI_PS_FIXED ((unsigned int) 0x0 << 1) // (SPI) Fixed Peripheral Select -#define AT91C_SPI_PS_VARIABLE ((unsigned int) 0x1 << 1) // (SPI) Variable Peripheral Select -#define AT91C_SPI_PCSDEC ((unsigned int) 0x1 << 2) // (SPI) Chip Select Decode -#define AT91C_SPI_FDIV ((unsigned int) 0x1 << 3) // (SPI) Clock Selection -#define AT91C_SPI_MODFDIS ((unsigned int) 0x1 << 4) // (SPI) Mode Fault Detection -#define AT91C_SPI_LLB ((unsigned int) 0x1 << 7) // (SPI) Clock Selection -#define AT91C_SPI_PCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select -#define AT91C_SPI_DLYBCS ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects -// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -#define AT91C_SPI_RD ((unsigned int) 0xFFFF << 0) // (SPI) Receive Data -#define AT91C_SPI_RPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -#define AT91C_SPI_TD ((unsigned int) 0xFFFF << 0) // (SPI) Transmit Data -#define AT91C_SPI_TPCS ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status -// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -#define AT91C_SPI_RDRF ((unsigned int) 0x1 << 0) // (SPI) Receive Data Register Full -#define AT91C_SPI_TDRE ((unsigned int) 0x1 << 1) // (SPI) Transmit Data Register Empty -#define AT91C_SPI_MODF ((unsigned int) 0x1 << 2) // (SPI) Mode Fault Error -#define AT91C_SPI_OVRES ((unsigned int) 0x1 << 3) // (SPI) Overrun Error Status -#define AT91C_SPI_ENDRX ((unsigned int) 0x1 << 4) // (SPI) End of Receiver Transfer -#define AT91C_SPI_ENDTX ((unsigned int) 0x1 << 5) // (SPI) End of Receiver Transfer -#define AT91C_SPI_RXBUFF ((unsigned int) 0x1 << 6) // (SPI) RXBUFF Interrupt -#define AT91C_SPI_TXBUFE ((unsigned int) 0x1 << 7) // (SPI) TXBUFE Interrupt -#define AT91C_SPI_NSSR ((unsigned int) 0x1 << 8) // (SPI) NSSR Interrupt -#define AT91C_SPI_TXEMPTY ((unsigned int) 0x1 << 9) // (SPI) TXEMPTY Interrupt -#define AT91C_SPI_SPIENS ((unsigned int) 0x1 << 16) // (SPI) Enable Status -// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -#define AT91C_SPI_CPOL ((unsigned int) 0x1 << 0) // (SPI) Clock Polarity -#define AT91C_SPI_NCPHA ((unsigned int) 0x1 << 1) // (SPI) Clock Phase -#define AT91C_SPI_CSAAT ((unsigned int) 0x1 << 3) // (SPI) Chip Select Active After Transfer -#define AT91C_SPI_BITS ((unsigned int) 0xF << 4) // (SPI) Bits Per Transfer -#define AT91C_SPI_BITS_8 ((unsigned int) 0x0 << 4) // (SPI) 8 Bits Per transfer -#define AT91C_SPI_BITS_9 ((unsigned int) 0x1 << 4) // (SPI) 9 Bits Per transfer -#define AT91C_SPI_BITS_10 ((unsigned int) 0x2 << 4) // (SPI) 10 Bits Per transfer -#define AT91C_SPI_BITS_11 ((unsigned int) 0x3 << 4) // (SPI) 11 Bits Per transfer -#define AT91C_SPI_BITS_12 ((unsigned int) 0x4 << 4) // (SPI) 12 Bits Per transfer -#define AT91C_SPI_BITS_13 ((unsigned int) 0x5 << 4) // (SPI) 13 Bits Per transfer -#define AT91C_SPI_BITS_14 ((unsigned int) 0x6 << 4) // (SPI) 14 Bits Per transfer -#define AT91C_SPI_BITS_15 ((unsigned int) 0x7 << 4) // (SPI) 15 Bits Per transfer -#define AT91C_SPI_BITS_16 ((unsigned int) 0x8 << 4) // (SPI) 16 Bits Per transfer -#define AT91C_SPI_SCBR ((unsigned int) 0xFF << 8) // (SPI) Serial Clock Baud Rate -#define AT91C_SPI_DLYBS ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK -#define AT91C_SPI_DLYBCT ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// ***************************************************************************** -typedef struct _AT91S_ADC { - AT91_REG ADC_CR; // ADC Control Register - AT91_REG ADC_MR; // ADC Mode Register - AT91_REG Reserved0[2]; // - AT91_REG ADC_CHER; // ADC Channel Enable Register - AT91_REG ADC_CHDR; // ADC Channel Disable Register - AT91_REG ADC_CHSR; // ADC Channel Status Register - AT91_REG ADC_SR; // ADC Status Register - AT91_REG ADC_LCDR; // ADC Last Converted Data Register - AT91_REG ADC_IER; // ADC Interrupt Enable Register - AT91_REG ADC_IDR; // ADC Interrupt Disable Register - AT91_REG ADC_IMR; // ADC Interrupt Mask Register - AT91_REG ADC_CDR0; // ADC Channel Data Register 0 - AT91_REG ADC_CDR1; // ADC Channel Data Register 1 - AT91_REG ADC_CDR2; // ADC Channel Data Register 2 - AT91_REG ADC_CDR3; // ADC Channel Data Register 3 - AT91_REG ADC_CDR4; // ADC Channel Data Register 4 - AT91_REG ADC_CDR5; // ADC Channel Data Register 5 - AT91_REG ADC_CDR6; // ADC Channel Data Register 6 - AT91_REG ADC_CDR7; // ADC Channel Data Register 7 - AT91_REG Reserved1[44]; // - AT91_REG ADC_RPR; // Receive Pointer Register - AT91_REG ADC_RCR; // Receive Counter Register - AT91_REG ADC_TPR; // Transmit Pointer Register - AT91_REG ADC_TCR; // Transmit Counter Register - AT91_REG ADC_RNPR; // Receive Next Pointer Register - AT91_REG ADC_RNCR; // Receive Next Counter Register - AT91_REG ADC_TNPR; // Transmit Next Pointer Register - AT91_REG ADC_TNCR; // Transmit Next Counter Register - AT91_REG ADC_PTCR; // PDC Transfer Control Register - AT91_REG ADC_PTSR; // PDC Transfer Status Register -} AT91S_ADC, *AT91PS_ADC; - -// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -#define AT91C_ADC_SWRST ((unsigned int) 0x1 << 0) // (ADC) Software Reset -#define AT91C_ADC_START ((unsigned int) 0x1 << 1) // (ADC) Start Conversion -// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -#define AT91C_ADC_TRGEN ((unsigned int) 0x1 << 0) // (ADC) Trigger Enable -#define AT91C_ADC_TRGEN_DIS ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -#define AT91C_ADC_TRGEN_EN ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled. -#define AT91C_ADC_TRGSEL ((unsigned int) 0x7 << 1) // (ADC) Trigger Selection -#define AT91C_ADC_TRGSEL_TIOA0 ((unsigned int) 0x0 << 1) // (ADC) Selected TRGSEL = TIAO0 -#define AT91C_ADC_TRGSEL_TIOA1 ((unsigned int) 0x1 << 1) // (ADC) Selected TRGSEL = TIAO1 -#define AT91C_ADC_TRGSEL_TIOA2 ((unsigned int) 0x2 << 1) // (ADC) Selected TRGSEL = TIAO2 -#define AT91C_ADC_TRGSEL_TIOA3 ((unsigned int) 0x3 << 1) // (ADC) Selected TRGSEL = TIAO3 -#define AT91C_ADC_TRGSEL_TIOA4 ((unsigned int) 0x4 << 1) // (ADC) Selected TRGSEL = TIAO4 -#define AT91C_ADC_TRGSEL_TIOA5 ((unsigned int) 0x5 << 1) // (ADC) Selected TRGSEL = TIAO5 -#define AT91C_ADC_TRGSEL_EXT ((unsigned int) 0x6 << 1) // (ADC) Selected TRGSEL = External Trigger -#define AT91C_ADC_LOWRES ((unsigned int) 0x1 << 4) // (ADC) Resolution. -#define AT91C_ADC_LOWRES_10_BIT ((unsigned int) 0x0 << 4) // (ADC) 10-bit resolution -#define AT91C_ADC_LOWRES_8_BIT ((unsigned int) 0x1 << 4) // (ADC) 8-bit resolution -#define AT91C_ADC_SLEEP ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_SLEEP_NORMAL_MODE ((unsigned int) 0x0 << 5) // (ADC) Normal Mode -#define AT91C_ADC_SLEEP_MODE ((unsigned int) 0x1 << 5) // (ADC) Sleep Mode -#define AT91C_ADC_PRESCAL ((unsigned int) 0x3F << 8) // (ADC) Prescaler rate selection -#define AT91C_ADC_STARTUP ((unsigned int) 0x1F << 16) // (ADC) Startup Time -#define AT91C_ADC_SHTIM ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time -// -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -#define AT91C_ADC_CH0 ((unsigned int) 0x1 << 0) // (ADC) Channel 0 -#define AT91C_ADC_CH1 ((unsigned int) 0x1 << 1) // (ADC) Channel 1 -#define AT91C_ADC_CH2 ((unsigned int) 0x1 << 2) // (ADC) Channel 2 -#define AT91C_ADC_CH3 ((unsigned int) 0x1 << 3) // (ADC) Channel 3 -#define AT91C_ADC_CH4 ((unsigned int) 0x1 << 4) // (ADC) Channel 4 -#define AT91C_ADC_CH5 ((unsigned int) 0x1 << 5) // (ADC) Channel 5 -#define AT91C_ADC_CH6 ((unsigned int) 0x1 << 6) // (ADC) Channel 6 -#define AT91C_ADC_CH7 ((unsigned int) 0x1 << 7) // (ADC) Channel 7 -// -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -#define AT91C_ADC_EOC0 ((unsigned int) 0x1 << 0) // (ADC) End of Conversion -#define AT91C_ADC_EOC1 ((unsigned int) 0x1 << 1) // (ADC) End of Conversion -#define AT91C_ADC_EOC2 ((unsigned int) 0x1 << 2) // (ADC) End of Conversion -#define AT91C_ADC_EOC3 ((unsigned int) 0x1 << 3) // (ADC) End of Conversion -#define AT91C_ADC_EOC4 ((unsigned int) 0x1 << 4) // (ADC) End of Conversion -#define AT91C_ADC_EOC5 ((unsigned int) 0x1 << 5) // (ADC) End of Conversion -#define AT91C_ADC_EOC6 ((unsigned int) 0x1 << 6) // (ADC) End of Conversion -#define AT91C_ADC_EOC7 ((unsigned int) 0x1 << 7) // (ADC) End of Conversion -#define AT91C_ADC_OVRE0 ((unsigned int) 0x1 << 8) // (ADC) Overrun Error -#define AT91C_ADC_OVRE1 ((unsigned int) 0x1 << 9) // (ADC) Overrun Error -#define AT91C_ADC_OVRE2 ((unsigned int) 0x1 << 10) // (ADC) Overrun Error -#define AT91C_ADC_OVRE3 ((unsigned int) 0x1 << 11) // (ADC) Overrun Error -#define AT91C_ADC_OVRE4 ((unsigned int) 0x1 << 12) // (ADC) Overrun Error -#define AT91C_ADC_OVRE5 ((unsigned int) 0x1 << 13) // (ADC) Overrun Error -#define AT91C_ADC_OVRE6 ((unsigned int) 0x1 << 14) // (ADC) Overrun Error -#define AT91C_ADC_OVRE7 ((unsigned int) 0x1 << 15) // (ADC) Overrun Error -#define AT91C_ADC_DRDY ((unsigned int) 0x1 << 16) // (ADC) Data Ready -#define AT91C_ADC_GOVRE ((unsigned int) 0x1 << 17) // (ADC) General Overrun -#define AT91C_ADC_ENDRX ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer -#define AT91C_ADC_RXBUFF ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt -// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -#define AT91C_ADC_LDATA ((unsigned int) 0x3FF << 0) // (ADC) Last Data Converted -// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -#define AT91C_ADC_DATA ((unsigned int) 0x3FF << 0) // (ADC) Converted Data -// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// ***************************************************************************** -typedef struct _AT91S_SSC { - AT91_REG SSC_CR; // Control Register - AT91_REG SSC_CMR; // Clock Mode Register - AT91_REG Reserved0[2]; // - AT91_REG SSC_RCMR; // Receive Clock ModeRegister - AT91_REG SSC_RFMR; // Receive Frame Mode Register - AT91_REG SSC_TCMR; // Transmit Clock Mode Register - AT91_REG SSC_TFMR; // Transmit Frame Mode Register - AT91_REG SSC_RHR; // Receive Holding Register - AT91_REG SSC_THR; // Transmit Holding Register - AT91_REG Reserved1[2]; // - AT91_REG SSC_RSHR; // Receive Sync Holding Register - AT91_REG SSC_TSHR; // Transmit Sync Holding Register - AT91_REG Reserved2[2]; // - AT91_REG SSC_SR; // Status Register - AT91_REG SSC_IER; // Interrupt Enable Register - AT91_REG SSC_IDR; // Interrupt Disable Register - AT91_REG SSC_IMR; // Interrupt Mask Register - AT91_REG Reserved3[44]; // - AT91_REG SSC_RPR; // Receive Pointer Register - AT91_REG SSC_RCR; // Receive Counter Register - AT91_REG SSC_TPR; // Transmit Pointer Register - AT91_REG SSC_TCR; // Transmit Counter Register - AT91_REG SSC_RNPR; // Receive Next Pointer Register - AT91_REG SSC_RNCR; // Receive Next Counter Register - AT91_REG SSC_TNPR; // Transmit Next Pointer Register - AT91_REG SSC_TNCR; // Transmit Next Counter Register - AT91_REG SSC_PTCR; // PDC Transfer Control Register - AT91_REG SSC_PTSR; // PDC Transfer Status Register -} AT91S_SSC, *AT91PS_SSC; - -// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -#define AT91C_SSC_RXEN ((unsigned int) 0x1 << 0) // (SSC) Receive Enable -#define AT91C_SSC_RXDIS ((unsigned int) 0x1 << 1) // (SSC) Receive Disable -#define AT91C_SSC_TXEN ((unsigned int) 0x1 << 8) // (SSC) Transmit Enable -#define AT91C_SSC_TXDIS ((unsigned int) 0x1 << 9) // (SSC) Transmit Disable -#define AT91C_SSC_SWRST ((unsigned int) 0x1 << 15) // (SSC) Software Reset -// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -#define AT91C_SSC_CKS ((unsigned int) 0x3 << 0) // (SSC) Receive/Transmit Clock Selection -#define AT91C_SSC_CKS_DIV ((unsigned int) 0x0) // (SSC) Divided Clock -#define AT91C_SSC_CKS_TK ((unsigned int) 0x1) // (SSC) TK Clock signal -#define AT91C_SSC_CKS_RK ((unsigned int) 0x2) // (SSC) RK pin -#define AT91C_SSC_CKO ((unsigned int) 0x7 << 2) // (SSC) Receive/Transmit Clock Output Mode Selection -#define AT91C_SSC_CKO_NONE ((unsigned int) 0x0 << 2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -#define AT91C_SSC_CKO_CONTINOUS ((unsigned int) 0x1 << 2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output -#define AT91C_SSC_CKO_DATA_TX ((unsigned int) 0x2 << 2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -#define AT91C_SSC_CKI ((unsigned int) 0x1 << 5) // (SSC) Receive/Transmit Clock Inversion -#define AT91C_SSC_START ((unsigned int) 0xF << 8) // (SSC) Receive/Transmit Start Selection -#define AT91C_SSC_START_CONTINOUS ((unsigned int) 0x0 << 8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -#define AT91C_SSC_START_TX ((unsigned int) 0x1 << 8) // (SSC) Transmit/Receive start -#define AT91C_SSC_START_LOW_RF ((unsigned int) 0x2 << 8) // (SSC) Detection of a low level on RF input -#define AT91C_SSC_START_HIGH_RF ((unsigned int) 0x3 << 8) // (SSC) Detection of a high level on RF input -#define AT91C_SSC_START_FALL_RF ((unsigned int) 0x4 << 8) // (SSC) Detection of a falling edge on RF input -#define AT91C_SSC_START_RISE_RF ((unsigned int) 0x5 << 8) // (SSC) Detection of a rising edge on RF input -#define AT91C_SSC_START_LEVEL_RF ((unsigned int) 0x6 << 8) // (SSC) Detection of any level change on RF input -#define AT91C_SSC_START_EDGE_RF ((unsigned int) 0x7 << 8) // (SSC) Detection of any edge on RF input -#define AT91C_SSC_START_0 ((unsigned int) 0x8 << 8) // (SSC) Compare 0 -#define AT91C_SSC_STTDLY ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay -#define AT91C_SSC_PERIOD ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection -// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -#define AT91C_SSC_DATLEN ((unsigned int) 0x1F << 0) // (SSC) Data Length -#define AT91C_SSC_LOOP ((unsigned int) 0x1 << 5) // (SSC) Loop Mode -#define AT91C_SSC_MSBF ((unsigned int) 0x1 << 7) // (SSC) Most Significant Bit First -#define AT91C_SSC_DATNB ((unsigned int) 0xF << 8) // (SSC) Data Number per Frame -#define AT91C_SSC_FSLEN ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length -#define AT91C_SSC_FSOS ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection -#define AT91C_SSC_FSOS_NONE ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -#define AT91C_SSC_FSOS_NEGATIVE ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -#define AT91C_SSC_FSOS_POSITIVE ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -#define AT91C_SSC_FSOS_LOW ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -#define AT91C_SSC_FSOS_HIGH ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -#define AT91C_SSC_FSOS_TOGGLE ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -#define AT91C_SSC_FSEDGE ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection -// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -#define AT91C_SSC_DATDEF ((unsigned int) 0x1 << 5) // (SSC) Data Default Value -#define AT91C_SSC_FSDEN ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable -// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -#define AT91C_SSC_TXRDY ((unsigned int) 0x1 << 0) // (SSC) Transmit Ready -#define AT91C_SSC_TXEMPTY ((unsigned int) 0x1 << 1) // (SSC) Transmit Empty -#define AT91C_SSC_ENDTX ((unsigned int) 0x1 << 2) // (SSC) End Of Transmission -#define AT91C_SSC_TXBUFE ((unsigned int) 0x1 << 3) // (SSC) Transmit Buffer Empty -#define AT91C_SSC_RXRDY ((unsigned int) 0x1 << 4) // (SSC) Receive Ready -#define AT91C_SSC_OVRUN ((unsigned int) 0x1 << 5) // (SSC) Receive Overrun -#define AT91C_SSC_ENDRX ((unsigned int) 0x1 << 6) // (SSC) End of Reception -#define AT91C_SSC_RXBUFF ((unsigned int) 0x1 << 7) // (SSC) Receive Buffer Full -#define AT91C_SSC_TXSYN ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync -#define AT91C_SSC_RXSYN ((unsigned int) 0x1 << 11) // (SSC) Receive Sync -#define AT91C_SSC_TXENA ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable -#define AT91C_SSC_RXENA ((unsigned int) 0x1 << 17) // (SSC) Receive Enable -// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Usart -// ***************************************************************************** -typedef struct _AT91S_USART { - AT91_REG US_CR; // Control Register - AT91_REG US_MR; // Mode Register - AT91_REG US_IER; // Interrupt Enable Register - AT91_REG US_IDR; // Interrupt Disable Register - AT91_REG US_IMR; // Interrupt Mask Register - AT91_REG US_CSR; // Channel Status Register - AT91_REG US_RHR; // Receiver Holding Register - AT91_REG US_THR; // Transmitter Holding Register - AT91_REG US_BRGR; // Baud Rate Generator Register - AT91_REG US_RTOR; // Receiver Time-out Register - AT91_REG US_TTGR; // Transmitter Time-guard Register - AT91_REG Reserved0[5]; // - AT91_REG US_FIDI; // FI_DI_Ratio Register - AT91_REG US_NER; // Nb Errors Register - AT91_REG Reserved1[1]; // - AT91_REG US_IF; // IRDA_FILTER Register - AT91_REG Reserved2[44]; // - AT91_REG US_RPR; // Receive Pointer Register - AT91_REG US_RCR; // Receive Counter Register - AT91_REG US_TPR; // Transmit Pointer Register - AT91_REG US_TCR; // Transmit Counter Register - AT91_REG US_RNPR; // Receive Next Pointer Register - AT91_REG US_RNCR; // Receive Next Counter Register - AT91_REG US_TNPR; // Transmit Next Pointer Register - AT91_REG US_TNCR; // Transmit Next Counter Register - AT91_REG US_PTCR; // PDC Transfer Control Register - AT91_REG US_PTSR; // PDC Transfer Status Register -} AT91S_USART, *AT91PS_USART; - -// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break -#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break -#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out -#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address -#define AT91C_US_RSTIT ((unsigned int) 0x1 << 13) // (USART) Reset Iterations -#define AT91C_US_RSTNACK ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge -#define AT91C_US_RETTO ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out -#define AT91C_US_DTREN ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable -#define AT91C_US_DTRDIS ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable -#define AT91C_US_RTSEN ((unsigned int) 0x1 << 18) // (USART) Request to Send enable -#define AT91C_US_RTSDIS ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable -// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -#define AT91C_US_USMODE ((unsigned int) 0xF << 0) // (USART) Usart mode -#define AT91C_US_USMODE_NORMAL ((unsigned int) 0x0) // (USART) Normal -#define AT91C_US_USMODE_RS485 ((unsigned int) 0x1) // (USART) RS485 -#define AT91C_US_USMODE_HWHSH ((unsigned int) 0x2) // (USART) Hardware Handshaking -#define AT91C_US_USMODE_MODEM ((unsigned int) 0x3) // (USART) Modem -#define AT91C_US_USMODE_ISO7816_0 ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0 -#define AT91C_US_USMODE_ISO7816_1 ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1 -#define AT91C_US_USMODE_IRDA ((unsigned int) 0x8) // (USART) IrDA -#define AT91C_US_USMODE_SWHSH ((unsigned int) 0xC) // (USART) Software Handshaking -#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock -#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1 -#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM) -#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK) -#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock -#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits -#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits -#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits -#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits -#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select -#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits -#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit -#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits -#define AT91C_US_MSBF ((unsigned int) 0x1 << 16) // (USART) Bit Order -#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length -#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select -#define AT91C_US_OVER ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode -#define AT91C_US_INACK ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge -#define AT91C_US_DSNACK ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK -#define AT91C_US_MAX_ITER ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions -#define AT91C_US_FILTER ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter -// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break -#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out -#define AT91C_US_ITERATION ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached -#define AT91C_US_NACK ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge -#define AT91C_US_RIIC ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag -#define AT91C_US_DSRIC ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag -#define AT91C_US_DCDIC ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag -#define AT91C_US_CTSIC ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag -// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -#define AT91C_US_RI ((unsigned int) 0x1 << 20) // (USART) Image of RI Input -#define AT91C_US_DSR ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input -#define AT91C_US_DCD ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input -#define AT91C_US_CTS ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Two-wire Interface -// ***************************************************************************** -typedef struct _AT91S_TWI { - AT91_REG TWI_CR; // Control Register - AT91_REG TWI_MMR; // Master Mode Register - AT91_REG Reserved0[1]; // - AT91_REG TWI_IADR; // Internal Address Register - AT91_REG TWI_CWGR; // Clock Waveform Generator Register - AT91_REG Reserved1[3]; // - AT91_REG TWI_SR; // Status Register - AT91_REG TWI_IER; // Interrupt Enable Register - AT91_REG TWI_IDR; // Interrupt Disable Register - AT91_REG TWI_IMR; // Interrupt Mask Register - AT91_REG TWI_RHR; // Receive Holding Register - AT91_REG TWI_THR; // Transmit Holding Register -} AT91S_TWI, *AT91PS_TWI; - -// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -#define AT91C_TWI_START ((unsigned int) 0x1 << 0) // (TWI) Send a START Condition -#define AT91C_TWI_STOP ((unsigned int) 0x1 << 1) // (TWI) Send a STOP Condition -#define AT91C_TWI_MSEN ((unsigned int) 0x1 << 2) // (TWI) TWI Master Transfer Enabled -#define AT91C_TWI_MSDIS ((unsigned int) 0x1 << 3) // (TWI) TWI Master Transfer Disabled -#define AT91C_TWI_SWRST ((unsigned int) 0x1 << 7) // (TWI) Software Reset -// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -#define AT91C_TWI_IADRSZ ((unsigned int) 0x3 << 8) // (TWI) Internal Device Address Size -#define AT91C_TWI_IADRSZ_NO ((unsigned int) 0x0 << 8) // (TWI) No internal device address -#define AT91C_TWI_IADRSZ_1_BYTE ((unsigned int) 0x1 << 8) // (TWI) One-byte internal device address -#define AT91C_TWI_IADRSZ_2_BYTE ((unsigned int) 0x2 << 8) // (TWI) Two-byte internal device address -#define AT91C_TWI_IADRSZ_3_BYTE ((unsigned int) 0x3 << 8) // (TWI) Three-byte internal device address -#define AT91C_TWI_MREAD ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction -#define AT91C_TWI_DADR ((unsigned int) 0x7F << 16) // (TWI) Device Address -// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -#define AT91C_TWI_CLDIV ((unsigned int) 0xFF << 0) // (TWI) Clock Low Divider -#define AT91C_TWI_CHDIV ((unsigned int) 0xFF << 8) // (TWI) Clock High Divider -#define AT91C_TWI_CKDIV ((unsigned int) 0x7 << 16) // (TWI) Clock Divider -// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -#define AT91C_TWI_TXCOMP ((unsigned int) 0x1 << 0) // (TWI) Transmission Completed -#define AT91C_TWI_RXRDY ((unsigned int) 0x1 << 1) // (TWI) Receive holding register ReaDY -#define AT91C_TWI_TXRDY ((unsigned int) 0x1 << 2) // (TWI) Transmit holding register ReaDY -#define AT91C_TWI_OVRE ((unsigned int) 0x1 << 6) // (TWI) Overrun Error -#define AT91C_TWI_UNRE ((unsigned int) 0x1 << 7) // (TWI) Underrun Error -#define AT91C_TWI_NACK ((unsigned int) 0x1 << 8) // (TWI) Not Acknowledged -// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// ***************************************************************************** -typedef struct _AT91S_TC { - AT91_REG TC_CCR; // Channel Control Register - AT91_REG TC_CMR; // Channel Mode Register (Capture Mode / Waveform Mode) - AT91_REG Reserved0[2]; // - AT91_REG TC_CV; // Counter Value - AT91_REG TC_RA; // Register A - AT91_REG TC_RB; // Register B - AT91_REG TC_RC; // Register C - AT91_REG TC_SR; // Status Register - AT91_REG TC_IER; // Interrupt Enable Register - AT91_REG TC_IDR; // Interrupt Disable Register - AT91_REG TC_IMR; // Interrupt Mask Register -} AT91S_TC, *AT91PS_TC; - -// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command -#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command -#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command -// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -#define AT91C_TC_CLKS ((unsigned int) 0x7 << 0) // (TC) Clock Selection -#define AT91C_TC_CLKS_TIMER_DIV1_CLOCK ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV2_CLOCK ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV3_CLOCK ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV4_CLOCK ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK -#define AT91C_TC_CLKS_TIMER_DIV5_CLOCK ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK -#define AT91C_TC_CLKS_XC0 ((unsigned int) 0x5) // (TC) Clock selected: XC0 -#define AT91C_TC_CLKS_XC1 ((unsigned int) 0x6) // (TC) Clock selected: XC1 -#define AT91C_TC_CLKS_XC2 ((unsigned int) 0x7) // (TC) Clock selected: XC2 -#define AT91C_TC_CLKI ((unsigned int) 0x1 << 3) // (TC) Clock Invert -#define AT91C_TC_BURST ((unsigned int) 0x3 << 4) // (TC) Burst Signal Selection -#define AT91C_TC_BURST_NONE ((unsigned int) 0x0 << 4) // (TC) The clock is not gated by an external signal -#define AT91C_TC_BURST_XC0 ((unsigned int) 0x1 << 4) // (TC) XC0 is ANDed with the selected clock -#define AT91C_TC_BURST_XC1 ((unsigned int) 0x2 << 4) // (TC) XC1 is ANDed with the selected clock -#define AT91C_TC_BURST_XC2 ((unsigned int) 0x3 << 4) // (TC) XC2 is ANDed with the selected clock -#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare -#define AT91C_TC_LDBSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RB Loading -#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare -#define AT91C_TC_LDBDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disabled with RB Loading -#define AT91C_TC_ETRGEDG ((unsigned int) 0x3 << 8) // (TC) External Trigger Edge Selection -#define AT91C_TC_ETRGEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_ETRGEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_ETRGEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_ETRGEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection -#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None -#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge -#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge -#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge -#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection -#define AT91C_TC_EEVT_TIOB ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input -#define AT91C_TC_EEVT_XC0 ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output -#define AT91C_TC_EEVT_XC1 ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output -#define AT91C_TC_EEVT_XC2 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output -#define AT91C_TC_ABETRG ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection -#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable -#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection -#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare -#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare -#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable -#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC) -#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA -#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none -#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set -#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear -#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle -#define AT91C_TC_LDRA ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection -#define AT91C_TC_LDRA_NONE ((unsigned int) 0x0 << 16) // (TC) Edge: None -#define AT91C_TC_LDRA_RISING ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRA_FALLING ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRA_BOTH ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA -#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA -#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none -#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set -#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear -#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle -#define AT91C_TC_LDRB ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection -#define AT91C_TC_LDRB_NONE ((unsigned int) 0x0 << 18) // (TC) Edge: None -#define AT91C_TC_LDRB_RISING ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA -#define AT91C_TC_LDRB_FALLING ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA -#define AT91C_TC_LDRB_BOTH ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA -#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA -#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none -#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set -#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear -#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle -#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA -#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none -#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set -#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear -#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle -#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB -#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none -#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set -#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear -#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle -#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB -#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none -#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set -#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear -#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle -#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB -#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none -#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set -#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear -#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle -#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB -#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none -#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set -#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear -#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle -// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow -#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun -#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare -#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare -#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare -#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading -#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading -#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 7) // (TC) External Trigger -#define AT91C_TC_CLKSTA ((unsigned int) 0x1 << 16) // (TC) Clock Enabling -#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror -#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror -// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Timer Counter Interface -// ***************************************************************************** -typedef struct _AT91S_TCB { - AT91S_TC TCB_TC0; // TC Channel 0 - AT91_REG Reserved0[4]; // - AT91S_TC TCB_TC1; // TC Channel 1 - AT91_REG Reserved1[4]; // - AT91S_TC TCB_TC2; // TC Channel 2 - AT91_REG Reserved2[4]; // - AT91_REG TCB_BCR; // TC Block Control Register - AT91_REG TCB_BMR; // TC Block Mode Register -} AT91S_TCB, *AT91PS_TCB; - -// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command -// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -#define AT91C_TCB_TC0XC0S ((unsigned int) 0x3 << 0) // (TCB) External Clock Signal 0 Selection -#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0 -#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0 -#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0 -#define AT91C_TCB_TC1XC1S ((unsigned int) 0x3 << 2) // (TCB) External Clock Signal 1 Selection -#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1 -#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1 -#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1 -#define AT91C_TCB_TC2XC2S ((unsigned int) 0x3 << 4) // (TCB) External Clock Signal 2 Selection -#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2 -#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2 -#define AT91C_TCB_TC2XC2S_TIOA1 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2 - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR PWMC Channel Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC_CH { - AT91_REG PWMC_CMR; // Channel Mode Register - AT91_REG PWMC_CDTYR; // Channel Duty Cycle Register - AT91_REG PWMC_CPRDR; // Channel Period Register - AT91_REG PWMC_CCNTR; // Channel Counter Register - AT91_REG PWMC_CUPDR; // Channel Update Register - AT91_REG PWMC_Reserved[3]; // Reserved -} AT91S_PWMC_CH, *AT91PS_PWMC_CH; - -// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -#define AT91C_PWMC_CPRE ((unsigned int) 0xF << 0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -#define AT91C_PWMC_CPRE_MCK ((unsigned int) 0x0) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKA ((unsigned int) 0xB) // (PWMC_CH) -#define AT91C_PWMC_CPRE_MCKB ((unsigned int) 0xC) // (PWMC_CH) -#define AT91C_PWMC_CALG ((unsigned int) 0x1 << 8) // (PWMC_CH) Channel Alignment -#define AT91C_PWMC_CPOL ((unsigned int) 0x1 << 9) // (PWMC_CH) Channel Polarity -#define AT91C_PWMC_CPD ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period -// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -#define AT91C_PWMC_CDTY ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Duty Cycle -// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -#define AT91C_PWMC_CPRD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Period -// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -#define AT91C_PWMC_CCNT ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Counter -// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -#define AT91C_PWMC_CUPD ((unsigned int) 0x0 << 0) // (PWMC_CH) Channel Update - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// ***************************************************************************** -typedef struct _AT91S_PWMC { - AT91_REG PWMC_MR; // PWMC Mode Register - AT91_REG PWMC_ENA; // PWMC Enable Register - AT91_REG PWMC_DIS; // PWMC Disable Register - AT91_REG PWMC_SR; // PWMC Status Register - AT91_REG PWMC_IER; // PWMC Interrupt Enable Register - AT91_REG PWMC_IDR; // PWMC Interrupt Disable Register - AT91_REG PWMC_IMR; // PWMC Interrupt Mask Register - AT91_REG PWMC_ISR; // PWMC Interrupt Status Register - AT91_REG Reserved0[55]; // - AT91_REG PWMC_VR; // PWMC Version Register - AT91_REG Reserved1[64]; // - AT91S_PWMC_CH PWMC_CH[4]; // PWMC Channel -} AT91S_PWMC, *AT91PS_PWMC; - -// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -#define AT91C_PWMC_DIVA ((unsigned int) 0xFF << 0) // (PWMC) CLKA divide factor. -#define AT91C_PWMC_PREA ((unsigned int) 0xF << 8) // (PWMC) Divider Input Clock Prescaler A -#define AT91C_PWMC_PREA_MCK ((unsigned int) 0x0 << 8) // (PWMC) -#define AT91C_PWMC_DIVB ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor. -#define AT91C_PWMC_PREB ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B -#define AT91C_PWMC_PREB_MCK ((unsigned int) 0x0 << 24) // (PWMC) -// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -#define AT91C_PWMC_CHID0 ((unsigned int) 0x1 << 0) // (PWMC) Channel ID 0 -#define AT91C_PWMC_CHID1 ((unsigned int) 0x1 << 1) // (PWMC) Channel ID 1 -#define AT91C_PWMC_CHID2 ((unsigned int) 0x1 << 2) // (PWMC) Channel ID 2 -#define AT91C_PWMC_CHID3 ((unsigned int) 0x1 << 3) // (PWMC) Channel ID 3 -// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// ***************************************************************************** -// SOFTWARE API DEFINITION FOR USB Device Interface -// ***************************************************************************** -typedef struct _AT91S_UDP { - AT91_REG UDP_NUM; // Frame Number Register - AT91_REG UDP_GLBSTATE; // Global State Register - AT91_REG UDP_FADDR; // Function Address Register - AT91_REG Reserved0[1]; // - AT91_REG UDP_IER; // Interrupt Enable Register - AT91_REG UDP_IDR; // Interrupt Disable Register - AT91_REG UDP_IMR; // Interrupt Mask Register - AT91_REG UDP_ISR; // Interrupt Status Register - AT91_REG UDP_ICR; // Interrupt Clear Register - AT91_REG Reserved1[1]; // - AT91_REG UDP_RSTEP; // Reset Endpoint Register - AT91_REG Reserved2[1]; // - AT91_REG UDP_CSR[4]; // Endpoint Control and Status Register - AT91_REG Reserved3[4]; // - AT91_REG UDP_FDR[4]; // Endpoint FIFO Data Register - AT91_REG Reserved4[5]; // - AT91_REG UDP_TXVC; // Transceiver Control Register -} AT91S_UDP, *AT91PS_UDP; - -// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -#define AT91C_UDP_FRM_NUM ((unsigned int) 0x7FF << 0) // (UDP) Frame Number as Defined in the Packet Field Formats -#define AT91C_UDP_FRM_ERR ((unsigned int) 0x1 << 16) // (UDP) Frame Error -#define AT91C_UDP_FRM_OK ((unsigned int) 0x1 << 17) // (UDP) Frame OK -// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -#define AT91C_UDP_FADDEN ((unsigned int) 0x1 << 0) // (UDP) Function Address Enable -#define AT91C_UDP_CONFG ((unsigned int) 0x1 << 1) // (UDP) Configured -#define AT91C_UDP_ESR ((unsigned int) 0x1 << 2) // (UDP) Enable Send Resume -#define AT91C_UDP_RSMINPR ((unsigned int) 0x1 << 3) // (UDP) A Resume Has Been Sent to the Host -#define AT91C_UDP_RMWUPE ((unsigned int) 0x1 << 4) // (UDP) Remote Wake Up Enable -// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -#define AT91C_UDP_FADD ((unsigned int) 0xFF << 0) // (UDP) Function Address Value -#define AT91C_UDP_FEN ((unsigned int) 0x1 << 8) // (UDP) Function Enable -// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -#define AT91C_UDP_EPINT0 ((unsigned int) 0x1 << 0) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT1 ((unsigned int) 0x1 << 1) // (UDP) Endpoint 0 Interrupt -#define AT91C_UDP_EPINT2 ((unsigned int) 0x1 << 2) // (UDP) Endpoint 2 Interrupt -#define AT91C_UDP_EPINT3 ((unsigned int) 0x1 << 3) // (UDP) Endpoint 3 Interrupt -#define AT91C_UDP_RXSUSP ((unsigned int) 0x1 << 8) // (UDP) USB Suspend Interrupt -#define AT91C_UDP_RXRSM ((unsigned int) 0x1 << 9) // (UDP) USB Resume Interrupt -#define AT91C_UDP_EXTRSM ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt -#define AT91C_UDP_SOFINT ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt -#define AT91C_UDP_WAKEUP ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt -// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -#define AT91C_UDP_ENDBUSRES ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt -// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -#define AT91C_UDP_EP0 ((unsigned int) 0x1 << 0) // (UDP) Reset Endpoint 0 -#define AT91C_UDP_EP1 ((unsigned int) 0x1 << 1) // (UDP) Reset Endpoint 1 -#define AT91C_UDP_EP2 ((unsigned int) 0x1 << 2) // (UDP) Reset Endpoint 2 -#define AT91C_UDP_EP3 ((unsigned int) 0x1 << 3) // (UDP) Reset Endpoint 3 -// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -#define AT91C_UDP_TXCOMP ((unsigned int) 0x1 << 0) // (UDP) Generates an IN packet with data previously written in the DPR -#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 << 1) // (UDP) Receive Data Bank 0 -#define AT91C_UDP_RXSETUP ((unsigned int) 0x1 << 2) // (UDP) Sends STALL to the Host (Control endpoints) -#define AT91C_UDP_ISOERROR ((unsigned int) 0x1 << 3) // (UDP) Isochronous error (Isochronous endpoints) -#define AT91C_UDP_TXPKTRDY ((unsigned int) 0x1 << 4) // (UDP) Transmit Packet Ready -#define AT91C_UDP_FORCESTALL ((unsigned int) 0x1 << 5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 << 6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -#define AT91C_UDP_DIR ((unsigned int) 0x1 << 7) // (UDP) Transfer Direction -#define AT91C_UDP_EPTYPE ((unsigned int) 0x7 << 8) // (UDP) Endpoint type -#define AT91C_UDP_EPTYPE_CTRL ((unsigned int) 0x0 << 8) // (UDP) Control -#define AT91C_UDP_EPTYPE_ISO_OUT ((unsigned int) 0x1 << 8) // (UDP) Isochronous OUT -#define AT91C_UDP_EPTYPE_BULK_OUT ((unsigned int) 0x2 << 8) // (UDP) Bulk OUT -#define AT91C_UDP_EPTYPE_INT_OUT ((unsigned int) 0x3 << 8) // (UDP) Interrupt OUT -#define AT91C_UDP_EPTYPE_ISO_IN ((unsigned int) 0x5 << 8) // (UDP) Isochronous IN -#define AT91C_UDP_EPTYPE_BULK_IN ((unsigned int) 0x6 << 8) // (UDP) Bulk IN -#define AT91C_UDP_EPTYPE_INT_IN ((unsigned int) 0x7 << 8) // (UDP) Interrupt IN -#define AT91C_UDP_DTGLE ((unsigned int) 0x1 << 11) // (UDP) Data Toggle -#define AT91C_UDP_EPEDS ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable -#define AT91C_UDP_RXBYTECNT ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO -// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -#define AT91C_UDP_TXVDIS ((unsigned int) 0x1 << 8) // (UDP) - -// ***************************************************************************** -// REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// ***************************************************************************** -// ========== Register definition for SYS peripheral ========== -// ========== Register definition for AIC peripheral ========== -#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register -#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode Register -#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register -#define AT91C_AIC_DCR ((AT91_REG *) 0xFFFFF138) // (AIC) Debug Control Register (Protect) -#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register -#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector Register -#define AT91C_AIC_FFSR ((AT91_REG *) 0xFFFFF148) // (AIC) Fast Forcing Status Register -#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register -#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register -#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register -#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register -#define AT91C_AIC_FFER ((AT91_REG *) 0xFFFFF140) // (AIC) Fast Forcing Enable Register -#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register -#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register -#define AT91C_AIC_FFDR ((AT91_REG *) 0xFFFFF144) // (AIC) Fast Forcing Disable Register -#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register -#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command Register -#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register -// ========== Register definition for PDC_DBGU peripheral ========== -#define AT91C_DBGU_TCR ((AT91_REG *) 0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register -#define AT91C_DBGU_RNPR ((AT91_REG *) 0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register -#define AT91C_DBGU_TNPR ((AT91_REG *) 0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register -#define AT91C_DBGU_TPR ((AT91_REG *) 0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register -#define AT91C_DBGU_RPR ((AT91_REG *) 0xFFFFF300) // (PDC_DBGU) Receive Pointer Register -#define AT91C_DBGU_RCR ((AT91_REG *) 0xFFFFF304) // (PDC_DBGU) Receive Counter Register -#define AT91C_DBGU_RNCR ((AT91_REG *) 0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register -#define AT91C_DBGU_PTCR ((AT91_REG *) 0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register -#define AT91C_DBGU_PTSR ((AT91_REG *) 0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register -#define AT91C_DBGU_TNCR ((AT91_REG *) 0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register -// ========== Register definition for DBGU peripheral ========== -#define AT91C_DBGU_EXID ((AT91_REG *) 0xFFFFF244) // (DBGU) Chip ID Extension Register -#define AT91C_DBGU_BRGR ((AT91_REG *) 0xFFFFF220) // (DBGU) Baud Rate Generator Register -#define AT91C_DBGU_IDR ((AT91_REG *) 0xFFFFF20C) // (DBGU) Interrupt Disable Register -#define AT91C_DBGU_CSR ((AT91_REG *) 0xFFFFF214) // (DBGU) Channel Status Register -#define AT91C_DBGU_CIDR ((AT91_REG *) 0xFFFFF240) // (DBGU) Chip ID Register -#define AT91C_DBGU_MR ((AT91_REG *) 0xFFFFF204) // (DBGU) Mode Register -#define AT91C_DBGU_IMR ((AT91_REG *) 0xFFFFF210) // (DBGU) Interrupt Mask Register -#define AT91C_DBGU_CR ((AT91_REG *) 0xFFFFF200) // (DBGU) Control Register -#define AT91C_DBGU_FNTR ((AT91_REG *) 0xFFFFF248) // (DBGU) Force NTRST Register -#define AT91C_DBGU_THR ((AT91_REG *) 0xFFFFF21C) // (DBGU) Transmitter Holding Register -#define AT91C_DBGU_RHR ((AT91_REG *) 0xFFFFF218) // (DBGU) Receiver Holding Register -#define AT91C_DBGU_IER ((AT91_REG *) 0xFFFFF208) // (DBGU) Interrupt Enable Register -// ========== Register definition for PIOA peripheral ========== -#define AT91C_PIOA_ODR ((AT91_REG *) 0xFFFFF414) // (PIOA) Output Disable Registerr -#define AT91C_PIOA_SODR ((AT91_REG *) 0xFFFFF430) // (PIOA) Set Output Data Register -#define AT91C_PIOA_ISR ((AT91_REG *) 0xFFFFF44C) // (PIOA) Interrupt Status Register -#define AT91C_PIOA_ABSR ((AT91_REG *) 0xFFFFF478) // (PIOA) AB Select Status Register -#define AT91C_PIOA_IER ((AT91_REG *) 0xFFFFF440) // (PIOA) Interrupt Enable Register -#define AT91C_PIOA_PPUDR ((AT91_REG *) 0xFFFFF460) // (PIOA) Pull-up Disable Register -#define AT91C_PIOA_IMR ((AT91_REG *) 0xFFFFF448) // (PIOA) Interrupt Mask Register -#define AT91C_PIOA_PER ((AT91_REG *) 0xFFFFF400) // (PIOA) PIO Enable Register -#define AT91C_PIOA_IFDR ((AT91_REG *) 0xFFFFF424) // (PIOA) Input Filter Disable Register -#define AT91C_PIOA_OWDR ((AT91_REG *) 0xFFFFF4A4) // (PIOA) Output Write Disable Register -#define AT91C_PIOA_MDSR ((AT91_REG *) 0xFFFFF458) // (PIOA) Multi-driver Status Register -#define AT91C_PIOA_IDR ((AT91_REG *) 0xFFFFF444) // (PIOA) Interrupt Disable Register -#define AT91C_PIOA_ODSR ((AT91_REG *) 0xFFFFF438) // (PIOA) Output Data Status Register -#define AT91C_PIOA_PPUSR ((AT91_REG *) 0xFFFFF468) // (PIOA) Pull-up Status Register -#define AT91C_PIOA_OWSR ((AT91_REG *) 0xFFFFF4A8) // (PIOA) Output Write Status Register -#define AT91C_PIOA_BSR ((AT91_REG *) 0xFFFFF474) // (PIOA) Select B Register -#define AT91C_PIOA_OWER ((AT91_REG *) 0xFFFFF4A0) // (PIOA) Output Write Enable Register -#define AT91C_PIOA_IFER ((AT91_REG *) 0xFFFFF420) // (PIOA) Input Filter Enable Register -#define AT91C_PIOA_PDSR ((AT91_REG *) 0xFFFFF43C) // (PIOA) Pin Data Status Register -#define AT91C_PIOA_PPUER ((AT91_REG *) 0xFFFFF464) // (PIOA) Pull-up Enable Register -#define AT91C_PIOA_OSR ((AT91_REG *) 0xFFFFF418) // (PIOA) Output Status Register -#define AT91C_PIOA_ASR ((AT91_REG *) 0xFFFFF470) // (PIOA) Select A Register -#define AT91C_PIOA_MDDR ((AT91_REG *) 0xFFFFF454) // (PIOA) Multi-driver Disable Register -#define AT91C_PIOA_CODR ((AT91_REG *) 0xFFFFF434) // (PIOA) Clear Output Data Register -#define AT91C_PIOA_MDER ((AT91_REG *) 0xFFFFF450) // (PIOA) Multi-driver Enable Register -#define AT91C_PIOA_PDR ((AT91_REG *) 0xFFFFF404) // (PIOA) PIO Disable Register -#define AT91C_PIOA_IFSR ((AT91_REG *) 0xFFFFF428) // (PIOA) Input Filter Status Register -#define AT91C_PIOA_OER ((AT91_REG *) 0xFFFFF410) // (PIOA) Output Enable Register -#define AT91C_PIOA_PSR ((AT91_REG *) 0xFFFFF408) // (PIOA) PIO Status Register -// ========== Register definition for CKGR peripheral ========== -#define AT91C_CKGR_MOR ((AT91_REG *) 0xFFFFFC20) // (CKGR) Main Oscillator Register -#define AT91C_CKGR_PLLR ((AT91_REG *) 0xFFFFFC2C) // (CKGR) PLL Register -#define AT91C_CKGR_MCFR ((AT91_REG *) 0xFFFFFC24) // (CKGR) Main Clock Frequency Register -// ========== Register definition for PMC peripheral ========== -#define AT91C_PMC_IDR ((AT91_REG *) 0xFFFFFC64) // (PMC) Interrupt Disable Register -#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register -#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register -#define AT91C_PMC_PCER ((AT91_REG *) 0xFFFFFC10) // (PMC) Peripheral Clock Enable Register -#define AT91C_PMC_PCKR ((AT91_REG *) 0xFFFFFC40) // (PMC) Programmable Clock Register -#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register -#define AT91C_PMC_SCDR ((AT91_REG *) 0xFFFFFC04) // (PMC) System Clock Disable Register -#define AT91C_PMC_PCDR ((AT91_REG *) 0xFFFFFC14) // (PMC) Peripheral Clock Disable Register -#define AT91C_PMC_SCSR ((AT91_REG *) 0xFFFFFC08) // (PMC) System Clock Status Register -#define AT91C_PMC_PCSR ((AT91_REG *) 0xFFFFFC18) // (PMC) Peripheral Clock Status Register -#define AT91C_PMC_MCFR ((AT91_REG *) 0xFFFFFC24) // (PMC) Main Clock Frequency Register -#define AT91C_PMC_SCER ((AT91_REG *) 0xFFFFFC00) // (PMC) System Clock Enable Register -#define AT91C_PMC_IMR ((AT91_REG *) 0xFFFFFC6C) // (PMC) Interrupt Mask Register -#define AT91C_PMC_IER ((AT91_REG *) 0xFFFFFC60) // (PMC) Interrupt Enable Register -#define AT91C_PMC_SR ((AT91_REG *) 0xFFFFFC68) // (PMC) Status Register -// ========== Register definition for RSTC peripheral ========== -#define AT91C_RSTC_RCR ((AT91_REG *) 0xFFFFFD00) // (RSTC) Reset Control Register -#define AT91C_RSTC_RMR ((AT91_REG *) 0xFFFFFD08) // (RSTC) Reset Mode Register -#define AT91C_RSTC_RSR ((AT91_REG *) 0xFFFFFD04) // (RSTC) Reset Status Register -// ========== Register definition for RTTC peripheral ========== -#define AT91C_RTTC_RTSR ((AT91_REG *) 0xFFFFFD2C) // (RTTC) Real-time Status Register -#define AT91C_RTTC_RTMR ((AT91_REG *) 0xFFFFFD20) // (RTTC) Real-time Mode Register -#define AT91C_RTTC_RTVR ((AT91_REG *) 0xFFFFFD28) // (RTTC) Real-time Value Register -#define AT91C_RTTC_RTAR ((AT91_REG *) 0xFFFFFD24) // (RTTC) Real-time Alarm Register -// ========== Register definition for PITC peripheral ========== -#define AT91C_PITC_PIVR ((AT91_REG *) 0xFFFFFD38) // (PITC) Period Interval Value Register -#define AT91C_PITC_PISR ((AT91_REG *) 0xFFFFFD34) // (PITC) Period Interval Status Register -#define AT91C_PITC_PIIR ((AT91_REG *) 0xFFFFFD3C) // (PITC) Period Interval Image Register -#define AT91C_PITC_PIMR ((AT91_REG *) 0xFFFFFD30) // (PITC) Period Interval Mode Register -// ========== Register definition for WDTC peripheral ========== -#define AT91C_WDTC_WDCR ((AT91_REG *) 0xFFFFFD40) // (WDTC) Watchdog Control Register -#define AT91C_WDTC_WDSR ((AT91_REG *) 0xFFFFFD48) // (WDTC) Watchdog Status Register -#define AT91C_WDTC_WDMR ((AT91_REG *) 0xFFFFFD44) // (WDTC) Watchdog Mode Register -// ========== Register definition for VREG peripheral ========== -#define AT91C_VREG_MR ((AT91_REG *) 0xFFFFFD60) // (VREG) Voltage Regulator Mode Register -// ========== Register definition for MC peripheral ========== -#define AT91C_MC_ASR ((AT91_REG *) 0xFFFFFF04) // (MC) MC Abort Status Register -#define AT91C_MC_RCR ((AT91_REG *) 0xFFFFFF00) // (MC) MC Remap Control Register -#define AT91C_MC_FCR ((AT91_REG *) 0xFFFFFF64) // (MC) MC Flash Command Register -#define AT91C_MC_AASR ((AT91_REG *) 0xFFFFFF08) // (MC) MC Abort Address Status Register -#define AT91C_MC_FSR ((AT91_REG *) 0xFFFFFF68) // (MC) MC Flash Status Register -#define AT91C_MC_FMR ((AT91_REG *) 0xFFFFFF60) // (MC) MC Flash Mode Register -// ========== Register definition for PDC_SPI peripheral ========== -#define AT91C_SPI_PTCR ((AT91_REG *) 0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register -#define AT91C_SPI_TPR ((AT91_REG *) 0xFFFE0108) // (PDC_SPI) Transmit Pointer Register -#define AT91C_SPI_TCR ((AT91_REG *) 0xFFFE010C) // (PDC_SPI) Transmit Counter Register -#define AT91C_SPI_RCR ((AT91_REG *) 0xFFFE0104) // (PDC_SPI) Receive Counter Register -#define AT91C_SPI_PTSR ((AT91_REG *) 0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register -#define AT91C_SPI_RNPR ((AT91_REG *) 0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register -#define AT91C_SPI_RPR ((AT91_REG *) 0xFFFE0100) // (PDC_SPI) Receive Pointer Register -#define AT91C_SPI_TNCR ((AT91_REG *) 0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register -#define AT91C_SPI_RNCR ((AT91_REG *) 0xFFFE0114) // (PDC_SPI) Receive Next Counter Register -#define AT91C_SPI_TNPR ((AT91_REG *) 0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register -// ========== Register definition for SPI peripheral ========== -#define AT91C_SPI_IER ((AT91_REG *) 0xFFFE0014) // (SPI) Interrupt Enable Register -#define AT91C_SPI_SR ((AT91_REG *) 0xFFFE0010) // (SPI) Status Register -#define AT91C_SPI_IDR ((AT91_REG *) 0xFFFE0018) // (SPI) Interrupt Disable Register -#define AT91C_SPI_CR ((AT91_REG *) 0xFFFE0000) // (SPI) Control Register -#define AT91C_SPI_MR ((AT91_REG *) 0xFFFE0004) // (SPI) Mode Register -#define AT91C_SPI_IMR ((AT91_REG *) 0xFFFE001C) // (SPI) Interrupt Mask Register -#define AT91C_SPI_TDR ((AT91_REG *) 0xFFFE000C) // (SPI) Transmit Data Register -#define AT91C_SPI_RDR ((AT91_REG *) 0xFFFE0008) // (SPI) Receive Data Register -#define AT91C_SPI_CSR ((AT91_REG *) 0xFFFE0030) // (SPI) Chip Select Register -// ========== Register definition for PDC_ADC peripheral ========== -#define AT91C_ADC_PTSR ((AT91_REG *) 0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register -#define AT91C_ADC_PTCR ((AT91_REG *) 0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register -#define AT91C_ADC_TNPR ((AT91_REG *) 0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register -#define AT91C_ADC_TNCR ((AT91_REG *) 0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register -#define AT91C_ADC_RNPR ((AT91_REG *) 0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register -#define AT91C_ADC_RNCR ((AT91_REG *) 0xFFFD8114) // (PDC_ADC) Receive Next Counter Register -#define AT91C_ADC_RPR ((AT91_REG *) 0xFFFD8100) // (PDC_ADC) Receive Pointer Register -#define AT91C_ADC_TCR ((AT91_REG *) 0xFFFD810C) // (PDC_ADC) Transmit Counter Register -#define AT91C_ADC_TPR ((AT91_REG *) 0xFFFD8108) // (PDC_ADC) Transmit Pointer Register -#define AT91C_ADC_RCR ((AT91_REG *) 0xFFFD8104) // (PDC_ADC) Receive Counter Register -// ========== Register definition for ADC peripheral ========== -#define AT91C_ADC_CDR2 ((AT91_REG *) 0xFFFD8038) // (ADC) ADC Channel Data Register 2 -#define AT91C_ADC_CDR3 ((AT91_REG *) 0xFFFD803C) // (ADC) ADC Channel Data Register 3 -#define AT91C_ADC_CDR0 ((AT91_REG *) 0xFFFD8030) // (ADC) ADC Channel Data Register 0 -#define AT91C_ADC_CDR5 ((AT91_REG *) 0xFFFD8044) // (ADC) ADC Channel Data Register 5 -#define AT91C_ADC_CHDR ((AT91_REG *) 0xFFFD8014) // (ADC) ADC Channel Disable Register -#define AT91C_ADC_SR ((AT91_REG *) 0xFFFD801C) // (ADC) ADC Status Register -#define AT91C_ADC_CDR4 ((AT91_REG *) 0xFFFD8040) // (ADC) ADC Channel Data Register 4 -#define AT91C_ADC_CDR1 ((AT91_REG *) 0xFFFD8034) // (ADC) ADC Channel Data Register 1 -#define AT91C_ADC_LCDR ((AT91_REG *) 0xFFFD8020) // (ADC) ADC Last Converted Data Register -#define AT91C_ADC_IDR ((AT91_REG *) 0xFFFD8028) // (ADC) ADC Interrupt Disable Register -#define AT91C_ADC_CR ((AT91_REG *) 0xFFFD8000) // (ADC) ADC Control Register -#define AT91C_ADC_CDR7 ((AT91_REG *) 0xFFFD804C) // (ADC) ADC Channel Data Register 7 -#define AT91C_ADC_CDR6 ((AT91_REG *) 0xFFFD8048) // (ADC) ADC Channel Data Register 6 -#define AT91C_ADC_IER ((AT91_REG *) 0xFFFD8024) // (ADC) ADC Interrupt Enable Register -#define AT91C_ADC_CHER ((AT91_REG *) 0xFFFD8010) // (ADC) ADC Channel Enable Register -#define AT91C_ADC_CHSR ((AT91_REG *) 0xFFFD8018) // (ADC) ADC Channel Status Register -#define AT91C_ADC_MR ((AT91_REG *) 0xFFFD8004) // (ADC) ADC Mode Register -#define AT91C_ADC_IMR ((AT91_REG *) 0xFFFD802C) // (ADC) ADC Interrupt Mask Register -// ========== Register definition for PDC_SSC peripheral ========== -#define AT91C_SSC_TNCR ((AT91_REG *) 0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register -#define AT91C_SSC_RPR ((AT91_REG *) 0xFFFD4100) // (PDC_SSC) Receive Pointer Register -#define AT91C_SSC_RNCR ((AT91_REG *) 0xFFFD4114) // (PDC_SSC) Receive Next Counter Register -#define AT91C_SSC_TPR ((AT91_REG *) 0xFFFD4108) // (PDC_SSC) Transmit Pointer Register -#define AT91C_SSC_PTCR ((AT91_REG *) 0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register -#define AT91C_SSC_TCR ((AT91_REG *) 0xFFFD410C) // (PDC_SSC) Transmit Counter Register -#define AT91C_SSC_RCR ((AT91_REG *) 0xFFFD4104) // (PDC_SSC) Receive Counter Register -#define AT91C_SSC_RNPR ((AT91_REG *) 0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register -#define AT91C_SSC_TNPR ((AT91_REG *) 0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register -#define AT91C_SSC_PTSR ((AT91_REG *) 0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register -// ========== Register definition for SSC peripheral ========== -#define AT91C_SSC_RHR ((AT91_REG *) 0xFFFD4020) // (SSC) Receive Holding Register -#define AT91C_SSC_RSHR ((AT91_REG *) 0xFFFD4030) // (SSC) Receive Sync Holding Register -#define AT91C_SSC_TFMR ((AT91_REG *) 0xFFFD401C) // (SSC) Transmit Frame Mode Register -#define AT91C_SSC_IDR ((AT91_REG *) 0xFFFD4048) // (SSC) Interrupt Disable Register -#define AT91C_SSC_THR ((AT91_REG *) 0xFFFD4024) // (SSC) Transmit Holding Register -#define AT91C_SSC_RCMR ((AT91_REG *) 0xFFFD4010) // (SSC) Receive Clock ModeRegister -#define AT91C_SSC_IER ((AT91_REG *) 0xFFFD4044) // (SSC) Interrupt Enable Register -#define AT91C_SSC_TSHR ((AT91_REG *) 0xFFFD4034) // (SSC) Transmit Sync Holding Register -#define AT91C_SSC_SR ((AT91_REG *) 0xFFFD4040) // (SSC) Status Register -#define AT91C_SSC_CMR ((AT91_REG *) 0xFFFD4004) // (SSC) Clock Mode Register -#define AT91C_SSC_TCMR ((AT91_REG *) 0xFFFD4018) // (SSC) Transmit Clock Mode Register -#define AT91C_SSC_CR ((AT91_REG *) 0xFFFD4000) // (SSC) Control Register -#define AT91C_SSC_IMR ((AT91_REG *) 0xFFFD404C) // (SSC) Interrupt Mask Register -#define AT91C_SSC_RFMR ((AT91_REG *) 0xFFFD4014) // (SSC) Receive Frame Mode Register -// ========== Register definition for PDC_US1 peripheral ========== -#define AT91C_US1_RNCR ((AT91_REG *) 0xFFFC4114) // (PDC_US1) Receive Next Counter Register -#define AT91C_US1_PTCR ((AT91_REG *) 0xFFFC4120) // (PDC_US1) PDC Transfer Control Register -#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC410C) // (PDC_US1) Transmit Counter Register -#define AT91C_US1_PTSR ((AT91_REG *) 0xFFFC4124) // (PDC_US1) PDC Transfer Status Register -#define AT91C_US1_TNPR ((AT91_REG *) 0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register -#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4104) // (PDC_US1) Receive Counter Register -#define AT91C_US1_RNPR ((AT91_REG *) 0xFFFC4110) // (PDC_US1) Receive Next Pointer Register -#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4100) // (PDC_US1) Receive Pointer Register -#define AT91C_US1_TNCR ((AT91_REG *) 0xFFFC411C) // (PDC_US1) Transmit Next Counter Register -#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4108) // (PDC_US1) Transmit Pointer Register -// ========== Register definition for US1 peripheral ========== -#define AT91C_US1_IF ((AT91_REG *) 0xFFFC404C) // (US1) IRDA_FILTER Register -#define AT91C_US1_NER ((AT91_REG *) 0xFFFC4044) // (US1) Nb Errors Register -#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFC4024) // (US1) Receiver Time-out Register -#define AT91C_US1_CSR ((AT91_REG *) 0xFFFC4014) // (US1) Channel Status Register -#define AT91C_US1_IDR ((AT91_REG *) 0xFFFC400C) // (US1) Interrupt Disable Register -#define AT91C_US1_IER ((AT91_REG *) 0xFFFC4008) // (US1) Interrupt Enable Register -#define AT91C_US1_THR ((AT91_REG *) 0xFFFC401C) // (US1) Transmitter Holding Register -#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFC4028) // (US1) Transmitter Time-guard Register -#define AT91C_US1_RHR ((AT91_REG *) 0xFFFC4018) // (US1) Receiver Holding Register -#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFC4020) // (US1) Baud Rate Generator Register -#define AT91C_US1_IMR ((AT91_REG *) 0xFFFC4010) // (US1) Interrupt Mask Register -#define AT91C_US1_FIDI ((AT91_REG *) 0xFFFC4040) // (US1) FI_DI_Ratio Register -#define AT91C_US1_CR ((AT91_REG *) 0xFFFC4000) // (US1) Control Register -#define AT91C_US1_MR ((AT91_REG *) 0xFFFC4004) // (US1) Mode Register -// ========== Register definition for PDC_US0 peripheral ========== -#define AT91C_US0_TNPR ((AT91_REG *) 0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register -#define AT91C_US0_RNPR ((AT91_REG *) 0xFFFC0110) // (PDC_US0) Receive Next Pointer Register -#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC010C) // (PDC_US0) Transmit Counter Register -#define AT91C_US0_PTCR ((AT91_REG *) 0xFFFC0120) // (PDC_US0) PDC Transfer Control Register -#define AT91C_US0_PTSR ((AT91_REG *) 0xFFFC0124) // (PDC_US0) PDC Transfer Status Register -#define AT91C_US0_TNCR ((AT91_REG *) 0xFFFC011C) // (PDC_US0) Transmit Next Counter Register -#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0108) // (PDC_US0) Transmit Pointer Register -#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0104) // (PDC_US0) Receive Counter Register -#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0100) // (PDC_US0) Receive Pointer Register -#define AT91C_US0_RNCR ((AT91_REG *) 0xFFFC0114) // (PDC_US0) Receive Next Counter Register -// ========== Register definition for US0 peripheral ========== -#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFC0020) // (US0) Baud Rate Generator Register -#define AT91C_US0_NER ((AT91_REG *) 0xFFFC0044) // (US0) Nb Errors Register -#define AT91C_US0_CR ((AT91_REG *) 0xFFFC0000) // (US0) Control Register -#define AT91C_US0_IMR ((AT91_REG *) 0xFFFC0010) // (US0) Interrupt Mask Register -#define AT91C_US0_FIDI ((AT91_REG *) 0xFFFC0040) // (US0) FI_DI_Ratio Register -#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFC0028) // (US0) Transmitter Time-guard Register -#define AT91C_US0_MR ((AT91_REG *) 0xFFFC0004) // (US0) Mode Register -#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFC0024) // (US0) Receiver Time-out Register -#define AT91C_US0_CSR ((AT91_REG *) 0xFFFC0014) // (US0) Channel Status Register -#define AT91C_US0_RHR ((AT91_REG *) 0xFFFC0018) // (US0) Receiver Holding Register -#define AT91C_US0_IDR ((AT91_REG *) 0xFFFC000C) // (US0) Interrupt Disable Register -#define AT91C_US0_THR ((AT91_REG *) 0xFFFC001C) // (US0) Transmitter Holding Register -#define AT91C_US0_IF ((AT91_REG *) 0xFFFC004C) // (US0) IRDA_FILTER Register -#define AT91C_US0_IER ((AT91_REG *) 0xFFFC0008) // (US0) Interrupt Enable Register -// ========== Register definition for TWI peripheral ========== -#define AT91C_TWI_IER ((AT91_REG *) 0xFFFB8024) // (TWI) Interrupt Enable Register -#define AT91C_TWI_CR ((AT91_REG *) 0xFFFB8000) // (TWI) Control Register -#define AT91C_TWI_SR ((AT91_REG *) 0xFFFB8020) // (TWI) Status Register -#define AT91C_TWI_IMR ((AT91_REG *) 0xFFFB802C) // (TWI) Interrupt Mask Register -#define AT91C_TWI_THR ((AT91_REG *) 0xFFFB8034) // (TWI) Transmit Holding Register -#define AT91C_TWI_IDR ((AT91_REG *) 0xFFFB8028) // (TWI) Interrupt Disable Register -#define AT91C_TWI_IADR ((AT91_REG *) 0xFFFB800C) // (TWI) Internal Address Register -#define AT91C_TWI_MMR ((AT91_REG *) 0xFFFB8004) // (TWI) Master Mode Register -#define AT91C_TWI_CWGR ((AT91_REG *) 0xFFFB8010) // (TWI) Clock Waveform Generator Register -#define AT91C_TWI_RHR ((AT91_REG *) 0xFFFB8030) // (TWI) Receive Holding Register -// ========== Register definition for TC0 peripheral ========== -#define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register -#define AT91C_TC0_RC ((AT91_REG *) 0xFFFA001C) // (TC0) Register C -#define AT91C_TC0_RB ((AT91_REG *) 0xFFFA0018) // (TC0) Register B -#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFA0000) // (TC0) Channel Control Register -#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC0_IER ((AT91_REG *) 0xFFFA0024) // (TC0) Interrupt Enable Register -#define AT91C_TC0_RA ((AT91_REG *) 0xFFFA0014) // (TC0) Register A -#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFA0028) // (TC0) Interrupt Disable Register -#define AT91C_TC0_CV ((AT91_REG *) 0xFFFA0010) // (TC0) Counter Value -#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFA002C) // (TC0) Interrupt Mask Register -// ========== Register definition for TC1 peripheral ========== -#define AT91C_TC1_RB ((AT91_REG *) 0xFFFA0058) // (TC1) Register B -#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFA0040) // (TC1) Channel Control Register -#define AT91C_TC1_IER ((AT91_REG *) 0xFFFA0064) // (TC1) Interrupt Enable Register -#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFA0068) // (TC1) Interrupt Disable Register -#define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register -#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC1_RA ((AT91_REG *) 0xFFFA0054) // (TC1) Register A -#define AT91C_TC1_RC ((AT91_REG *) 0xFFFA005C) // (TC1) Register C -#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFA006C) // (TC1) Interrupt Mask Register -#define AT91C_TC1_CV ((AT91_REG *) 0xFFFA0050) // (TC1) Counter Value -// ========== Register definition for TC2 peripheral ========== -#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFA0080) // (TC2) Channel Control Register -#define AT91C_TC2_CV ((AT91_REG *) 0xFFFA0090) // (TC2) Counter Value -#define AT91C_TC2_RA ((AT91_REG *) 0xFFFA0094) // (TC2) Register A -#define AT91C_TC2_RB ((AT91_REG *) 0xFFFA0098) // (TC2) Register B -#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFA00A8) // (TC2) Interrupt Disable Register -#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFA00AC) // (TC2) Interrupt Mask Register -#define AT91C_TC2_RC ((AT91_REG *) 0xFFFA009C) // (TC2) Register C -#define AT91C_TC2_IER ((AT91_REG *) 0xFFFA00A4) // (TC2) Interrupt Enable Register -#define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register -// ========== Register definition for TCB peripheral ========== -#define AT91C_TCB_BMR ((AT91_REG *) 0xFFFA00C4) // (TCB) TC Block Mode Register -#define AT91C_TCB_BCR ((AT91_REG *) 0xFFFA00C0) // (TCB) TC Block Control Register -// ========== Register definition for PWMC_CH3 peripheral ========== -#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 0xFFFCC270) // (PWMC_CH3) Channel Update Register -#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 0xFFFCC274) // (PWMC_CH3) Reserved -#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 0xFFFCC268) // (PWMC_CH3) Channel Period Register -#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register -#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 0xFFFCC26C) // (PWMC_CH3) Channel Counter Register -#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 0xFFFCC260) // (PWMC_CH3) Channel Mode Register -// ========== Register definition for PWMC_CH2 peripheral ========== -#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 0xFFFCC254) // (PWMC_CH2) Reserved -#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 0xFFFCC240) // (PWMC_CH2) Channel Mode Register -#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 0xFFFCC24C) // (PWMC_CH2) Channel Counter Register -#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 0xFFFCC248) // (PWMC_CH2) Channel Period Register -#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 0xFFFCC250) // (PWMC_CH2) Channel Update Register -#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register -// ========== Register definition for PWMC_CH1 peripheral ========== -#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 0xFFFCC234) // (PWMC_CH1) Reserved -#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 0xFFFCC230) // (PWMC_CH1) Channel Update Register -#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 0xFFFCC228) // (PWMC_CH1) Channel Period Register -#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 0xFFFCC22C) // (PWMC_CH1) Channel Counter Register -#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register -#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 0xFFFCC220) // (PWMC_CH1) Channel Mode Register -// ========== Register definition for PWMC_CH0 peripheral ========== -#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 0xFFFCC214) // (PWMC_CH0) Reserved -#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 0xFFFCC208) // (PWMC_CH0) Channel Period Register -#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register -#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 0xFFFCC200) // (PWMC_CH0) Channel Mode Register -#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 0xFFFCC210) // (PWMC_CH0) Channel Update Register -#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 0xFFFCC20C) // (PWMC_CH0) Channel Counter Register -// ========== Register definition for PWMC peripheral ========== -#define AT91C_PWMC_IDR ((AT91_REG *) 0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register -#define AT91C_PWMC_DIS ((AT91_REG *) 0xFFFCC008) // (PWMC) PWMC Disable Register -#define AT91C_PWMC_IER ((AT91_REG *) 0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register -#define AT91C_PWMC_VR ((AT91_REG *) 0xFFFCC0FC) // (PWMC) PWMC Version Register -#define AT91C_PWMC_ISR ((AT91_REG *) 0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register -#define AT91C_PWMC_SR ((AT91_REG *) 0xFFFCC00C) // (PWMC) PWMC Status Register -#define AT91C_PWMC_IMR ((AT91_REG *) 0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register -#define AT91C_PWMC_MR ((AT91_REG *) 0xFFFCC000) // (PWMC) PWMC Mode Register -#define AT91C_PWMC_ENA ((AT91_REG *) 0xFFFCC004) // (PWMC) PWMC Enable Register -// ========== Register definition for UDP peripheral ========== -#define AT91C_UDP_IMR ((AT91_REG *) 0xFFFB0018) // (UDP) Interrupt Mask Register -#define AT91C_UDP_FADDR ((AT91_REG *) 0xFFFB0008) // (UDP) Function Address Register -#define AT91C_UDP_NUM ((AT91_REG *) 0xFFFB0000) // (UDP) Frame Number Register -#define AT91C_UDP_FDR ((AT91_REG *) 0xFFFB0050) // (UDP) Endpoint FIFO Data Register -#define AT91C_UDP_ISR ((AT91_REG *) 0xFFFB001C) // (UDP) Interrupt Status Register -#define AT91C_UDP_CSR ((AT91_REG *) 0xFFFB0030) // (UDP) Endpoint Control and Status Register -#define AT91C_UDP_IDR ((AT91_REG *) 0xFFFB0014) // (UDP) Interrupt Disable Register -#define AT91C_UDP_ICR ((AT91_REG *) 0xFFFB0020) // (UDP) Interrupt Clear Register -#define AT91C_UDP_RSTEP ((AT91_REG *) 0xFFFB0028) // (UDP) Reset Endpoint Register -#define AT91C_UDP_TXVC ((AT91_REG *) 0xFFFB0074) // (UDP) Transceiver Control Register -#define AT91C_UDP_GLBSTATE ((AT91_REG *) 0xFFFB0004) // (UDP) Global State Register -#define AT91C_UDP_IER ((AT91_REG *) 0xFFFB0010) // (UDP) Interrupt Enable Register - -// ***************************************************************************** -// PIO DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_PIO_PA0 ((unsigned int) 1 << 0) // Pin Controlled by PA0 -#define AT91C_PA0_PWM0 ((unsigned int) AT91C_PIO_PA0) // PWM Channel 0 -#define AT91C_PA0_TIOA0 ((unsigned int) AT91C_PIO_PA0) // Timer Counter 0 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA1 ((unsigned int) 1 << 1) // Pin Controlled by PA1 -#define AT91C_PA1_PWM1 ((unsigned int) AT91C_PIO_PA1) // PWM Channel 1 -#define AT91C_PA1_TIOB0 ((unsigned int) AT91C_PIO_PA1) // Timer Counter 0 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA10 ((unsigned int) 1 << 10) // Pin Controlled by PA10 -#define AT91C_PA10_DTXD ((unsigned int) AT91C_PIO_PA10) // DBGU Debug Transmit Data -#define AT91C_PA10_NPCS2 ((unsigned int) AT91C_PIO_PA10) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA11 ((unsigned int) 1 << 11) // Pin Controlled by PA11 -#define AT91C_PA11_NPCS0 ((unsigned int) AT91C_PIO_PA11) // SPI Peripheral Chip Select 0 -#define AT91C_PA11_PWM0 ((unsigned int) AT91C_PIO_PA11) // PWM Channel 0 -#define AT91C_PIO_PA12 ((unsigned int) 1 << 12) // Pin Controlled by PA12 -#define AT91C_PA12_MISO ((unsigned int) AT91C_PIO_PA12) // SPI Master In Slave -#define AT91C_PA12_PWM1 ((unsigned int) AT91C_PIO_PA12) // PWM Channel 1 -#define AT91C_PIO_PA13 ((unsigned int) 1 << 13) // Pin Controlled by PA13 -#define AT91C_PA13_MOSI ((unsigned int) AT91C_PIO_PA13) // SPI Master Out Slave -#define AT91C_PA13_PWM2 ((unsigned int) AT91C_PIO_PA13) // PWM Channel 2 -#define AT91C_PIO_PA14 ((unsigned int) 1 << 14) // Pin Controlled by PA14 -#define AT91C_PA14_SPCK ((unsigned int) AT91C_PIO_PA14) // SPI Serial Clock -#define AT91C_PA14_PWM3 ((unsigned int) AT91C_PIO_PA14) // PWM Channel 3 -#define AT91C_PIO_PA15 ((unsigned int) 1 << 15) // Pin Controlled by PA15 -#define AT91C_PA15_TF ((unsigned int) AT91C_PIO_PA15) // SSC Transmit Frame Sync -#define AT91C_PA15_TIOA1 ((unsigned int) AT91C_PIO_PA15) // Timer Counter 1 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA16 ((unsigned int) 1 << 16) // Pin Controlled by PA16 -#define AT91C_PA16_TK ((unsigned int) AT91C_PIO_PA16) // SSC Transmit Clock -#define AT91C_PA16_TIOB1 ((unsigned int) AT91C_PIO_PA16) // Timer Counter 1 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA17 ((unsigned int) 1 << 17) // Pin Controlled by PA17 -#define AT91C_PA17_TD ((unsigned int) AT91C_PIO_PA17) // SSC Transmit data -#define AT91C_PA17_PCK1 ((unsigned int) AT91C_PIO_PA17) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA18 ((unsigned int) 1 << 18) // Pin Controlled by PA18 -#define AT91C_PA18_RD ((unsigned int) AT91C_PIO_PA18) // SSC Receive Data -#define AT91C_PA18_PCK2 ((unsigned int) AT91C_PIO_PA18) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA19 ((unsigned int) 1 << 19) // Pin Controlled by PA19 -#define AT91C_PA19_RK ((unsigned int) AT91C_PIO_PA19) // SSC Receive Clock -#define AT91C_PA19_FIQ ((unsigned int) AT91C_PIO_PA19) // AIC Fast Interrupt Input -#define AT91C_PIO_PA2 ((unsigned int) 1 << 2) // Pin Controlled by PA2 -#define AT91C_PA2_PWM2 ((unsigned int) AT91C_PIO_PA2) // PWM Channel 2 -#define AT91C_PA2_SCK0 ((unsigned int) AT91C_PIO_PA2) // USART 0 Serial Clock -#define AT91C_PIO_PA20 ((unsigned int) 1 << 20) // Pin Controlled by PA20 -#define AT91C_PA20_RF ((unsigned int) AT91C_PIO_PA20) // SSC Receive Frame Sync -#define AT91C_PA20_IRQ0 ((unsigned int) AT91C_PIO_PA20) // External Interrupt 0 -#define AT91C_PIO_PA21 ((unsigned int) 1 << 21) // Pin Controlled by PA21 -#define AT91C_PA21_RXD1 ((unsigned int) AT91C_PIO_PA21) // USART 1 Receive Data -#define AT91C_PA21_PCK1 ((unsigned int) AT91C_PIO_PA21) // PMC Programmable Clock Output 1 -#define AT91C_PIO_PA22 ((unsigned int) 1 << 22) // Pin Controlled by PA22 -#define AT91C_PA22_TXD1 ((unsigned int) AT91C_PIO_PA22) // USART 1 Transmit Data -#define AT91C_PA22_NPCS3 ((unsigned int) AT91C_PIO_PA22) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA23 ((unsigned int) 1 << 23) // Pin Controlled by PA23 -#define AT91C_PA23_SCK1 ((unsigned int) AT91C_PIO_PA23) // USART 1 Serial Clock -#define AT91C_PA23_PWM0 ((unsigned int) AT91C_PIO_PA23) // PWM Channel 0 -#define AT91C_PIO_PA24 ((unsigned int) 1 << 24) // Pin Controlled by PA24 -#define AT91C_PA24_RTS1 ((unsigned int) AT91C_PIO_PA24) // USART 1 Ready To Send -#define AT91C_PA24_PWM1 ((unsigned int) AT91C_PIO_PA24) // PWM Channel 1 -#define AT91C_PIO_PA25 ((unsigned int) 1 << 25) // Pin Controlled by PA25 -#define AT91C_PA25_CTS1 ((unsigned int) AT91C_PIO_PA25) // USART 1 Clear To Send -#define AT91C_PA25_PWM2 ((unsigned int) AT91C_PIO_PA25) // PWM Channel 2 -#define AT91C_PIO_PA26 ((unsigned int) 1 << 26) // Pin Controlled by PA26 -#define AT91C_PA26_DCD1 ((unsigned int) AT91C_PIO_PA26) // USART 1 Data Carrier Detect -#define AT91C_PA26_TIOA2 ((unsigned int) AT91C_PIO_PA26) // Timer Counter 2 Multipurpose Timer I/O Pin A -#define AT91C_PIO_PA27 ((unsigned int) 1 << 27) // Pin Controlled by PA27 -#define AT91C_PA27_DTR1 ((unsigned int) AT91C_PIO_PA27) // USART 1 Data Terminal ready -#define AT91C_PA27_TIOB2 ((unsigned int) AT91C_PIO_PA27) // Timer Counter 2 Multipurpose Timer I/O Pin B -#define AT91C_PIO_PA28 ((unsigned int) 1 << 28) // Pin Controlled by PA28 -#define AT91C_PA28_DSR1 ((unsigned int) AT91C_PIO_PA28) // USART 1 Data Set ready -#define AT91C_PA28_TCLK1 ((unsigned int) AT91C_PIO_PA28) // Timer Counter 1 external clock input -#define AT91C_PIO_PA29 ((unsigned int) 1 << 29) // Pin Controlled by PA29 -#define AT91C_PA29_RI1 ((unsigned int) AT91C_PIO_PA29) // USART 1 Ring Indicator -#define AT91C_PA29_TCLK2 ((unsigned int) AT91C_PIO_PA29) // Timer Counter 2 external clock input -#define AT91C_PIO_PA3 ((unsigned int) 1 << 3) // Pin Controlled by PA3 -#define AT91C_PA3_TWD ((unsigned int) AT91C_PIO_PA3) // TWI Two-wire Serial Data -#define AT91C_PA3_NPCS3 ((unsigned int) AT91C_PIO_PA3) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA30 ((unsigned int) 1 << 30) // Pin Controlled by PA30 -#define AT91C_PA30_IRQ1 ((unsigned int) AT91C_PIO_PA30) // External Interrupt 1 -#define AT91C_PA30_NPCS2 ((unsigned int) AT91C_PIO_PA30) // SPI Peripheral Chip Select 2 -#define AT91C_PIO_PA31 ((unsigned int) 1 << 31) // Pin Controlled by PA31 -#define AT91C_PA31_NPCS1 ((unsigned int) AT91C_PIO_PA31) // SPI Peripheral Chip Select 1 -#define AT91C_PA31_PCK2 ((unsigned int) AT91C_PIO_PA31) // PMC Programmable Clock Output 2 -#define AT91C_PIO_PA4 ((unsigned int) 1 << 4) // Pin Controlled by PA4 -#define AT91C_PA4_TWCK ((unsigned int) AT91C_PIO_PA4) // TWI Two-wire Serial Clock -#define AT91C_PA4_TCLK0 ((unsigned int) AT91C_PIO_PA4) // Timer Counter 0 external clock input -#define AT91C_PIO_PA5 ((unsigned int) 1 << 5) // Pin Controlled by PA5 -#define AT91C_PA5_RXD0 ((unsigned int) AT91C_PIO_PA5) // USART 0 Receive Data -#define AT91C_PA5_NPCS3 ((unsigned int) AT91C_PIO_PA5) // SPI Peripheral Chip Select 3 -#define AT91C_PIO_PA6 ((unsigned int) 1 << 6) // Pin Controlled by PA6 -#define AT91C_PA6_TXD0 ((unsigned int) AT91C_PIO_PA6) // USART 0 Transmit Data -#define AT91C_PA6_PCK0 ((unsigned int) AT91C_PIO_PA6) // PMC Programmable Clock Output 0 -#define AT91C_PIO_PA7 ((unsigned int) 1 << 7) // Pin Controlled by PA7 -#define AT91C_PA7_RTS0 ((unsigned int) AT91C_PIO_PA7) // USART 0 Ready To Send -#define AT91C_PA7_PWM3 ((unsigned int) AT91C_PIO_PA7) // PWM Channel 3 -#define AT91C_PIO_PA8 ((unsigned int) 1 << 8) // Pin Controlled by PA8 -#define AT91C_PA8_CTS0 ((unsigned int) AT91C_PIO_PA8) // USART 0 Clear To Send -#define AT91C_PA8_ADTRG ((unsigned int) AT91C_PIO_PA8) // ADC External Trigger -#define AT91C_PIO_PA9 ((unsigned int) 1 << 9) // Pin Controlled by PA9 -#define AT91C_PA9_DRXD ((unsigned int) AT91C_PIO_PA9) // DBGU Debug Receive Data -#define AT91C_PA9_NPCS1 ((unsigned int) AT91C_PIO_PA9) // SPI Peripheral Chip Select 1 - -// ***************************************************************************** -// PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ) -#define AT91C_ID_SYS ((unsigned int) 1) // System Peripheral -#define AT91C_ID_PIOA ((unsigned int) 2) // Parallel IO Controller -#define AT91C_ID_3_Reserved ((unsigned int) 3) // Reserved -#define AT91C_ID_ADC ((unsigned int) 4) // Analog-to-Digital Converter -#define AT91C_ID_SPI ((unsigned int) 5) // Serial Peripheral Interface -#define AT91C_ID_US0 ((unsigned int) 6) // USART 0 -#define AT91C_ID_US1 ((unsigned int) 7) // USART 1 -#define AT91C_ID_SSC ((unsigned int) 8) // Serial Synchronous Controller -#define AT91C_ID_TWI ((unsigned int) 9) // Two-Wire Interface -#define AT91C_ID_PWMC ((unsigned int) 10) // PWM Controller -#define AT91C_ID_UDP ((unsigned int) 11) // USB Device Port -#define AT91C_ID_TC0 ((unsigned int) 12) // Timer Counter 0 -#define AT91C_ID_TC1 ((unsigned int) 13) // Timer Counter 1 -#define AT91C_ID_TC2 ((unsigned int) 14) // Timer Counter 2 -#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved -#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved -#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved -#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved -#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved -#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved -#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved -#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved -#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved -#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved -#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved -#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved -#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved -#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved -#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved -#define AT91C_ID_IRQ0 ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0) -#define AT91C_ID_IRQ1 ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1) -#define AT91C_ALL_INT ((unsigned int) 0xC0007FF7) // ALL VALID INTERRUPTS - -// ***************************************************************************** -// BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -#define AT91C_BASE_SYS ((AT91PS_SYS) 0xFFFFF000) // (SYS) Base Address -#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address -#define AT91C_BASE_PDC_DBGU ((AT91PS_PDC) 0xFFFFF300) // (PDC_DBGU) Base Address -#define AT91C_BASE_DBGU ((AT91PS_DBGU) 0xFFFFF200) // (DBGU) Base Address -#define AT91C_BASE_PIOA ((AT91PS_PIO) 0xFFFFF400) // (PIOA) Base Address -#define AT91C_BASE_CKGR ((AT91PS_CKGR) 0xFFFFFC20) // (CKGR) Base Address -#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) // (PMC) Base Address -#define AT91C_BASE_RSTC ((AT91PS_RSTC) 0xFFFFFD00) // (RSTC) Base Address -#define AT91C_BASE_RTTC ((AT91PS_RTTC) 0xFFFFFD20) // (RTTC) Base Address -#define AT91C_BASE_PITC ((AT91PS_PITC) 0xFFFFFD30) // (PITC) Base Address -#define AT91C_BASE_WDTC ((AT91PS_WDTC) 0xFFFFFD40) // (WDTC) Base Address -#define AT91C_BASE_VREG ((AT91PS_VREG) 0xFFFFFD60) // (VREG) Base Address -#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) // (MC) Base Address -#define AT91C_BASE_PDC_SPI ((AT91PS_PDC) 0xFFFE0100) // (PDC_SPI) Base Address -#define AT91C_BASE_SPI ((AT91PS_SPI) 0xFFFE0000) // (SPI) Base Address -#define AT91C_BASE_PDC_ADC ((AT91PS_PDC) 0xFFFD8100) // (PDC_ADC) Base Address -#define AT91C_BASE_ADC ((AT91PS_ADC) 0xFFFD8000) // (ADC) Base Address -#define AT91C_BASE_PDC_SSC ((AT91PS_PDC) 0xFFFD4100) // (PDC_SSC) Base Address -#define AT91C_BASE_SSC ((AT91PS_SSC) 0xFFFD4000) // (SSC) Base Address -#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4100) // (PDC_US1) Base Address -#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) // (US1) Base Address -#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0100) // (PDC_US0) Base Address -#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) // (US0) Base Address -#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) // (TWI) Base Address -#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) // (TC0) Base Address -#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA0040) // (TC1) Base Address -#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFA0080) // (TC2) Base Address -#define AT91C_BASE_TCB ((AT91PS_TCB) 0xFFFA0000) // (TCB) Base Address -#define AT91C_BASE_PWMC_CH3 ((AT91PS_PWMC_CH) 0xFFFCC260) // (PWMC_CH3) Base Address -#define AT91C_BASE_PWMC_CH2 ((AT91PS_PWMC_CH) 0xFFFCC240) // (PWMC_CH2) Base Address -#define AT91C_BASE_PWMC_CH1 ((AT91PS_PWMC_CH) 0xFFFCC220) // (PWMC_CH1) Base Address -#define AT91C_BASE_PWMC_CH0 ((AT91PS_PWMC_CH) 0xFFFCC200) // (PWMC_CH0) Base Address -#define AT91C_BASE_PWMC ((AT91PS_PWMC) 0xFFFCC000) // (PWMC) Base Address -#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) // (UDP) Base Address - -// ***************************************************************************** -// MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// ***************************************************************************** -// ISRAM -#define AT91C_ISRAM ((char *) 0x00200000) // Internal SRAM base address -#define AT91C_ISRAM_SIZE ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbytes) -// IFLASH -#define AT91C_IFLASH ((char *) 0x00100000) // Internal FLASH base address -#define AT91C_IFLASH_SIZE ((unsigned int) 0x00010000) // Internal FLASH size in byte (64 Kbytes) -#define AT91C_IFLASH_PAGE_SIZE ((unsigned int) 128) // Internal FLASH Page Size: 128 bytes -#define AT91C_IFLASH_LOCK_REGION_SIZE ((unsigned int) 4096) // Internal FLASH Lock Region Size: 4 Kbytes -#define AT91C_IFLASH_NB_OF_PAGES ((unsigned int) 256) // Internal FLASH Number of Pages: 256 bytes -#define AT91C_IFLASH_NB_OF_LOCK_BITS ((unsigned int) 8) // Internal FLASH Number of Lock Bits: 8 bytes -#endif /* __IAR_SYSTEMS_ICC__ */ - -#ifdef __IAR_SYSTEMS_ASM__ - -// - Hardware register definition - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR System Peripherals -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Advanced Interrupt Controller -// - ***************************************************************************** -// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- -AT91C_AIC_PRIOR EQU (0x7 << 0) ;- (AIC) Priority Level -AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level -AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level -AT91C_AIC_SRCTYPE EQU (0x3 << 5) ;- (AIC) Interrupt Source Type -AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 << 5) ;- (AIC) Internal Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 << 5) ;- (AIC) External Sources Code Label Low-level Sensitive -AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 << 5) ;- (AIC) Internal Sources Code Label Positive Edge triggered -AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 << 5) ;- (AIC) External Sources Code Label Negative Edge triggered -AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 << 5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive -AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 << 5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered -// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- -AT91C_AIC_NFIQ EQU (0x1 << 0) ;- (AIC) NFIQ Status -AT91C_AIC_NIRQ EQU (0x1 << 1) ;- (AIC) NIRQ Status -// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- -AT91C_AIC_DCR_PROT EQU (0x1 << 0) ;- (AIC) Protection Mode -AT91C_AIC_DCR_GMSK EQU (0x1 << 1) ;- (AIC) General Mask - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Peripheral DMA Controller -// - ***************************************************************************** -// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- -AT91C_PDC_RXTEN EQU (0x1 << 0) ;- (PDC) Receiver Transfer Enable -AT91C_PDC_RXTDIS EQU (0x1 << 1) ;- (PDC) Receiver Transfer Disable -AT91C_PDC_TXTEN EQU (0x1 << 8) ;- (PDC) Transmitter Transfer Enable -AT91C_PDC_TXTDIS EQU (0x1 << 9) ;- (PDC) Transmitter Transfer Disable -// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Debug Unit -// - ***************************************************************************** -// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_RSTRX EQU (0x1 << 2) ;- (DBGU) Reset Receiver -AT91C_US_RSTTX EQU (0x1 << 3) ;- (DBGU) Reset Transmitter -AT91C_US_RXEN EQU (0x1 << 4) ;- (DBGU) Receiver Enable -AT91C_US_RXDIS EQU (0x1 << 5) ;- (DBGU) Receiver Disable -AT91C_US_TXEN EQU (0x1 << 6) ;- (DBGU) Transmitter Enable -AT91C_US_TXDIS EQU (0x1 << 7) ;- (DBGU) Transmitter Disable -AT91C_US_RSTSTA EQU (0x1 << 8) ;- (DBGU) Reset Status Bits -// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_PAR EQU (0x7 << 9) ;- (DBGU) Parity type -AT91C_US_PAR_EVEN EQU (0x0 << 9) ;- (DBGU) Even Parity -AT91C_US_PAR_ODD EQU (0x1 << 9) ;- (DBGU) Odd Parity -AT91C_US_PAR_SPACE EQU (0x2 << 9) ;- (DBGU) Parity forced to 0 (Space) -AT91C_US_PAR_MARK EQU (0x3 << 9) ;- (DBGU) Parity forced to 1 (Mark) -AT91C_US_PAR_NONE EQU (0x4 << 9) ;- (DBGU) No Parity -AT91C_US_PAR_MULTI_DROP EQU (0x6 << 9) ;- (DBGU) Multi-drop mode -AT91C_US_CHMODE EQU (0x3 << 14) ;- (DBGU) Channel Mode -AT91C_US_CHMODE_NORMAL EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART. -AT91C_US_CHMODE_AUTO EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin. -AT91C_US_CHMODE_LOCAL EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal. -AT91C_US_CHMODE_REMOTE EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin. -// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXRDY EQU (0x1 << 0) ;- (DBGU) RXRDY Interrupt -AT91C_US_TXRDY EQU (0x1 << 1) ;- (DBGU) TXRDY Interrupt -AT91C_US_ENDRX EQU (0x1 << 3) ;- (DBGU) End of Receive Transfer Interrupt -AT91C_US_ENDTX EQU (0x1 << 4) ;- (DBGU) End of Transmit Interrupt -AT91C_US_OVRE EQU (0x1 << 5) ;- (DBGU) Overrun Interrupt -AT91C_US_FRAME EQU (0x1 << 6) ;- (DBGU) Framing Error Interrupt -AT91C_US_PARE EQU (0x1 << 7) ;- (DBGU) Parity Error Interrupt -AT91C_US_TXEMPTY EQU (0x1 << 9) ;- (DBGU) TXEMPTY Interrupt -AT91C_US_TXBUFE EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt -AT91C_US_RXBUFF EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt -AT91C_US_COMM_TX EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt -AT91C_US_COMM_RX EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt -// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- -// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- -AT91C_US_FORCE_NTRST EQU (0x1 << 0) ;- (DBGU) Force NTRST in JTAG - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Parallel Input Output Controler -// - ***************************************************************************** - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Clock Generator Controler -// - ***************************************************************************** -// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- -AT91C_CKGR_MOSCEN EQU (0x1 << 0) ;- (CKGR) Main Oscillator Enable -AT91C_CKGR_OSCBYPASS EQU (0x1 << 1) ;- (CKGR) Main Oscillator Bypass -AT91C_CKGR_OSCOUNT EQU (0xFF << 8) ;- (CKGR) Main Oscillator Start-up Time -// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- -AT91C_CKGR_MAINF EQU (0xFFFF << 0) ;- (CKGR) Main Clock Frequency -AT91C_CKGR_MAINRDY EQU (0x1 << 16) ;- (CKGR) Main Clock Ready -// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- -AT91C_CKGR_DIV EQU (0xFF << 0) ;- (CKGR) Divider Selected -AT91C_CKGR_DIV_0 EQU (0x0) ;- (CKGR) Divider output is 0 -AT91C_CKGR_DIV_BYPASS EQU (0x1) ;- (CKGR) Divider is bypassed -AT91C_CKGR_PLLCOUNT EQU (0x3F << 8) ;- (CKGR) PLL Counter -AT91C_CKGR_OUT EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range -AT91C_CKGR_OUT_0 EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_1 EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_2 EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_OUT_3 EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet -AT91C_CKGR_MUL EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier -AT91C_CKGR_USBDIV EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks -AT91C_CKGR_USBDIV_0 EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output -AT91C_CKGR_USBDIV_1 EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2 -AT91C_CKGR_USBDIV_2 EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Power Management Controler -// - ***************************************************************************** -// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- -AT91C_PMC_PCK EQU (0x1 << 0) ;- (PMC) Processor Clock -AT91C_PMC_UDP EQU (0x1 << 7) ;- (PMC) USB Device Port Clock -AT91C_PMC_PCK0 EQU (0x1 << 8) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK1 EQU (0x1 << 9) ;- (PMC) Programmable Clock Output -AT91C_PMC_PCK2 EQU (0x1 << 10) ;- (PMC) Programmable Clock Output -// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- -// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- -// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- -// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- -// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- -// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- -AT91C_PMC_CSS EQU (0x3 << 0) ;- (PMC) Programmable Clock Selection -AT91C_PMC_CSS_SLOW_CLK EQU (0x0) ;- (PMC) Slow Clock is selected -AT91C_PMC_CSS_MAIN_CLK EQU (0x1) ;- (PMC) Main Clock is selected -AT91C_PMC_CSS_PLL_CLK EQU (0x3) ;- (PMC) Clock from PLL is selected -AT91C_PMC_PRES EQU (0x7 << 2) ;- (PMC) Programmable Clock Prescaler -AT91C_PMC_PRES_CLK EQU (0x0 << 2) ;- (PMC) Selected clock -AT91C_PMC_PRES_CLK_2 EQU (0x1 << 2) ;- (PMC) Selected clock divided by 2 -AT91C_PMC_PRES_CLK_4 EQU (0x2 << 2) ;- (PMC) Selected clock divided by 4 -AT91C_PMC_PRES_CLK_8 EQU (0x3 << 2) ;- (PMC) Selected clock divided by 8 -AT91C_PMC_PRES_CLK_16 EQU (0x4 << 2) ;- (PMC) Selected clock divided by 16 -AT91C_PMC_PRES_CLK_32 EQU (0x5 << 2) ;- (PMC) Selected clock divided by 32 -AT91C_PMC_PRES_CLK_64 EQU (0x6 << 2) ;- (PMC) Selected clock divided by 64 -// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- -// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- -AT91C_PMC_MOSCS EQU (0x1 << 0) ;- (PMC) MOSC Status/Enable/Disable/Mask -AT91C_PMC_LOCK EQU (0x1 << 2) ;- (PMC) PLL Status/Enable/Disable/Mask -AT91C_PMC_MCKRDY EQU (0x1 << 3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK0RDY EQU (0x1 << 8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK1RDY EQU (0x1 << 9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask -AT91C_PMC_PCK2RDY EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask -// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- -// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- -// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Reset Controller Interface -// - ***************************************************************************** -// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- -AT91C_RSTC_PROCRST EQU (0x1 << 0) ;- (RSTC) Processor Reset -AT91C_RSTC_PERRST EQU (0x1 << 2) ;- (RSTC) Peripheral Reset -AT91C_RSTC_EXTRST EQU (0x1 << 3) ;- (RSTC) External Reset -AT91C_RSTC_KEY EQU (0xFF << 24) ;- (RSTC) Password -// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- -AT91C_RSTC_URSTS EQU (0x1 << 0) ;- (RSTC) User Reset Status -AT91C_RSTC_BODSTS EQU (0x1 << 1) ;- (RSTC) Brownout Detection Status -AT91C_RSTC_RSTTYP EQU (0x7 << 8) ;- (RSTC) Reset Type -AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 << 8) ;- (RSTC) Power-up Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WAKEUP EQU (0x1 << 8) ;- (RSTC) WakeUp Reset. VDDCORE rising. -AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 << 8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured. -AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 << 8) ;- (RSTC) Software Reset. Processor reset required by the software. -AT91C_RSTC_RSTTYP_USER EQU (0x4 << 8) ;- (RSTC) User Reset. NRST pin detected low. -AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 << 8) ;- (RSTC) Brownout Reset occured. -AT91C_RSTC_NRSTL EQU (0x1 << 16) ;- (RSTC) NRST pin level -AT91C_RSTC_SRCMP EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress. -// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- -AT91C_RSTC_URSTEN EQU (0x1 << 0) ;- (RSTC) User Reset Enable -AT91C_RSTC_URSTIEN EQU (0x1 << 4) ;- (RSTC) User Reset Interrupt Enable -AT91C_RSTC_ERSTL EQU (0xF << 8) ;- (RSTC) User Reset Length -AT91C_RSTC_BODIEN EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Real Time Timer Controller Interface -// - ***************************************************************************** -// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- -AT91C_RTTC_RTPRES EQU (0xFFFF << 0) ;- (RTTC) Real-time Timer Prescaler Value -AT91C_RTTC_ALMIEN EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable -AT91C_RTTC_RTTINCIEN EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable -AT91C_RTTC_RTTRST EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart -// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- -AT91C_RTTC_ALMV EQU (0x0 << 0) ;- (RTTC) Alarm Value -// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- -AT91C_RTTC_CRTV EQU (0x0 << 0) ;- (RTTC) Current Real-time Value -// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- -AT91C_RTTC_ALMS EQU (0x1 << 0) ;- (RTTC) Real-time Alarm Status -AT91C_RTTC_RTTINC EQU (0x1 << 1) ;- (RTTC) Real-time Timer Increment - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Periodic Interval Timer Controller Interface -// - ***************************************************************************** -// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- -AT91C_PITC_PIV EQU (0xFFFFF << 0) ;- (PITC) Periodic Interval Value -AT91C_PITC_PITEN EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled -AT91C_PITC_PITIEN EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable -// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- -AT91C_PITC_PITS EQU (0x1 << 0) ;- (PITC) Periodic Interval Timer Status -// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- -AT91C_PITC_CPIV EQU (0xFFFFF << 0) ;- (PITC) Current Periodic Interval Value -AT91C_PITC_PICNT EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter -// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Watchdog Timer Controller Interface -// - ***************************************************************************** -// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- -AT91C_WDTC_WDRSTT EQU (0x1 << 0) ;- (WDTC) Watchdog Restart -AT91C_WDTC_KEY EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password -// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- -AT91C_WDTC_WDV EQU (0xFFF << 0) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDFIEN EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable -AT91C_WDTC_WDRSTEN EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable -AT91C_WDTC_WDRPROC EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart -AT91C_WDTC_WDDIS EQU (0x1 << 15) ;- (WDTC) Watchdog Disable -AT91C_WDTC_WDD EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value -AT91C_WDTC_WDDBGHLT EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt -AT91C_WDTC_WDIDLEHLT EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt -// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- -AT91C_WDTC_WDUNF EQU (0x1 << 0) ;- (WDTC) Watchdog Underflow -AT91C_WDTC_WDERR EQU (0x1 << 1) ;- (WDTC) Watchdog Error - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Voltage Regulator Mode Controller Interface -// - ***************************************************************************** -// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- -AT91C_VREG_PSTDBY EQU (0x1 << 0) ;- (VREG) Voltage Regulator Power Standby Mode - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Memory Controller Interface -// - ***************************************************************************** -// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- -AT91C_MC_RCB EQU (0x1 << 0) ;- (MC) Remap Command Bit -// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- -AT91C_MC_UNDADD EQU (0x1 << 0) ;- (MC) Undefined Addess Abort Status -AT91C_MC_MISADD EQU (0x1 << 1) ;- (MC) Misaligned Addess Abort Status -AT91C_MC_ABTSZ EQU (0x3 << 8) ;- (MC) Abort Size Status -AT91C_MC_ABTSZ_BYTE EQU (0x0 << 8) ;- (MC) Byte -AT91C_MC_ABTSZ_HWORD EQU (0x1 << 8) ;- (MC) Half-word -AT91C_MC_ABTSZ_WORD EQU (0x2 << 8) ;- (MC) Word -AT91C_MC_ABTTYP EQU (0x3 << 10) ;- (MC) Abort Type Status -AT91C_MC_ABTTYP_DATAR EQU (0x0 << 10) ;- (MC) Data Read -AT91C_MC_ABTTYP_DATAW EQU (0x1 << 10) ;- (MC) Data Write -AT91C_MC_ABTTYP_FETCH EQU (0x2 << 10) ;- (MC) Code Fetch -AT91C_MC_MST0 EQU (0x1 << 16) ;- (MC) Master 0 Abort Source -AT91C_MC_MST1 EQU (0x1 << 17) ;- (MC) Master 1 Abort Source -AT91C_MC_SVMST0 EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source -AT91C_MC_SVMST1 EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source -// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- -AT91C_MC_FRDY EQU (0x1 << 0) ;- (MC) Flash Ready -AT91C_MC_LOCKE EQU (0x1 << 2) ;- (MC) Lock Error -AT91C_MC_PROGE EQU (0x1 << 3) ;- (MC) Programming Error -AT91C_MC_NEBP EQU (0x1 << 7) ;- (MC) No Erase Before Programming -AT91C_MC_FWS EQU (0x3 << 8) ;- (MC) Flash Wait State -AT91C_MC_FWS_0FWS EQU (0x0 << 8) ;- (MC) 1 cycle for Read, 2 for Write operations -AT91C_MC_FWS_1FWS EQU (0x1 << 8) ;- (MC) 2 cycles for Read, 3 for Write operations -AT91C_MC_FWS_2FWS EQU (0x2 << 8) ;- (MC) 3 cycles for Read, 4 for Write operations -AT91C_MC_FWS_3FWS EQU (0x3 << 8) ;- (MC) 4 cycles for Read, 4 for Write operations -AT91C_MC_FMCN EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number -// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- -AT91C_MC_FCMD EQU (0xF << 0) ;- (MC) Flash Command -AT91C_MC_FCMD_START_PROG EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN. -AT91C_MC_FCMD_LOCK EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed. -AT91C_MC_FCMD_UNLOCK EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN. -AT91C_MC_FCMD_ERASE_ALL EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled. -AT91C_MC_FCMD_SET_GP_NVM EQU (0xB) ;- (MC) Set General Purpose NVM bits. -AT91C_MC_FCMD_CLR_GP_NVM EQU (0xD) ;- (MC) Clear General Purpose NVM bits. -AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit. -AT91C_MC_PAGEN EQU (0x3FF << 8) ;- (MC) Page Number -AT91C_MC_KEY EQU (0xFF << 24) ;- (MC) Writing Protect Key -// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- -AT91C_MC_SECURITY EQU (0x1 << 4) ;- (MC) Security Bit Status -AT91C_MC_GPNVM0 EQU (0x1 << 8) ;- (MC) Sector 0 Lock Status -AT91C_MC_GPNVM1 EQU (0x1 << 9) ;- (MC) Sector 1 Lock Status -AT91C_MC_GPNVM2 EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status -AT91C_MC_GPNVM3 EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status -AT91C_MC_GPNVM4 EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status -AT91C_MC_GPNVM5 EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status -AT91C_MC_GPNVM6 EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status -AT91C_MC_GPNVM7 EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS0 EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status -AT91C_MC_LOCKS1 EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status -AT91C_MC_LOCKS2 EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status -AT91C_MC_LOCKS3 EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status -AT91C_MC_LOCKS4 EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status -AT91C_MC_LOCKS5 EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status -AT91C_MC_LOCKS6 EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status -AT91C_MC_LOCKS7 EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status -AT91C_MC_LOCKS8 EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status -AT91C_MC_LOCKS9 EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status -AT91C_MC_LOCKS10 EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status -AT91C_MC_LOCKS11 EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status -AT91C_MC_LOCKS12 EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status -AT91C_MC_LOCKS13 EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status -AT91C_MC_LOCKS14 EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status -AT91C_MC_LOCKS15 EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Serial Parallel Interface -// - ***************************************************************************** -// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- -AT91C_SPI_SPIEN EQU (0x1 << 0) ;- (SPI) SPI Enable -AT91C_SPI_SPIDIS EQU (0x1 << 1) ;- (SPI) SPI Disable -AT91C_SPI_SWRST EQU (0x1 << 7) ;- (SPI) SPI Software reset -AT91C_SPI_LASTXFER EQU (0x1 << 24) ;- (SPI) SPI Last Transfer -// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- -AT91C_SPI_MSTR EQU (0x1 << 0) ;- (SPI) Master/Slave Mode -AT91C_SPI_PS EQU (0x1 << 1) ;- (SPI) Peripheral Select -AT91C_SPI_PS_FIXED EQU (0x0 << 1) ;- (SPI) Fixed Peripheral Select -AT91C_SPI_PS_VARIABLE EQU (0x1 << 1) ;- (SPI) Variable Peripheral Select -AT91C_SPI_PCSDEC EQU (0x1 << 2) ;- (SPI) Chip Select Decode -AT91C_SPI_FDIV EQU (0x1 << 3) ;- (SPI) Clock Selection -AT91C_SPI_MODFDIS EQU (0x1 << 4) ;- (SPI) Mode Fault Detection -AT91C_SPI_LLB EQU (0x1 << 7) ;- (SPI) Clock Selection -AT91C_SPI_PCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select -AT91C_SPI_DLYBCS EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects -// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- -AT91C_SPI_RD EQU (0xFFFF << 0) ;- (SPI) Receive Data -AT91C_SPI_RPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- -AT91C_SPI_TD EQU (0xFFFF << 0) ;- (SPI) Transmit Data -AT91C_SPI_TPCS EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status -// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- -AT91C_SPI_RDRF EQU (0x1 << 0) ;- (SPI) Receive Data Register Full -AT91C_SPI_TDRE EQU (0x1 << 1) ;- (SPI) Transmit Data Register Empty -AT91C_SPI_MODF EQU (0x1 << 2) ;- (SPI) Mode Fault Error -AT91C_SPI_OVRES EQU (0x1 << 3) ;- (SPI) Overrun Error Status -AT91C_SPI_ENDRX EQU (0x1 << 4) ;- (SPI) End of Receiver Transfer -AT91C_SPI_ENDTX EQU (0x1 << 5) ;- (SPI) End of Receiver Transfer -AT91C_SPI_RXBUFF EQU (0x1 << 6) ;- (SPI) RXBUFF Interrupt -AT91C_SPI_TXBUFE EQU (0x1 << 7) ;- (SPI) TXBUFE Interrupt -AT91C_SPI_NSSR EQU (0x1 << 8) ;- (SPI) NSSR Interrupt -AT91C_SPI_TXEMPTY EQU (0x1 << 9) ;- (SPI) TXEMPTY Interrupt -AT91C_SPI_SPIENS EQU (0x1 << 16) ;- (SPI) Enable Status -// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- -// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- -// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- -// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- -AT91C_SPI_CPOL EQU (0x1 << 0) ;- (SPI) Clock Polarity -AT91C_SPI_NCPHA EQU (0x1 << 1) ;- (SPI) Clock Phase -AT91C_SPI_CSAAT EQU (0x1 << 3) ;- (SPI) Chip Select Active After Transfer -AT91C_SPI_BITS EQU (0xF << 4) ;- (SPI) Bits Per Transfer -AT91C_SPI_BITS_8 EQU (0x0 << 4) ;- (SPI) 8 Bits Per transfer -AT91C_SPI_BITS_9 EQU (0x1 << 4) ;- (SPI) 9 Bits Per transfer -AT91C_SPI_BITS_10 EQU (0x2 << 4) ;- (SPI) 10 Bits Per transfer -AT91C_SPI_BITS_11 EQU (0x3 << 4) ;- (SPI) 11 Bits Per transfer -AT91C_SPI_BITS_12 EQU (0x4 << 4) ;- (SPI) 12 Bits Per transfer -AT91C_SPI_BITS_13 EQU (0x5 << 4) ;- (SPI) 13 Bits Per transfer -AT91C_SPI_BITS_14 EQU (0x6 << 4) ;- (SPI) 14 Bits Per transfer -AT91C_SPI_BITS_15 EQU (0x7 << 4) ;- (SPI) 15 Bits Per transfer -AT91C_SPI_BITS_16 EQU (0x8 << 4) ;- (SPI) 16 Bits Per transfer -AT91C_SPI_SCBR EQU (0xFF << 8) ;- (SPI) Serial Clock Baud Rate -AT91C_SPI_DLYBS EQU (0xFF << 16) ;- (SPI) Delay Before SPCK -AT91C_SPI_DLYBCT EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Analog to Digital Convertor -// - ***************************************************************************** -// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- -AT91C_ADC_SWRST EQU (0x1 << 0) ;- (ADC) Software Reset -AT91C_ADC_START EQU (0x1 << 1) ;- (ADC) Start Conversion -// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- -AT91C_ADC_TRGEN EQU (0x1 << 0) ;- (ADC) Trigger Enable -AT91C_ADC_TRGEN_DIS EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software -AT91C_ADC_TRGEN_EN EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled. -AT91C_ADC_TRGSEL EQU (0x7 << 1) ;- (ADC) Trigger Selection -AT91C_ADC_TRGSEL_TIOA0 EQU (0x0 << 1) ;- (ADC) Selected TRGSEL = TIAO0 -AT91C_ADC_TRGSEL_TIOA1 EQU (0x1 << 1) ;- (ADC) Selected TRGSEL = TIAO1 -AT91C_ADC_TRGSEL_TIOA2 EQU (0x2 << 1) ;- (ADC) Selected TRGSEL = TIAO2 -AT91C_ADC_TRGSEL_TIOA3 EQU (0x3 << 1) ;- (ADC) Selected TRGSEL = TIAO3 -AT91C_ADC_TRGSEL_TIOA4 EQU (0x4 << 1) ;- (ADC) Selected TRGSEL = TIAO4 -AT91C_ADC_TRGSEL_TIOA5 EQU (0x5 << 1) ;- (ADC) Selected TRGSEL = TIAO5 -AT91C_ADC_TRGSEL_EXT EQU (0x6 << 1) ;- (ADC) Selected TRGSEL = External Trigger -AT91C_ADC_LOWRES EQU (0x1 << 4) ;- (ADC) Resolution. -AT91C_ADC_LOWRES_10_BIT EQU (0x0 << 4) ;- (ADC) 10-bit resolution -AT91C_ADC_LOWRES_8_BIT EQU (0x1 << 4) ;- (ADC) 8-bit resolution -AT91C_ADC_SLEEP EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 << 5) ;- (ADC) Normal Mode -AT91C_ADC_SLEEP_MODE EQU (0x1 << 5) ;- (ADC) Sleep Mode -AT91C_ADC_PRESCAL EQU (0x3F << 8) ;- (ADC) Prescaler rate selection -AT91C_ADC_STARTUP EQU (0x1F << 16) ;- (ADC) Startup Time -AT91C_ADC_SHTIM EQU (0xF << 24) ;- (ADC) Sample & Hold Time -// - -------- ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- -AT91C_ADC_CH0 EQU (0x1 << 0) ;- (ADC) Channel 0 -AT91C_ADC_CH1 EQU (0x1 << 1) ;- (ADC) Channel 1 -AT91C_ADC_CH2 EQU (0x1 << 2) ;- (ADC) Channel 2 -AT91C_ADC_CH3 EQU (0x1 << 3) ;- (ADC) Channel 3 -AT91C_ADC_CH4 EQU (0x1 << 4) ;- (ADC) Channel 4 -AT91C_ADC_CH5 EQU (0x1 << 5) ;- (ADC) Channel 5 -AT91C_ADC_CH6 EQU (0x1 << 6) ;- (ADC) Channel 6 -AT91C_ADC_CH7 EQU (0x1 << 7) ;- (ADC) Channel 7 -// - -------- ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- -// - -------- ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- -// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- -AT91C_ADC_EOC0 EQU (0x1 << 0) ;- (ADC) End of Conversion -AT91C_ADC_EOC1 EQU (0x1 << 1) ;- (ADC) End of Conversion -AT91C_ADC_EOC2 EQU (0x1 << 2) ;- (ADC) End of Conversion -AT91C_ADC_EOC3 EQU (0x1 << 3) ;- (ADC) End of Conversion -AT91C_ADC_EOC4 EQU (0x1 << 4) ;- (ADC) End of Conversion -AT91C_ADC_EOC5 EQU (0x1 << 5) ;- (ADC) End of Conversion -AT91C_ADC_EOC6 EQU (0x1 << 6) ;- (ADC) End of Conversion -AT91C_ADC_EOC7 EQU (0x1 << 7) ;- (ADC) End of Conversion -AT91C_ADC_OVRE0 EQU (0x1 << 8) ;- (ADC) Overrun Error -AT91C_ADC_OVRE1 EQU (0x1 << 9) ;- (ADC) Overrun Error -AT91C_ADC_OVRE2 EQU (0x1 << 10) ;- (ADC) Overrun Error -AT91C_ADC_OVRE3 EQU (0x1 << 11) ;- (ADC) Overrun Error -AT91C_ADC_OVRE4 EQU (0x1 << 12) ;- (ADC) Overrun Error -AT91C_ADC_OVRE5 EQU (0x1 << 13) ;- (ADC) Overrun Error -AT91C_ADC_OVRE6 EQU (0x1 << 14) ;- (ADC) Overrun Error -AT91C_ADC_OVRE7 EQU (0x1 << 15) ;- (ADC) Overrun Error -AT91C_ADC_DRDY EQU (0x1 << 16) ;- (ADC) Data Ready -AT91C_ADC_GOVRE EQU (0x1 << 17) ;- (ADC) General Overrun -AT91C_ADC_ENDRX EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer -AT91C_ADC_RXBUFF EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt -// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- -AT91C_ADC_LDATA EQU (0x3FF << 0) ;- (ADC) Last Data Converted -// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- -// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- -// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- -// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- -AT91C_ADC_DATA EQU (0x3FF << 0) ;- (ADC) Converted Data -// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- -// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- -// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- -// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- -// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- -// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- -// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Synchronous Serial Controller Interface -// - ***************************************************************************** -// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- -AT91C_SSC_RXEN EQU (0x1 << 0) ;- (SSC) Receive Enable -AT91C_SSC_RXDIS EQU (0x1 << 1) ;- (SSC) Receive Disable -AT91C_SSC_TXEN EQU (0x1 << 8) ;- (SSC) Transmit Enable -AT91C_SSC_TXDIS EQU (0x1 << 9) ;- (SSC) Transmit Disable -AT91C_SSC_SWRST EQU (0x1 << 15) ;- (SSC) Software Reset -// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- -AT91C_SSC_CKS EQU (0x3 << 0) ;- (SSC) Receive/Transmit Clock Selection -AT91C_SSC_CKS_DIV EQU (0x0) ;- (SSC) Divided Clock -AT91C_SSC_CKS_TK EQU (0x1) ;- (SSC) TK Clock signal -AT91C_SSC_CKS_RK EQU (0x2) ;- (SSC) RK pin -AT91C_SSC_CKO EQU (0x7 << 2) ;- (SSC) Receive/Transmit Clock Output Mode Selection -AT91C_SSC_CKO_NONE EQU (0x0 << 2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only -AT91C_SSC_CKO_CONTINOUS EQU (0x1 << 2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output -AT91C_SSC_CKO_DATA_TX EQU (0x2 << 2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output -AT91C_SSC_CKI EQU (0x1 << 5) ;- (SSC) Receive/Transmit Clock Inversion -AT91C_SSC_START EQU (0xF << 8) ;- (SSC) Receive/Transmit Start Selection -AT91C_SSC_START_CONTINOUS EQU (0x0 << 8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. -AT91C_SSC_START_TX EQU (0x1 << 8) ;- (SSC) Transmit/Receive start -AT91C_SSC_START_LOW_RF EQU (0x2 << 8) ;- (SSC) Detection of a low level on RF input -AT91C_SSC_START_HIGH_RF EQU (0x3 << 8) ;- (SSC) Detection of a high level on RF input -AT91C_SSC_START_FALL_RF EQU (0x4 << 8) ;- (SSC) Detection of a falling edge on RF input -AT91C_SSC_START_RISE_RF EQU (0x5 << 8) ;- (SSC) Detection of a rising edge on RF input -AT91C_SSC_START_LEVEL_RF EQU (0x6 << 8) ;- (SSC) Detection of any level change on RF input -AT91C_SSC_START_EDGE_RF EQU (0x7 << 8) ;- (SSC) Detection of any edge on RF input -AT91C_SSC_START_0 EQU (0x8 << 8) ;- (SSC) Compare 0 -AT91C_SSC_STTDLY EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay -AT91C_SSC_PERIOD EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection -// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- -AT91C_SSC_DATLEN EQU (0x1F << 0) ;- (SSC) Data Length -AT91C_SSC_LOOP EQU (0x1 << 5) ;- (SSC) Loop Mode -AT91C_SSC_MSBF EQU (0x1 << 7) ;- (SSC) Most Significant Bit First -AT91C_SSC_DATNB EQU (0xF << 8) ;- (SSC) Data Number per Frame -AT91C_SSC_FSLEN EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length -AT91C_SSC_FSOS EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection -AT91C_SSC_FSOS_NONE EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only -AT91C_SSC_FSOS_NEGATIVE EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse -AT91C_SSC_FSOS_POSITIVE EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse -AT91C_SSC_FSOS_LOW EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer -AT91C_SSC_FSOS_HIGH EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer -AT91C_SSC_FSOS_TOGGLE EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer -AT91C_SSC_FSEDGE EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection -// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- -// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- -AT91C_SSC_DATDEF EQU (0x1 << 5) ;- (SSC) Data Default Value -AT91C_SSC_FSDEN EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable -// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- -AT91C_SSC_TXRDY EQU (0x1 << 0) ;- (SSC) Transmit Ready -AT91C_SSC_TXEMPTY EQU (0x1 << 1) ;- (SSC) Transmit Empty -AT91C_SSC_ENDTX EQU (0x1 << 2) ;- (SSC) End Of Transmission -AT91C_SSC_TXBUFE EQU (0x1 << 3) ;- (SSC) Transmit Buffer Empty -AT91C_SSC_RXRDY EQU (0x1 << 4) ;- (SSC) Receive Ready -AT91C_SSC_OVRUN EQU (0x1 << 5) ;- (SSC) Receive Overrun -AT91C_SSC_ENDRX EQU (0x1 << 6) ;- (SSC) End of Reception -AT91C_SSC_RXBUFF EQU (0x1 << 7) ;- (SSC) Receive Buffer Full -AT91C_SSC_TXSYN EQU (0x1 << 10) ;- (SSC) Transmit Sync -AT91C_SSC_RXSYN EQU (0x1 << 11) ;- (SSC) Receive Sync -AT91C_SSC_TXENA EQU (0x1 << 16) ;- (SSC) Transmit Enable -AT91C_SSC_RXENA EQU (0x1 << 17) ;- (SSC) Receive Enable -// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- -// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- -// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Usart -// - ***************************************************************************** -// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- -AT91C_US_STTBRK EQU (0x1 << 9) ;- (USART) Start Break -AT91C_US_STPBRK EQU (0x1 << 10) ;- (USART) Stop Break -AT91C_US_STTTO EQU (0x1 << 11) ;- (USART) Start Time-out -AT91C_US_SENDA EQU (0x1 << 12) ;- (USART) Send Address -AT91C_US_RSTIT EQU (0x1 << 13) ;- (USART) Reset Iterations -AT91C_US_RSTNACK EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge -AT91C_US_RETTO EQU (0x1 << 15) ;- (USART) Rearm Time-out -AT91C_US_DTREN EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable -AT91C_US_DTRDIS EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable -AT91C_US_RTSEN EQU (0x1 << 18) ;- (USART) Request to Send enable -AT91C_US_RTSDIS EQU (0x1 << 19) ;- (USART) Request to Send Disable -// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- -AT91C_US_USMODE EQU (0xF << 0) ;- (USART) Usart mode -AT91C_US_USMODE_NORMAL EQU (0x0) ;- (USART) Normal -AT91C_US_USMODE_RS485 EQU (0x1) ;- (USART) RS485 -AT91C_US_USMODE_HWHSH EQU (0x2) ;- (USART) Hardware Handshaking -AT91C_US_USMODE_MODEM EQU (0x3) ;- (USART) Modem -AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0 -AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1 -AT91C_US_USMODE_IRDA EQU (0x8) ;- (USART) IrDA -AT91C_US_USMODE_SWHSH EQU (0xC) ;- (USART) Software Handshaking -AT91C_US_CLKS EQU (0x3 << 4) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CLKS_CLOCK EQU (0x0 << 4) ;- (USART) Clock -AT91C_US_CLKS_FDIV1 EQU (0x1 << 4) ;- (USART) fdiv1 -AT91C_US_CLKS_SLOW EQU (0x2 << 4) ;- (USART) slow_clock (ARM) -AT91C_US_CLKS_EXT EQU (0x3 << 4) ;- (USART) External (SCK) -AT91C_US_CHRL EQU (0x3 << 6) ;- (USART) Clock Selection (Baud Rate generator Input Clock -AT91C_US_CHRL_5_BITS EQU (0x0 << 6) ;- (USART) Character Length: 5 bits -AT91C_US_CHRL_6_BITS EQU (0x1 << 6) ;- (USART) Character Length: 6 bits -AT91C_US_CHRL_7_BITS EQU (0x2 << 6) ;- (USART) Character Length: 7 bits -AT91C_US_CHRL_8_BITS EQU (0x3 << 6) ;- (USART) Character Length: 8 bits -AT91C_US_SYNC EQU (0x1 << 8) ;- (USART) Synchronous Mode Select -AT91C_US_NBSTOP EQU (0x3 << 12) ;- (USART) Number of Stop bits -AT91C_US_NBSTOP_1_BIT EQU (0x0 << 12) ;- (USART) 1 stop bit -AT91C_US_NBSTOP_15_BIT EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits -AT91C_US_NBSTOP_2_BIT EQU (0x2 << 12) ;- (USART) 2 stop bits -AT91C_US_MSBF EQU (0x1 << 16) ;- (USART) Bit Order -AT91C_US_MODE9 EQU (0x1 << 17) ;- (USART) 9-bit Character length -AT91C_US_CKLO EQU (0x1 << 18) ;- (USART) Clock Output Select -AT91C_US_OVER EQU (0x1 << 19) ;- (USART) Over Sampling Mode -AT91C_US_INACK EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge -AT91C_US_DSNACK EQU (0x1 << 21) ;- (USART) Disable Successive NACK -AT91C_US_MAX_ITER EQU (0x1 << 24) ;- (USART) Number of Repetitions -AT91C_US_FILTER EQU (0x1 << 28) ;- (USART) Receive Line Filter -// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- -AT91C_US_RXBRK EQU (0x1 << 2) ;- (USART) Break Received/End of Break -AT91C_US_TIMEOUT EQU (0x1 << 8) ;- (USART) Receiver Time-out -AT91C_US_ITERATION EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached -AT91C_US_NACK EQU (0x1 << 13) ;- (USART) Non Acknowledge -AT91C_US_RIIC EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag -AT91C_US_DSRIC EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag -AT91C_US_DCDIC EQU (0x1 << 18) ;- (USART) Data Carrier Flag -AT91C_US_CTSIC EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag -// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- -// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- -// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- -AT91C_US_RI EQU (0x1 << 20) ;- (USART) Image of RI Input -AT91C_US_DSR EQU (0x1 << 21) ;- (USART) Image of DSR Input -AT91C_US_DCD EQU (0x1 << 22) ;- (USART) Image of DCD Input -AT91C_US_CTS EQU (0x1 << 23) ;- (USART) Image of CTS Input - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Two-wire Interface -// - ***************************************************************************** -// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- -AT91C_TWI_START EQU (0x1 << 0) ;- (TWI) Send a START Condition -AT91C_TWI_STOP EQU (0x1 << 1) ;- (TWI) Send a STOP Condition -AT91C_TWI_MSEN EQU (0x1 << 2) ;- (TWI) TWI Master Transfer Enabled -AT91C_TWI_MSDIS EQU (0x1 << 3) ;- (TWI) TWI Master Transfer Disabled -AT91C_TWI_SWRST EQU (0x1 << 7) ;- (TWI) Software Reset -// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- -AT91C_TWI_IADRSZ EQU (0x3 << 8) ;- (TWI) Internal Device Address Size -AT91C_TWI_IADRSZ_NO EQU (0x0 << 8) ;- (TWI) No internal device address -AT91C_TWI_IADRSZ_1_BYTE EQU (0x1 << 8) ;- (TWI) One-byte internal device address -AT91C_TWI_IADRSZ_2_BYTE EQU (0x2 << 8) ;- (TWI) Two-byte internal device address -AT91C_TWI_IADRSZ_3_BYTE EQU (0x3 << 8) ;- (TWI) Three-byte internal device address -AT91C_TWI_MREAD EQU (0x1 << 12) ;- (TWI) Master Read Direction -AT91C_TWI_DADR EQU (0x7F << 16) ;- (TWI) Device Address -// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- -AT91C_TWI_CLDIV EQU (0xFF << 0) ;- (TWI) Clock Low Divider -AT91C_TWI_CHDIV EQU (0xFF << 8) ;- (TWI) Clock High Divider -AT91C_TWI_CKDIV EQU (0x7 << 16) ;- (TWI) Clock Divider -// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- -AT91C_TWI_TXCOMP EQU (0x1 << 0) ;- (TWI) Transmission Completed -AT91C_TWI_RXRDY EQU (0x1 << 1) ;- (TWI) Receive holding register ReaDY -AT91C_TWI_TXRDY EQU (0x1 << 2) ;- (TWI) Transmit holding register ReaDY -AT91C_TWI_OVRE EQU (0x1 << 6) ;- (TWI) Overrun Error -AT91C_TWI_UNRE EQU (0x1 << 7) ;- (TWI) Underrun Error -AT91C_TWI_NACK EQU (0x1 << 8) ;- (TWI) Not Acknowledged -// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- -// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- -// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Channel Interface -// - ***************************************************************************** -// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- -AT91C_TC_CLKEN EQU (0x1 << 0) ;- (TC) Counter Clock Enable Command -AT91C_TC_CLKDIS EQU (0x1 << 1) ;- (TC) Counter Clock Disable Command -AT91C_TC_SWTRG EQU (0x1 << 2) ;- (TC) Software Trigger Command -// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- -AT91C_TC_CLKS EQU (0x7 << 0) ;- (TC) Clock Selection -AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK -AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK -AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK -AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK -AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK -AT91C_TC_CLKS_XC0 EQU (0x5) ;- (TC) Clock selected: XC0 -AT91C_TC_CLKS_XC1 EQU (0x6) ;- (TC) Clock selected: XC1 -AT91C_TC_CLKS_XC2 EQU (0x7) ;- (TC) Clock selected: XC2 -AT91C_TC_CLKI EQU (0x1 << 3) ;- (TC) Clock Invert -AT91C_TC_BURST EQU (0x3 << 4) ;- (TC) Burst Signal Selection -AT91C_TC_BURST_NONE EQU (0x0 << 4) ;- (TC) The clock is not gated by an external signal -AT91C_TC_BURST_XC0 EQU (0x1 << 4) ;- (TC) XC0 is ANDed with the selected clock -AT91C_TC_BURST_XC1 EQU (0x2 << 4) ;- (TC) XC1 is ANDed with the selected clock -AT91C_TC_BURST_XC2 EQU (0x3 << 4) ;- (TC) XC2 is ANDed with the selected clock -AT91C_TC_CPCSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RC Compare -AT91C_TC_LDBSTOP EQU (0x1 << 6) ;- (TC) Counter Clock Stopped with RB Loading -AT91C_TC_CPCDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disable with RC Compare -AT91C_TC_LDBDIS EQU (0x1 << 7) ;- (TC) Counter Clock Disabled with RB Loading -AT91C_TC_ETRGEDG EQU (0x3 << 8) ;- (TC) External Trigger Edge Selection -AT91C_TC_ETRGEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_ETRGEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_ETRGEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_ETRGEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVTEDG EQU (0x3 << 8) ;- (TC) External Event Edge Selection -AT91C_TC_EEVTEDG_NONE EQU (0x0 << 8) ;- (TC) Edge: None -AT91C_TC_EEVTEDG_RISING EQU (0x1 << 8) ;- (TC) Edge: rising edge -AT91C_TC_EEVTEDG_FALLING EQU (0x2 << 8) ;- (TC) Edge: falling edge -AT91C_TC_EEVTEDG_BOTH EQU (0x3 << 8) ;- (TC) Edge: each edge -AT91C_TC_EEVT EQU (0x3 << 10) ;- (TC) External Event Selection -AT91C_TC_EEVT_TIOB EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input -AT91C_TC_EEVT_XC0 EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output -AT91C_TC_EEVT_XC1 EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output -AT91C_TC_EEVT_XC2 EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output -AT91C_TC_ABETRG EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection -AT91C_TC_ENETRG EQU (0x1 << 12) ;- (TC) External Event Trigger enable -AT91C_TC_WAVESEL EQU (0x3 << 13) ;- (TC) Waveform Selection -AT91C_TC_WAVESEL_UP EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare -AT91C_TC_WAVESEL_UP_AUTO EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare -AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare -AT91C_TC_CPCTRG EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable -AT91C_TC_WAVE EQU (0x1 << 15) ;- (TC) -AT91C_TC_ACPA EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA -AT91C_TC_ACPA_NONE EQU (0x0 << 16) ;- (TC) Effect: none -AT91C_TC_ACPA_SET EQU (0x1 << 16) ;- (TC) Effect: set -AT91C_TC_ACPA_CLEAR EQU (0x2 << 16) ;- (TC) Effect: clear -AT91C_TC_ACPA_TOGGLE EQU (0x3 << 16) ;- (TC) Effect: toggle -AT91C_TC_LDRA EQU (0x3 << 16) ;- (TC) RA Loading Selection -AT91C_TC_LDRA_NONE EQU (0x0 << 16) ;- (TC) Edge: None -AT91C_TC_LDRA_RISING EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRA_FALLING EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRA_BOTH EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA -AT91C_TC_ACPC EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA -AT91C_TC_ACPC_NONE EQU (0x0 << 18) ;- (TC) Effect: none -AT91C_TC_ACPC_SET EQU (0x1 << 18) ;- (TC) Effect: set -AT91C_TC_ACPC_CLEAR EQU (0x2 << 18) ;- (TC) Effect: clear -AT91C_TC_ACPC_TOGGLE EQU (0x3 << 18) ;- (TC) Effect: toggle -AT91C_TC_LDRB EQU (0x3 << 18) ;- (TC) RB Loading Selection -AT91C_TC_LDRB_NONE EQU (0x0 << 18) ;- (TC) Edge: None -AT91C_TC_LDRB_RISING EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA -AT91C_TC_LDRB_FALLING EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA -AT91C_TC_LDRB_BOTH EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA -AT91C_TC_AEEVT EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA -AT91C_TC_AEEVT_NONE EQU (0x0 << 20) ;- (TC) Effect: none -AT91C_TC_AEEVT_SET EQU (0x1 << 20) ;- (TC) Effect: set -AT91C_TC_AEEVT_CLEAR EQU (0x2 << 20) ;- (TC) Effect: clear -AT91C_TC_AEEVT_TOGGLE EQU (0x3 << 20) ;- (TC) Effect: toggle -AT91C_TC_ASWTRG EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA -AT91C_TC_ASWTRG_NONE EQU (0x0 << 22) ;- (TC) Effect: none -AT91C_TC_ASWTRG_SET EQU (0x1 << 22) ;- (TC) Effect: set -AT91C_TC_ASWTRG_CLEAR EQU (0x2 << 22) ;- (TC) Effect: clear -AT91C_TC_ASWTRG_TOGGLE EQU (0x3 << 22) ;- (TC) Effect: toggle -AT91C_TC_BCPB EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB -AT91C_TC_BCPB_NONE EQU (0x0 << 24) ;- (TC) Effect: none -AT91C_TC_BCPB_SET EQU (0x1 << 24) ;- (TC) Effect: set -AT91C_TC_BCPB_CLEAR EQU (0x2 << 24) ;- (TC) Effect: clear -AT91C_TC_BCPB_TOGGLE EQU (0x3 << 24) ;- (TC) Effect: toggle -AT91C_TC_BCPC EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB -AT91C_TC_BCPC_NONE EQU (0x0 << 26) ;- (TC) Effect: none -AT91C_TC_BCPC_SET EQU (0x1 << 26) ;- (TC) Effect: set -AT91C_TC_BCPC_CLEAR EQU (0x2 << 26) ;- (TC) Effect: clear -AT91C_TC_BCPC_TOGGLE EQU (0x3 << 26) ;- (TC) Effect: toggle -AT91C_TC_BEEVT EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB -AT91C_TC_BEEVT_NONE EQU (0x0 << 28) ;- (TC) Effect: none -AT91C_TC_BEEVT_SET EQU (0x1 << 28) ;- (TC) Effect: set -AT91C_TC_BEEVT_CLEAR EQU (0x2 << 28) ;- (TC) Effect: clear -AT91C_TC_BEEVT_TOGGLE EQU (0x3 << 28) ;- (TC) Effect: toggle -AT91C_TC_BSWTRG EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB -AT91C_TC_BSWTRG_NONE EQU (0x0 << 30) ;- (TC) Effect: none -AT91C_TC_BSWTRG_SET EQU (0x1 << 30) ;- (TC) Effect: set -AT91C_TC_BSWTRG_CLEAR EQU (0x2 << 30) ;- (TC) Effect: clear -AT91C_TC_BSWTRG_TOGGLE EQU (0x3 << 30) ;- (TC) Effect: toggle -// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- -AT91C_TC_COVFS EQU (0x1 << 0) ;- (TC) Counter Overflow -AT91C_TC_LOVRS EQU (0x1 << 1) ;- (TC) Load Overrun -AT91C_TC_CPAS EQU (0x1 << 2) ;- (TC) RA Compare -AT91C_TC_CPBS EQU (0x1 << 3) ;- (TC) RB Compare -AT91C_TC_CPCS EQU (0x1 << 4) ;- (TC) RC Compare -AT91C_TC_LDRAS EQU (0x1 << 5) ;- (TC) RA Loading -AT91C_TC_LDRBS EQU (0x1 << 6) ;- (TC) RB Loading -AT91C_TC_ETRGS EQU (0x1 << 7) ;- (TC) External Trigger -AT91C_TC_CLKSTA EQU (0x1 << 16) ;- (TC) Clock Enabling -AT91C_TC_MTIOA EQU (0x1 << 17) ;- (TC) TIOA Mirror -AT91C_TC_MTIOB EQU (0x1 << 18) ;- (TC) TIOA Mirror -// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- -// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- -// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Timer Counter Interface -// - ***************************************************************************** -// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- -AT91C_TCB_SYNC EQU (0x1 << 0) ;- (TCB) Synchro Command -// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- -AT91C_TCB_TC0XC0S EQU (0x3 << 0) ;- (TCB) External Clock Signal 0 Selection -AT91C_TCB_TC0XC0S_TCLK0 EQU (0x0) ;- (TCB) TCLK0 connected to XC0 -AT91C_TCB_TC0XC0S_NONE EQU (0x1) ;- (TCB) None signal connected to XC0 -AT91C_TCB_TC0XC0S_TIOA1 EQU (0x2) ;- (TCB) TIOA1 connected to XC0 -AT91C_TCB_TC0XC0S_TIOA2 EQU (0x3) ;- (TCB) TIOA2 connected to XC0 -AT91C_TCB_TC1XC1S EQU (0x3 << 2) ;- (TCB) External Clock Signal 1 Selection -AT91C_TCB_TC1XC1S_TCLK1 EQU (0x0 << 2) ;- (TCB) TCLK1 connected to XC1 -AT91C_TCB_TC1XC1S_NONE EQU (0x1 << 2) ;- (TCB) None signal connected to XC1 -AT91C_TCB_TC1XC1S_TIOA0 EQU (0x2 << 2) ;- (TCB) TIOA0 connected to XC1 -AT91C_TCB_TC1XC1S_TIOA2 EQU (0x3 << 2) ;- (TCB) TIOA2 connected to XC1 -AT91C_TCB_TC2XC2S EQU (0x3 << 4) ;- (TCB) External Clock Signal 2 Selection -AT91C_TCB_TC2XC2S_TCLK2 EQU (0x0 << 4) ;- (TCB) TCLK2 connected to XC2 -AT91C_TCB_TC2XC2S_NONE EQU (0x1 << 4) ;- (TCB) None signal connected to XC2 -AT91C_TCB_TC2XC2S_TIOA0 EQU (0x2 << 4) ;- (TCB) TIOA0 connected to XC2 -AT91C_TCB_TC2XC2S_TIOA1 EQU (0x3 << 4) ;- (TCB) TIOA2 connected to XC2 - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR PWMC Channel Interface -// - ***************************************************************************** -// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- -AT91C_PWMC_CPRE EQU (0xF << 0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx -AT91C_PWMC_CPRE_MCK EQU (0x0) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKA EQU (0xB) ;- (PWMC_CH) -AT91C_PWMC_CPRE_MCKB EQU (0xC) ;- (PWMC_CH) -AT91C_PWMC_CALG EQU (0x1 << 8) ;- (PWMC_CH) Channel Alignment -AT91C_PWMC_CPOL EQU (0x1 << 9) ;- (PWMC_CH) Channel Polarity -AT91C_PWMC_CPD EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period -// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- -AT91C_PWMC_CDTY EQU (0x0 << 0) ;- (PWMC_CH) Channel Duty Cycle -// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- -AT91C_PWMC_CPRD EQU (0x0 << 0) ;- (PWMC_CH) Channel Period -// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- -AT91C_PWMC_CCNT EQU (0x0 << 0) ;- (PWMC_CH) Channel Counter -// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- -AT91C_PWMC_CUPD EQU (0x0 << 0) ;- (PWMC_CH) Channel Update - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller Interface -// - ***************************************************************************** -// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- -AT91C_PWMC_DIVA EQU (0xFF << 0) ;- (PWMC) CLKA divide factor. -AT91C_PWMC_PREA EQU (0xF << 8) ;- (PWMC) Divider Input Clock Prescaler A -AT91C_PWMC_PREA_MCK EQU (0x0 << 8) ;- (PWMC) -AT91C_PWMC_DIVB EQU (0xFF << 16) ;- (PWMC) CLKB divide factor. -AT91C_PWMC_PREB EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B -AT91C_PWMC_PREB_MCK EQU (0x0 << 24) ;- (PWMC) -// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- -AT91C_PWMC_CHID0 EQU (0x1 << 0) ;- (PWMC) Channel ID 0 -AT91C_PWMC_CHID1 EQU (0x1 << 1) ;- (PWMC) Channel ID 1 -AT91C_PWMC_CHID2 EQU (0x1 << 2) ;- (PWMC) Channel ID 2 -AT91C_PWMC_CHID3 EQU (0x1 << 3) ;- (PWMC) Channel ID 3 -// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- -// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- -// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- -// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- -// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- -// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- - -// - ***************************************************************************** -// - SOFTWARE API DEFINITION FOR USB Device Interface -// - ***************************************************************************** -// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- -AT91C_UDP_FRM_NUM EQU (0x7FF << 0) ;- (UDP) Frame Number as Defined in the Packet Field Formats -AT91C_UDP_FRM_ERR EQU (0x1 << 16) ;- (UDP) Frame Error -AT91C_UDP_FRM_OK EQU (0x1 << 17) ;- (UDP) Frame OK -// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- -AT91C_UDP_FADDEN EQU (0x1 << 0) ;- (UDP) Function Address Enable -AT91C_UDP_CONFG EQU (0x1 << 1) ;- (UDP) Configured -AT91C_UDP_ESR EQU (0x1 << 2) ;- (UDP) Enable Send Resume -AT91C_UDP_RSMINPR EQU (0x1 << 3) ;- (UDP) A Resume Has Been Sent to the Host -AT91C_UDP_RMWUPE EQU (0x1 << 4) ;- (UDP) Remote Wake Up Enable -// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- -AT91C_UDP_FADD EQU (0xFF << 0) ;- (UDP) Function Address Value -AT91C_UDP_FEN EQU (0x1 << 8) ;- (UDP) Function Enable -// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- -AT91C_UDP_EPINT0 EQU (0x1 << 0) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT1 EQU (0x1 << 1) ;- (UDP) Endpoint 0 Interrupt -AT91C_UDP_EPINT2 EQU (0x1 << 2) ;- (UDP) Endpoint 2 Interrupt -AT91C_UDP_EPINT3 EQU (0x1 << 3) ;- (UDP) Endpoint 3 Interrupt -AT91C_UDP_RXSUSP EQU (0x1 << 8) ;- (UDP) USB Suspend Interrupt -AT91C_UDP_RXRSM EQU (0x1 << 9) ;- (UDP) USB Resume Interrupt -AT91C_UDP_EXTRSM EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt -AT91C_UDP_SOFINT EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt -AT91C_UDP_WAKEUP EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt -// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- -// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- -// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- -AT91C_UDP_ENDBUSRES EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt -// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- -// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- -AT91C_UDP_EP0 EQU (0x1 << 0) ;- (UDP) Reset Endpoint 0 -AT91C_UDP_EP1 EQU (0x1 << 1) ;- (UDP) Reset Endpoint 1 -AT91C_UDP_EP2 EQU (0x1 << 2) ;- (UDP) Reset Endpoint 2 -AT91C_UDP_EP3 EQU (0x1 << 3) ;- (UDP) Reset Endpoint 3 -// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- -AT91C_UDP_TXCOMP EQU (0x1 << 0) ;- (UDP) Generates an IN packet with data previously written in the DPR -AT91C_UDP_RX_DATA_BK0 EQU (0x1 << 1) ;- (UDP) Receive Data Bank 0 -AT91C_UDP_RXSETUP EQU (0x1 << 2) ;- (UDP) Sends STALL to the Host (Control endpoints) -AT91C_UDP_ISOERROR EQU (0x1 << 3) ;- (UDP) Isochronous error (Isochronous endpoints) -AT91C_UDP_TXPKTRDY EQU (0x1 << 4) ;- (UDP) Transmit Packet Ready -AT91C_UDP_FORCESTALL EQU (0x1 << 5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints). -AT91C_UDP_RX_DATA_BK1 EQU (0x1 << 6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes). -AT91C_UDP_DIR EQU (0x1 << 7) ;- (UDP) Transfer Direction -AT91C_UDP_EPTYPE EQU (0x7 << 8) ;- (UDP) Endpoint type -AT91C_UDP_EPTYPE_CTRL EQU (0x0 << 8) ;- (UDP) Control -AT91C_UDP_EPTYPE_ISO_OUT EQU (0x1 << 8) ;- (UDP) Isochronous OUT -AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 << 8) ;- (UDP) Bulk OUT -AT91C_UDP_EPTYPE_INT_OUT EQU (0x3 << 8) ;- (UDP) Interrupt OUT -AT91C_UDP_EPTYPE_ISO_IN EQU (0x5 << 8) ;- (UDP) Isochronous IN -AT91C_UDP_EPTYPE_BULK_IN EQU (0x6 << 8) ;- (UDP) Bulk IN -AT91C_UDP_EPTYPE_INT_IN EQU (0x7 << 8) ;- (UDP) Interrupt IN -AT91C_UDP_DTGLE EQU (0x1 << 11) ;- (UDP) Data Toggle -AT91C_UDP_EPEDS EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable -AT91C_UDP_RXBYTECNT EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO -// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- -AT91C_UDP_TXVDIS EQU (0x1 << 8) ;- (UDP) - -// - ***************************************************************************** -// - REGISTER ADDRESS DEFINITION FOR AT91SAM7S64 -// - ***************************************************************************** -// - ========== Register definition for SYS peripheral ========== -// - ========== Register definition for AIC peripheral ========== -AT91C_AIC_IVR EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register -AT91C_AIC_SMR EQU (0xFFFFF000) ;- (AIC) Source Mode Register -AT91C_AIC_FVR EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register -AT91C_AIC_DCR EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect) -AT91C_AIC_EOICR EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register -AT91C_AIC_SVR EQU (0xFFFFF080) ;- (AIC) Source Vector Register -AT91C_AIC_FFSR EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register -AT91C_AIC_ICCR EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register -AT91C_AIC_ISR EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register -AT91C_AIC_IMR EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register -AT91C_AIC_IPR EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register -AT91C_AIC_FFER EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register -AT91C_AIC_IECR EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register -AT91C_AIC_ISCR EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register -AT91C_AIC_FFDR EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register -AT91C_AIC_CISR EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register -AT91C_AIC_IDCR EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register -AT91C_AIC_SPU EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register -// - ========== Register definition for PDC_DBGU peripheral ========== -AT91C_DBGU_TCR EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register -AT91C_DBGU_RNPR EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register -AT91C_DBGU_TNPR EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register -AT91C_DBGU_TPR EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register -AT91C_DBGU_RPR EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register -AT91C_DBGU_RCR EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register -AT91C_DBGU_RNCR EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register -AT91C_DBGU_PTCR EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register -AT91C_DBGU_PTSR EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register -AT91C_DBGU_TNCR EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register -// - ========== Register definition for DBGU peripheral ========== -AT91C_DBGU_EXID EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register -AT91C_DBGU_BRGR EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register -AT91C_DBGU_IDR EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register -AT91C_DBGU_CSR EQU (0xFFFFF214) ;- (DBGU) Channel Status Register -AT91C_DBGU_CIDR EQU (0xFFFFF240) ;- (DBGU) Chip ID Register -AT91C_DBGU_MR EQU (0xFFFFF204) ;- (DBGU) Mode Register -AT91C_DBGU_IMR EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register -AT91C_DBGU_CR EQU (0xFFFFF200) ;- (DBGU) Control Register -AT91C_DBGU_FNTR EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register -AT91C_DBGU_THR EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register -AT91C_DBGU_RHR EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register -AT91C_DBGU_IER EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register -// - ========== Register definition for PIOA peripheral ========== -AT91C_PIOA_ODR EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr -AT91C_PIOA_SODR EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register -AT91C_PIOA_ISR EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register -AT91C_PIOA_ABSR EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register -AT91C_PIOA_IER EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register -AT91C_PIOA_PPUDR EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register -AT91C_PIOA_IMR EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register -AT91C_PIOA_PER EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register -AT91C_PIOA_IFDR EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register -AT91C_PIOA_OWDR EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register -AT91C_PIOA_MDSR EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register -AT91C_PIOA_IDR EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register -AT91C_PIOA_ODSR EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register -AT91C_PIOA_PPUSR EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register -AT91C_PIOA_OWSR EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register -AT91C_PIOA_BSR EQU (0xFFFFF474) ;- (PIOA) Select B Register -AT91C_PIOA_OWER EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register -AT91C_PIOA_IFER EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register -AT91C_PIOA_PDSR EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register -AT91C_PIOA_PPUER EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register -AT91C_PIOA_OSR EQU (0xFFFFF418) ;- (PIOA) Output Status Register -AT91C_PIOA_ASR EQU (0xFFFFF470) ;- (PIOA) Select A Register -AT91C_PIOA_MDDR EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register -AT91C_PIOA_CODR EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register -AT91C_PIOA_MDER EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register -AT91C_PIOA_PDR EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register -AT91C_PIOA_IFSR EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register -AT91C_PIOA_OER EQU (0xFFFFF410) ;- (PIOA) Output Enable Register -AT91C_PIOA_PSR EQU (0xFFFFF408) ;- (PIOA) PIO Status Register -// - ========== Register definition for CKGR peripheral ========== -AT91C_CKGR_MOR EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register -AT91C_CKGR_PLLR EQU (0xFFFFFC2C) ;- (CKGR) PLL Register -AT91C_CKGR_MCFR EQU (0xFFFFFC24) ;- (CKGR) Main Clock Frequency Register -// - ========== Register definition for PMC peripheral ========== -AT91C_PMC_IDR EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register -AT91C_PMC_MOR EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register -AT91C_PMC_PLLR EQU (0xFFFFFC2C) ;- (PMC) PLL Register -AT91C_PMC_PCER EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register -AT91C_PMC_PCKR EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register -AT91C_PMC_MCKR EQU (0xFFFFFC30) ;- (PMC) Master Clock Register -AT91C_PMC_SCDR EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register -AT91C_PMC_PCDR EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register -AT91C_PMC_SCSR EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register -AT91C_PMC_PCSR EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register -AT91C_PMC_MCFR EQU (0xFFFFFC24) ;- (PMC) Main Clock Frequency Register -AT91C_PMC_SCER EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register -AT91C_PMC_IMR EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register -AT91C_PMC_IER EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register -AT91C_PMC_SR EQU (0xFFFFFC68) ;- (PMC) Status Register -// - ========== Register definition for RSTC peripheral ========== -AT91C_RSTC_RCR EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register -AT91C_RSTC_RMR EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register -AT91C_RSTC_RSR EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register -// - ========== Register definition for RTTC peripheral ========== -AT91C_RTTC_RTSR EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register -AT91C_RTTC_RTMR EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register -AT91C_RTTC_RTVR EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register -AT91C_RTTC_RTAR EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register -// - ========== Register definition for PITC peripheral ========== -AT91C_PITC_PIVR EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register -AT91C_PITC_PISR EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register -AT91C_PITC_PIIR EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register -AT91C_PITC_PIMR EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register -// - ========== Register definition for WDTC peripheral ========== -AT91C_WDTC_WDCR EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register -AT91C_WDTC_WDSR EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register -AT91C_WDTC_WDMR EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register -// - ========== Register definition for VREG peripheral ========== -AT91C_VREG_MR EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register -// - ========== Register definition for MC peripheral ========== -AT91C_MC_ASR EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register -AT91C_MC_RCR EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register -AT91C_MC_FCR EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register -AT91C_MC_AASR EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register -AT91C_MC_FSR EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register -AT91C_MC_FMR EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register -// - ========== Register definition for PDC_SPI peripheral ========== -AT91C_SPI_PTCR EQU (0xFFFE0120) ;- (PDC_SPI) PDC Transfer Control Register -AT91C_SPI_TPR EQU (0xFFFE0108) ;- (PDC_SPI) Transmit Pointer Register -AT91C_SPI_TCR EQU (0xFFFE010C) ;- (PDC_SPI) Transmit Counter Register -AT91C_SPI_RCR EQU (0xFFFE0104) ;- (PDC_SPI) Receive Counter Register -AT91C_SPI_PTSR EQU (0xFFFE0124) ;- (PDC_SPI) PDC Transfer Status Register -AT91C_SPI_RNPR EQU (0xFFFE0110) ;- (PDC_SPI) Receive Next Pointer Register -AT91C_SPI_RPR EQU (0xFFFE0100) ;- (PDC_SPI) Receive Pointer Register -AT91C_SPI_TNCR EQU (0xFFFE011C) ;- (PDC_SPI) Transmit Next Counter Register -AT91C_SPI_RNCR EQU (0xFFFE0114) ;- (PDC_SPI) Receive Next Counter Register -AT91C_SPI_TNPR EQU (0xFFFE0118) ;- (PDC_SPI) Transmit Next Pointer Register -// - ========== Register definition for SPI peripheral ========== -AT91C_SPI_IER EQU (0xFFFE0014) ;- (SPI) Interrupt Enable Register -AT91C_SPI_SR EQU (0xFFFE0010) ;- (SPI) Status Register -AT91C_SPI_IDR EQU (0xFFFE0018) ;- (SPI) Interrupt Disable Register -AT91C_SPI_CR EQU (0xFFFE0000) ;- (SPI) Control Register -AT91C_SPI_MR EQU (0xFFFE0004) ;- (SPI) Mode Register -AT91C_SPI_IMR EQU (0xFFFE001C) ;- (SPI) Interrupt Mask Register -AT91C_SPI_TDR EQU (0xFFFE000C) ;- (SPI) Transmit Data Register -AT91C_SPI_RDR EQU (0xFFFE0008) ;- (SPI) Receive Data Register -AT91C_SPI_CSR EQU (0xFFFE0030) ;- (SPI) Chip Select Register -// - ========== Register definition for PDC_ADC peripheral ========== -AT91C_ADC_PTSR EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register -AT91C_ADC_PTCR EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register -AT91C_ADC_TNPR EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register -AT91C_ADC_TNCR EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register -AT91C_ADC_RNPR EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register -AT91C_ADC_RNCR EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register -AT91C_ADC_RPR EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register -AT91C_ADC_TCR EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register -AT91C_ADC_TPR EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register -AT91C_ADC_RCR EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register -// - ========== Register definition for ADC peripheral ========== -AT91C_ADC_CDR2 EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2 -AT91C_ADC_CDR3 EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3 -AT91C_ADC_CDR0 EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0 -AT91C_ADC_CDR5 EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5 -AT91C_ADC_CHDR EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register -AT91C_ADC_SR EQU (0xFFFD801C) ;- (ADC) ADC Status Register -AT91C_ADC_CDR4 EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4 -AT91C_ADC_CDR1 EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1 -AT91C_ADC_LCDR EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register -AT91C_ADC_IDR EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register -AT91C_ADC_CR EQU (0xFFFD8000) ;- (ADC) ADC Control Register -AT91C_ADC_CDR7 EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7 -AT91C_ADC_CDR6 EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6 -AT91C_ADC_IER EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register -AT91C_ADC_CHER EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register -AT91C_ADC_CHSR EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register -AT91C_ADC_MR EQU (0xFFFD8004) ;- (ADC) ADC Mode Register -AT91C_ADC_IMR EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register -// - ========== Register definition for PDC_SSC peripheral ========== -AT91C_SSC_TNCR EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register -AT91C_SSC_RPR EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register -AT91C_SSC_RNCR EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register -AT91C_SSC_TPR EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register -AT91C_SSC_PTCR EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register -AT91C_SSC_TCR EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register -AT91C_SSC_RCR EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register -AT91C_SSC_RNPR EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register -AT91C_SSC_TNPR EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register -AT91C_SSC_PTSR EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register -// - ========== Register definition for SSC peripheral ========== -AT91C_SSC_RHR EQU (0xFFFD4020) ;- (SSC) Receive Holding Register -AT91C_SSC_RSHR EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register -AT91C_SSC_TFMR EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register -AT91C_SSC_IDR EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register -AT91C_SSC_THR EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register -AT91C_SSC_RCMR EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister -AT91C_SSC_IER EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register -AT91C_SSC_TSHR EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register -AT91C_SSC_SR EQU (0xFFFD4040) ;- (SSC) Status Register -AT91C_SSC_CMR EQU (0xFFFD4004) ;- (SSC) Clock Mode Register -AT91C_SSC_TCMR EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register -AT91C_SSC_CR EQU (0xFFFD4000) ;- (SSC) Control Register -AT91C_SSC_IMR EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register -AT91C_SSC_RFMR EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register -// - ========== Register definition for PDC_US1 peripheral ========== -AT91C_US1_RNCR EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register -AT91C_US1_PTCR EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register -AT91C_US1_TCR EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register -AT91C_US1_PTSR EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register -AT91C_US1_TNPR EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register -AT91C_US1_RCR EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register -AT91C_US1_RNPR EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register -AT91C_US1_RPR EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register -AT91C_US1_TNCR EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register -AT91C_US1_TPR EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register -// - ========== Register definition for US1 peripheral ========== -AT91C_US1_IF EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register -AT91C_US1_NER EQU (0xFFFC4044) ;- (US1) Nb Errors Register -AT91C_US1_RTOR EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register -AT91C_US1_CSR EQU (0xFFFC4014) ;- (US1) Channel Status Register -AT91C_US1_IDR EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register -AT91C_US1_IER EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register -AT91C_US1_THR EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register -AT91C_US1_TTGR EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register -AT91C_US1_RHR EQU (0xFFFC4018) ;- (US1) Receiver Holding Register -AT91C_US1_BRGR EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register -AT91C_US1_IMR EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register -AT91C_US1_FIDI EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register -AT91C_US1_CR EQU (0xFFFC4000) ;- (US1) Control Register -AT91C_US1_MR EQU (0xFFFC4004) ;- (US1) Mode Register -// - ========== Register definition for PDC_US0 peripheral ========== -AT91C_US0_TNPR EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register -AT91C_US0_RNPR EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register -AT91C_US0_TCR EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register -AT91C_US0_PTCR EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register -AT91C_US0_PTSR EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register -AT91C_US0_TNCR EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register -AT91C_US0_TPR EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register -AT91C_US0_RCR EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register -AT91C_US0_RPR EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register -AT91C_US0_RNCR EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register -// - ========== Register definition for US0 peripheral ========== -AT91C_US0_BRGR EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register -AT91C_US0_NER EQU (0xFFFC0044) ;- (US0) Nb Errors Register -AT91C_US0_CR EQU (0xFFFC0000) ;- (US0) Control Register -AT91C_US0_IMR EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register -AT91C_US0_FIDI EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register -AT91C_US0_TTGR EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register -AT91C_US0_MR EQU (0xFFFC0004) ;- (US0) Mode Register -AT91C_US0_RTOR EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register -AT91C_US0_CSR EQU (0xFFFC0014) ;- (US0) Channel Status Register -AT91C_US0_RHR EQU (0xFFFC0018) ;- (US0) Receiver Holding Register -AT91C_US0_IDR EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register -AT91C_US0_THR EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register -AT91C_US0_IF EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register -AT91C_US0_IER EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register -// - ========== Register definition for TWI peripheral ========== -AT91C_TWI_IER EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register -AT91C_TWI_CR EQU (0xFFFB8000) ;- (TWI) Control Register -AT91C_TWI_SR EQU (0xFFFB8020) ;- (TWI) Status Register -AT91C_TWI_IMR EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register -AT91C_TWI_THR EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register -AT91C_TWI_IDR EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register -AT91C_TWI_IADR EQU (0xFFFB800C) ;- (TWI) Internal Address Register -AT91C_TWI_MMR EQU (0xFFFB8004) ;- (TWI) Master Mode Register -AT91C_TWI_CWGR EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register -AT91C_TWI_RHR EQU (0xFFFB8030) ;- (TWI) Receive Holding Register -// - ========== Register definition for TC0 peripheral ========== -AT91C_TC0_SR EQU (0xFFFA0020) ;- (TC0) Status Register -AT91C_TC0_RC EQU (0xFFFA001C) ;- (TC0) Register C -AT91C_TC0_RB EQU (0xFFFA0018) ;- (TC0) Register B -AT91C_TC0_CCR EQU (0xFFFA0000) ;- (TC0) Channel Control Register -AT91C_TC0_CMR EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC0_IER EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register -AT91C_TC0_RA EQU (0xFFFA0014) ;- (TC0) Register A -AT91C_TC0_IDR EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register -AT91C_TC0_CV EQU (0xFFFA0010) ;- (TC0) Counter Value -AT91C_TC0_IMR EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register -// - ========== Register definition for TC1 peripheral ========== -AT91C_TC1_RB EQU (0xFFFA0058) ;- (TC1) Register B -AT91C_TC1_CCR EQU (0xFFFA0040) ;- (TC1) Channel Control Register -AT91C_TC1_IER EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register -AT91C_TC1_IDR EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register -AT91C_TC1_SR EQU (0xFFFA0060) ;- (TC1) Status Register -AT91C_TC1_CMR EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC1_RA EQU (0xFFFA0054) ;- (TC1) Register A -AT91C_TC1_RC EQU (0xFFFA005C) ;- (TC1) Register C -AT91C_TC1_IMR EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register -AT91C_TC1_CV EQU (0xFFFA0050) ;- (TC1) Counter Value -// - ========== Register definition for TC2 peripheral ========== -AT91C_TC2_CMR EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode) -AT91C_TC2_CCR EQU (0xFFFA0080) ;- (TC2) Channel Control Register -AT91C_TC2_CV EQU (0xFFFA0090) ;- (TC2) Counter Value -AT91C_TC2_RA EQU (0xFFFA0094) ;- (TC2) Register A -AT91C_TC2_RB EQU (0xFFFA0098) ;- (TC2) Register B -AT91C_TC2_IDR EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register -AT91C_TC2_IMR EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register -AT91C_TC2_RC EQU (0xFFFA009C) ;- (TC2) Register C -AT91C_TC2_IER EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register -AT91C_TC2_SR EQU (0xFFFA00A0) ;- (TC2) Status Register -// - ========== Register definition for TCB peripheral ========== -AT91C_TCB_BMR EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register -AT91C_TCB_BCR EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register -// - ========== Register definition for PWMC_CH3 peripheral ========== -AT91C_PWMC_CH3_CUPDR EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register -AT91C_PWMC_CH3_Reserved EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved -AT91C_PWMC_CH3_CPRDR EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register -AT91C_PWMC_CH3_CDTYR EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register -AT91C_PWMC_CH3_CCNTR EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register -AT91C_PWMC_CH3_CMR EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register -// - ========== Register definition for PWMC_CH2 peripheral ========== -AT91C_PWMC_CH2_Reserved EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved -AT91C_PWMC_CH2_CMR EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register -AT91C_PWMC_CH2_CCNTR EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register -AT91C_PWMC_CH2_CPRDR EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register -AT91C_PWMC_CH2_CUPDR EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register -AT91C_PWMC_CH2_CDTYR EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register -// - ========== Register definition for PWMC_CH1 peripheral ========== -AT91C_PWMC_CH1_Reserved EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved -AT91C_PWMC_CH1_CUPDR EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register -AT91C_PWMC_CH1_CPRDR EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register -AT91C_PWMC_CH1_CCNTR EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register -AT91C_PWMC_CH1_CDTYR EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register -AT91C_PWMC_CH1_CMR EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register -// - ========== Register definition for PWMC_CH0 peripheral ========== -AT91C_PWMC_CH0_Reserved EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved -AT91C_PWMC_CH0_CPRDR EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register -AT91C_PWMC_CH0_CDTYR EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register -AT91C_PWMC_CH0_CMR EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register -AT91C_PWMC_CH0_CUPDR EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register -AT91C_PWMC_CH0_CCNTR EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register -// - ========== Register definition for PWMC peripheral ========== -AT91C_PWMC_IDR EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register -AT91C_PWMC_DIS EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register -AT91C_PWMC_IER EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register -AT91C_PWMC_VR EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register -AT91C_PWMC_ISR EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register -AT91C_PWMC_SR EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register -AT91C_PWMC_IMR EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register -AT91C_PWMC_MR EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register -AT91C_PWMC_ENA EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register -// - ========== Register definition for UDP peripheral ========== -AT91C_UDP_IMR EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register -AT91C_UDP_FADDR EQU (0xFFFB0008) ;- (UDP) Function Address Register -AT91C_UDP_NUM EQU (0xFFFB0000) ;- (UDP) Frame Number Register -AT91C_UDP_FDR EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register -AT91C_UDP_ISR EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register -AT91C_UDP_CSR EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register -AT91C_UDP_IDR EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register -AT91C_UDP_ICR EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register -AT91C_UDP_RSTEP EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register -AT91C_UDP_TXVC EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register -AT91C_UDP_GLBSTATE EQU (0xFFFB0004) ;- (UDP) Global State Register -AT91C_UDP_IER EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register - -// - ***************************************************************************** -// - PIO DEFINITIONS FOR AT91SAM7S64 -// - ***************************************************************************** -AT91C_PIO_PA0 EQU (1 << 0) ;- Pin Controlled by PA0 -AT91C_PA0_PWM0 EQU (AT91C_PIO_PA0) ;- PWM Channel 0 -AT91C_PA0_TIOA0 EQU (AT91C_PIO_PA0) ;- Timer Counter 0 Multipurpose Timer I/O Pin A -AT91C_PIO_PA1 EQU (1 << 1) ;- Pin Controlled by PA1 -AT91C_PA1_PWM1 EQU (AT91C_PIO_PA1) ;- PWM Channel 1 -AT91C_PA1_TIOB0 EQU (AT91C_PIO_PA1) ;- Timer Counter 0 Multipurpose Timer I/O Pin B -AT91C_PIO_PA10 EQU (1 << 10) ;- Pin Controlled by PA10 -AT91C_PA10_DTXD EQU (AT91C_PIO_PA10) ;- DBGU Debug Transmit Data -AT91C_PA10_NPCS2 EQU (AT91C_PIO_PA10) ;- SPI Peripheral Chip Select 2 -AT91C_PIO_PA11 EQU (1 << 11) ;- Pin Controlled by PA11 -AT91C_PA11_NPCS0 EQU (AT91C_PIO_PA11) ;- SPI Peripheral Chip Select 0 -AT91C_PA11_PWM0 EQU (AT91C_PIO_PA11) ;- PWM Channel 0 -AT91C_PIO_PA12 EQU (1 << 12) ;- Pin Controlled by PA12 -AT91C_PA12_MISO EQU (AT91C_PIO_PA12) ;- SPI Master In Slave -AT91C_PA12_PWM1 EQU (AT91C_PIO_PA12) ;- PWM Channel 1 -AT91C_PIO_PA13 EQU (1 << 13) ;- Pin Controlled by PA13 -AT91C_PA13_MOSI EQU (AT91C_PIO_PA13) ;- SPI Master Out Slave -AT91C_PA13_PWM2 EQU (AT91C_PIO_PA13) ;- PWM Channel 2 -AT91C_PIO_PA14 EQU (1 << 14) ;- Pin Controlled by PA14 -AT91C_PA14_SPCK EQU (AT91C_PIO_PA14) ;- SPI Serial Clock -AT91C_PA14_PWM3 EQU (AT91C_PIO_PA14) ;- PWM Channel 3 -AT91C_PIO_PA15 EQU (1 << 15) ;- Pin Controlled by PA15 -AT91C_PA15_TF EQU (AT91C_PIO_PA15) ;- SSC Transmit Frame Sync -AT91C_PA15_TIOA1 EQU (AT91C_PIO_PA15) ;- Timer Counter 1 Multipurpose Timer I/O Pin A -AT91C_PIO_PA16 EQU (1 << 16) ;- Pin Controlled by PA16 -AT91C_PA16_TK EQU (AT91C_PIO_PA16) ;- SSC Transmit Clock -AT91C_PA16_TIOB1 EQU (AT91C_PIO_PA16) ;- Timer Counter 1 Multipurpose Timer I/O Pin B -AT91C_PIO_PA17 EQU (1 << 17) ;- Pin Controlled by PA17 -AT91C_PA17_TD EQU (AT91C_PIO_PA17) ;- SSC Transmit data -AT91C_PA17_PCK1 EQU (AT91C_PIO_PA17) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA18 EQU (1 << 18) ;- Pin Controlled by PA18 -AT91C_PA18_RD EQU (AT91C_PIO_PA18) ;- SSC Receive Data -AT91C_PA18_PCK2 EQU (AT91C_PIO_PA18) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA19 EQU (1 << 19) ;- Pin Controlled by PA19 -AT91C_PA19_RK EQU (AT91C_PIO_PA19) ;- SSC Receive Clock -AT91C_PA19_FIQ EQU (AT91C_PIO_PA19) ;- AIC Fast Interrupt Input -AT91C_PIO_PA2 EQU (1 << 2) ;- Pin Controlled by PA2 -AT91C_PA2_PWM2 EQU (AT91C_PIO_PA2) ;- PWM Channel 2 -AT91C_PA2_SCK0 EQU (AT91C_PIO_PA2) ;- USART 0 Serial Clock -AT91C_PIO_PA20 EQU (1 << 20) ;- Pin Controlled by PA20 -AT91C_PA20_RF EQU (AT91C_PIO_PA20) ;- SSC Receive Frame Sync -AT91C_PA20_IRQ0 EQU (AT91C_PIO_PA20) ;- External Interrupt 0 -AT91C_PIO_PA21 EQU (1 << 21) ;- Pin Controlled by PA21 -AT91C_PA21_RXD1 EQU (AT91C_PIO_PA21) ;- USART 1 Receive Data -AT91C_PA21_PCK1 EQU (AT91C_PIO_PA21) ;- PMC Programmable Clock Output 1 -AT91C_PIO_PA22 EQU (1 << 22) ;- Pin Controlled by PA22 -AT91C_PA22_TXD1 EQU (AT91C_PIO_PA22) ;- USART 1 Transmit Data -AT91C_PA22_NPCS3 EQU (AT91C_PIO_PA22) ;- SPI Peripheral Chip Select 3 -AT91C_PIO_PA23 EQU (1 << 23) ;- Pin Controlled by PA23 -AT91C_PA23_SCK1 EQU (AT91C_PIO_PA23) ;- USART 1 Serial Clock -AT91C_PA23_PWM0 EQU (AT91C_PIO_PA23) ;- PWM Channel 0 -AT91C_PIO_PA24 EQU (1 << 24) ;- Pin Controlled by PA24 -AT91C_PA24_RTS1 EQU (AT91C_PIO_PA24) ;- USART 1 Ready To Send -AT91C_PA24_PWM1 EQU (AT91C_PIO_PA24) ;- PWM Channel 1 -AT91C_PIO_PA25 EQU (1 << 25) ;- Pin Controlled by PA25 -AT91C_PA25_CTS1 EQU (AT91C_PIO_PA25) ;- USART 1 Clear To Send -AT91C_PA25_PWM2 EQU (AT91C_PIO_PA25) ;- PWM Channel 2 -AT91C_PIO_PA26 EQU (1 << 26) ;- Pin Controlled by PA26 -AT91C_PA26_DCD1 EQU (AT91C_PIO_PA26) ;- USART 1 Data Carrier Detect -AT91C_PA26_TIOA2 EQU (AT91C_PIO_PA26) ;- Timer Counter 2 Multipurpose Timer I/O Pin A -AT91C_PIO_PA27 EQU (1 << 27) ;- Pin Controlled by PA27 -AT91C_PA27_DTR1 EQU (AT91C_PIO_PA27) ;- USART 1 Data Terminal ready -AT91C_PA27_TIOB2 EQU (AT91C_PIO_PA27) ;- Timer Counter 2 Multipurpose Timer I/O Pin B -AT91C_PIO_PA28 EQU (1 << 28) ;- Pin Controlled by PA28 -AT91C_PA28_DSR1 EQU (AT91C_PIO_PA28) ;- USART 1 Data Set ready -AT91C_PA28_TCLK1 EQU (AT91C_PIO_PA28) ;- Timer Counter 1 external clock input -AT91C_PIO_PA29 EQU (1 << 29) ;- Pin Controlled by PA29 -AT91C_PA29_RI1 EQU (AT91C_PIO_PA29) ;- USART 1 Ring Indicator -AT91C_PA29_TCLK2 EQU (AT91C_PIO_PA29) ;- Timer Counter 2 external clock input -AT91C_PIO_PA3 EQU (1 << 3) ;- Pin Controlled by PA3 -AT91C_PA3_TWD EQU (AT91C_PIO_PA3) ;- TWI Two-wire Serial Data -AT91C_PA3_NPCS3 EQU (AT91C_PIO_PA3) ;- SPI Peripheral Chip Select 3 -AT91C_PIO_PA30 EQU (1 << 30) ;- Pin Controlled by PA30 -AT91C_PA30_IRQ1 EQU (AT91C_PIO_PA30) ;- External Interrupt 1 -AT91C_PA30_NPCS2 EQU (AT91C_PIO_PA30) ;- SPI Peripheral Chip Select 2 -AT91C_PIO_PA31 EQU (1 << 31) ;- Pin Controlled by PA31 -AT91C_PA31_NPCS1 EQU (AT91C_PIO_PA31) ;- SPI Peripheral Chip Select 1 -AT91C_PA31_PCK2 EQU (AT91C_PIO_PA31) ;- PMC Programmable Clock Output 2 -AT91C_PIO_PA4 EQU (1 << 4) ;- Pin Controlled by PA4 -AT91C_PA4_TWCK EQU (AT91C_PIO_PA4) ;- TWI Two-wire Serial Clock -AT91C_PA4_TCLK0 EQU (AT91C_PIO_PA4) ;- Timer Counter 0 external clock input -AT91C_PIO_PA5 EQU (1 << 5) ;- Pin Controlled by PA5 -AT91C_PA5_RXD0 EQU (AT91C_PIO_PA5) ;- USART 0 Receive Data -AT91C_PA5_NPCS3 EQU (AT91C_PIO_PA5) ;- SPI Peripheral Chip Select 3 -AT91C_PIO_PA6 EQU (1 << 6) ;- Pin Controlled by PA6 -AT91C_PA6_TXD0 EQU (AT91C_PIO_PA6) ;- USART 0 Transmit Data -AT91C_PA6_PCK0 EQU (AT91C_PIO_PA6) ;- PMC Programmable Clock Output 0 -AT91C_PIO_PA7 EQU (1 << 7) ;- Pin Controlled by PA7 -AT91C_PA7_RTS0 EQU (AT91C_PIO_PA7) ;- USART 0 Ready To Send -AT91C_PA7_PWM3 EQU (AT91C_PIO_PA7) ;- PWM Channel 3 -AT91C_PIO_PA8 EQU (1 << 8) ;- Pin Controlled by PA8 -AT91C_PA8_CTS0 EQU (AT91C_PIO_PA8) ;- USART 0 Clear To Send -AT91C_PA8_ADTRG EQU (AT91C_PIO_PA8) ;- ADC External Trigger -AT91C_PIO_PA9 EQU (1 << 9) ;- Pin Controlled by PA9 -AT91C_PA9_DRXD EQU (AT91C_PIO_PA9) ;- DBGU Debug Receive Data -AT91C_PA9_NPCS1 EQU (AT91C_PIO_PA9) ;- SPI Peripheral Chip Select 1 - -// - ***************************************************************************** -// - PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 -// - ***************************************************************************** -AT91C_ID_FIQ EQU ( 0) ;- Advanced Interrupt Controller (FIQ) -AT91C_ID_SYS EQU ( 1) ;- System Peripheral -AT91C_ID_PIOA EQU ( 2) ;- Parallel IO Controller -AT91C_ID_3_Reserved EQU ( 3) ;- Reserved -AT91C_ID_ADC EQU ( 4) ;- Analog-to-Digital Converter -AT91C_ID_SPI EQU ( 5) ;- Serial Peripheral Interface -AT91C_ID_US0 EQU ( 6) ;- USART 0 -AT91C_ID_US1 EQU ( 7) ;- USART 1 -AT91C_ID_SSC EQU ( 8) ;- Serial Synchronous Controller -AT91C_ID_TWI EQU ( 9) ;- Two-Wire Interface -AT91C_ID_PWMC EQU (10) ;- PWM Controller -AT91C_ID_UDP EQU (11) ;- USB Device Port -AT91C_ID_TC0 EQU (12) ;- Timer Counter 0 -AT91C_ID_TC1 EQU (13) ;- Timer Counter 1 -AT91C_ID_TC2 EQU (14) ;- Timer Counter 2 -AT91C_ID_15_Reserved EQU (15) ;- Reserved -AT91C_ID_16_Reserved EQU (16) ;- Reserved -AT91C_ID_17_Reserved EQU (17) ;- Reserved -AT91C_ID_18_Reserved EQU (18) ;- Reserved -AT91C_ID_19_Reserved EQU (19) ;- Reserved -AT91C_ID_20_Reserved EQU (20) ;- Reserved -AT91C_ID_21_Reserved EQU (21) ;- Reserved -AT91C_ID_22_Reserved EQU (22) ;- Reserved -AT91C_ID_23_Reserved EQU (23) ;- Reserved -AT91C_ID_24_Reserved EQU (24) ;- Reserved -AT91C_ID_25_Reserved EQU (25) ;- Reserved -AT91C_ID_26_Reserved EQU (26) ;- Reserved -AT91C_ID_27_Reserved EQU (27) ;- Reserved -AT91C_ID_28_Reserved EQU (28) ;- Reserved -AT91C_ID_29_Reserved EQU (29) ;- Reserved -AT91C_ID_IRQ0 EQU (30) ;- Advanced Interrupt Controller (IRQ0) -AT91C_ID_IRQ1 EQU (31) ;- Advanced Interrupt Controller (IRQ1) -AT91C_ALL_INT EQU (0xC0007FF7) ;- ALL VALID INTERRUPTS - -// - ***************************************************************************** -// - BASE ADDRESS DEFINITIONS FOR AT91SAM7S64 -// - ***************************************************************************** -AT91C_BASE_SYS EQU (0xFFFFF000) ;- (SYS) Base Address -AT91C_BASE_AIC EQU (0xFFFFF000) ;- (AIC) Base Address -AT91C_BASE_PDC_DBGU EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address -AT91C_BASE_DBGU EQU (0xFFFFF200) ;- (DBGU) Base Address -AT91C_BASE_PIOA EQU (0xFFFFF400) ;- (PIOA) Base Address -AT91C_BASE_CKGR EQU (0xFFFFFC20) ;- (CKGR) Base Address -AT91C_BASE_PMC EQU (0xFFFFFC00) ;- (PMC) Base Address -AT91C_BASE_RSTC EQU (0xFFFFFD00) ;- (RSTC) Base Address -AT91C_BASE_RTTC EQU (0xFFFFFD20) ;- (RTTC) Base Address -AT91C_BASE_PITC EQU (0xFFFFFD30) ;- (PITC) Base Address -AT91C_BASE_WDTC EQU (0xFFFFFD40) ;- (WDTC) Base Address -AT91C_BASE_VREG EQU (0xFFFFFD60) ;- (VREG) Base Address -AT91C_BASE_MC EQU (0xFFFFFF00) ;- (MC) Base Address -AT91C_BASE_PDC_SPI EQU (0xFFFE0100) ;- (PDC_SPI) Base Address -AT91C_BASE_SPI EQU (0xFFFE0000) ;- (SPI) Base Address -AT91C_BASE_PDC_ADC EQU (0xFFFD8100) ;- (PDC_ADC) Base Address -AT91C_BASE_ADC EQU (0xFFFD8000) ;- (ADC) Base Address -AT91C_BASE_PDC_SSC EQU (0xFFFD4100) ;- (PDC_SSC) Base Address -AT91C_BASE_SSC EQU (0xFFFD4000) ;- (SSC) Base Address -AT91C_BASE_PDC_US1 EQU (0xFFFC4100) ;- (PDC_US1) Base Address -AT91C_BASE_US1 EQU (0xFFFC4000) ;- (US1) Base Address -AT91C_BASE_PDC_US0 EQU (0xFFFC0100) ;- (PDC_US0) Base Address -AT91C_BASE_US0 EQU (0xFFFC0000) ;- (US0) Base Address -AT91C_BASE_TWI EQU (0xFFFB8000) ;- (TWI) Base Address -AT91C_BASE_TC0 EQU (0xFFFA0000) ;- (TC0) Base Address -AT91C_BASE_TC1 EQU (0xFFFA0040) ;- (TC1) Base Address -AT91C_BASE_TC2 EQU (0xFFFA0080) ;- (TC2) Base Address -AT91C_BASE_TCB EQU (0xFFFA0000) ;- (TCB) Base Address -AT91C_BASE_PWMC_CH3 EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address -AT91C_BASE_PWMC_CH2 EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address -AT91C_BASE_PWMC_CH1 EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address -AT91C_BASE_PWMC_CH0 EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address -AT91C_BASE_PWMC EQU (0xFFFCC000) ;- (PWMC) Base Address -AT91C_BASE_UDP EQU (0xFFFB0000) ;- (UDP) Base Address - -// - ***************************************************************************** -// - MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64 -// - ***************************************************************************** -// - ISRAM -AT91C_ISRAM EQU (0x00200000) ;- Internal SRAM base address -AT91C_ISRAM_SIZE EQU (0x00004000) ;- Internal SRAM size in byte (16 Kbytes) -// - IFLASH -AT91C_IFLASH EQU (0x00100000) ;- Internal FLASH base address -AT91C_IFLASH_SIZE EQU (0x00010000) ;- Internal FLASH size in byte (64 Kbytes) -AT91C_IFLASH_PAGE_SIZE EQU (128) ;- Internal FLASH Page Size: 128 bytes -AT91C_IFLASH_LOCK_REGION_SIZE EQU (4096) ;- Internal FLASH Lock Region Size: 4 Kbytes -AT91C_IFLASH_NB_OF_PAGES EQU (256) ;- Internal FLASH Number of Pages: 256 bytes -AT91C_IFLASH_NB_OF_LOCK_BITS EQU (8) ;- Internal FLASH Number of Lock Bits: 8 bytes -#endif /* __IAR_SYSTEMS_ASM__ */ - - -#endif /* AT91SAM7S64_H */ diff --git a/openpcd/firmware/include/old/lib_AT91SAM7S256.h b/openpcd/firmware/include/old/lib_AT91SAM7S256.h deleted file mode 100644 index 988af4d..0000000 --- a/openpcd/firmware/include/old/lib_AT91SAM7S256.h +++ /dev/null @@ -1,3719 +0,0 @@ -//* ---------------------------------------------------------------------------- -//* ATMEL Microcontroller Software Support - ROUSSET - -//* ---------------------------------------------------------------------------- -//* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR -//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF -//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE -//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, -//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, -//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF -//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING -//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, -//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -//* ---------------------------------------------------------------------------- -//* File Name : lib_AT91SAM7S256.h -//* Object : AT91SAM7S256 inlined functions -//* Generated : AT91 SW Application Group 01/16/2006 (16:36:07) -//* -//* CVS Reference : /lib_MC_SAM7S.h/1.1/Thu Mar 25 15:19:14 2004// -//* CVS Reference : /lib_pdc.h/1.2/Tue Jul 2 13:29:40 2002// -//* CVS Reference : /lib_dbgu.h/1.1/Thu Aug 25 12:56:22 2005// -//* CVS Reference : /lib_VREG_6085B.h/1.1/Tue Feb 1 16:20:47 2005// -//* CVS Reference : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003// -//* CVS Reference : /lib_spi2.h/1.2/Tue Aug 23 15:37:28 2005// -//* CVS Reference : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004// -//* CVS Reference : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003// -//* CVS Reference : /lib_pitc_6079A.h/1.2/Tue Nov 9 14:43:56 2004// -//* CVS Reference : /lib_pmc_SAM7S.h/1.5/Fri Nov 4 09:37:21 2005// -//* CVS Reference : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003// -//* CVS Reference : /lib_rstc_6098A.h/1.1/Wed Oct 6 10:39:20 2004// -//* CVS Reference : /lib_rttc_6081A.h/1.1/Wed Oct 6 10:39:38 2004// -//* CVS Reference : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003// -//* CVS Reference : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004// -//* CVS Reference : /lib_wdtc_6080A.h/1.1/Wed Oct 6 10:38:30 2004// -//* CVS Reference : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002// -//* CVS Reference : /lib_udp.h/1.5/Tue Aug 30 12:13:47 2005// -//* CVS Reference : /lib_aic_6075b.h/1.2/Thu Jul 7 07:48:22 2005// -//* ---------------------------------------------------------------------------- - -#ifndef lib_AT91SAM7S256_H -#define lib_AT91SAM7S256_H - -/* ***************************************************************************** - SOFTWARE API FOR AIC - ***************************************************************************** */ -#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20] - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ConfigureIt -//* \brief Interrupt Handler Initialization -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_ConfigureIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id, // \arg interrupt number to initialize - unsigned int priority, // \arg priority to give to the interrupt - unsigned int src_type, // \arg activation and sense of activation - void (*newHandler) () ) // \arg address of the interrupt handler -{ - unsigned int oldHandler; - unsigned int mask ; - - oldHandler = pAic->AIC_SVR[irq_id]; - - mask = 0x1 << irq_id ; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Save the interrupt handler routine pointer and the interrupt priority - pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ; - //* Store the Source Mode Register - pAic->AIC_SMR[irq_id] = src_type | priority ; - //* Clear the interrupt on the interrupt controller - pAic->AIC_ICCR = mask ; - - return oldHandler; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_EnableIt -//* \brief Enable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_EnableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - //* Enable the interrupt on the interrupt controller - pAic->AIC_IECR = 0x1 << irq_id ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_DisableIt -//* \brief Disable corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_DisableIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id ) // \arg interrupt number to initialize -{ - unsigned int mask = 0x1 << irq_id; - //* Disable the interrupt on the interrupt controller - pAic->AIC_IDCR = mask ; - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = mask ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_ClearIt -//* \brief Clear corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_ClearIt ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number to initialize -{ - //* Clear the interrupt on the Interrupt Controller ( if one is pending ) - pAic->AIC_ICCR = (0x1 << irq_id); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_AcknowledgeIt -//* \brief Acknowledge corresponding IT number -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_AcknowledgeIt ( - AT91PS_AIC pAic) // \arg pointer to the AIC registers -{ - pAic->AIC_EOICR = pAic->AIC_EOICR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_SetExceptionVector -//* \brief Configure vector handler -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_SetExceptionVector ( - unsigned int *pVector, // \arg pointer to the AIC registers - void (*Handler) () ) // \arg Interrupt Handler -{ - unsigned int oldVector = *pVector; - - if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE) - *pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE; - else - *pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000; - - return oldVector; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Trig -//* \brief Trig an IT -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Trig ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg interrupt number -{ - pAic->AIC_ISCR = (0x1 << irq_id) ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsActive -//* \brief Test if an IT is active -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsActive ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_ISR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_IsPending -//* \brief Test if an IT is pending -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_AIC_IsPending ( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - unsigned int irq_id) // \arg Interrupt Number -{ - return (pAic->AIC_IPR & (0x1 << irq_id)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_Open -//* \brief Set exception vectors and AIC registers to default values -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_Open( - AT91PS_AIC pAic, // \arg pointer to the AIC registers - void (*IrqHandler) (), // \arg Default IRQ vector exception - void (*FiqHandler) (), // \arg Default FIQ vector exception - void (*DefaultHandler) (), // \arg Default Handler set in ISR - void (*SpuriousHandler) (), // \arg Default Spurious Handler - unsigned int protectMode) // \arg Debug Control Register -{ - int i; - - // Disable all interrupts and set IVR to the default handler - for (i = 0; i < 32; ++i) { - AT91F_AIC_DisableIt(pAic, i); - AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler); - } - - // Set the IRQ exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler); - // Set the Fast Interrupt exception vector - AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler); - - pAic->AIC_SPU = (unsigned int) SpuriousHandler; - pAic->AIC_DCR = protectMode; -} -/* ***************************************************************************** - SOFTWARE API FOR PDC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextRx -//* \brief Set the next receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RNPR = (unsigned int) address; - pPDC->PDC_RNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetNextTx -//* \brief Set the next transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetNextTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TNPR = (unsigned int) address; - pPDC->PDC_TNCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetRx -//* \brief Set the receive transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetRx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be received - unsigned int bytes) // \arg number of bytes to be received -{ - pPDC->PDC_RPR = (unsigned int) address; - pPDC->PDC_RCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SetTx -//* \brief Set the transmit transfer descriptor -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_SetTx ( - AT91PS_PDC pPDC, // \arg pointer to a PDC controller - char *address, // \arg address to the next bloc to be transmitted - unsigned int bytes) // \arg number of bytes to be transmitted -{ - pPDC->PDC_TPR = (unsigned int) address; - pPDC->PDC_TCR = bytes; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableTx -//* \brief Enable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_EnableRx -//* \brief Enable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_EnableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableTx -//* \brief Disable transmit -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableTx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_TXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_DisableRx -//* \brief Disable receive -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_DisableRx ( - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - pPDC->PDC_PTCR = AT91C_PDC_RXTDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsTxEmpty -//* \brief Test if the current transfer descriptor has been sent -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextTxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_TNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsRxEmpty -//* \brief Test if the current transfer descriptor has been filled -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_IsNextRxEmpty -//* \brief Test if the next transfer descriptor has been moved to the current td -//*---------------------------------------------------------------------------- -static inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete - AT91PS_PDC pPDC ) // \arg pointer to a PDC controller -{ - return !(pPDC->PDC_RNCR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Open -//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Open ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - - //* Enable the RX and TX PDC transfer requests - AT91F_PDC_EnableRx(pPDC); - AT91F_PDC_EnableTx(pPDC); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_Close -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline void AT91F_PDC_Close ( - AT91PS_PDC pPDC) // \arg pointer to a PDC controller -{ - //* Disable the RX and TX PDC transfer requests - AT91F_PDC_DisableRx(pPDC); - AT91F_PDC_DisableTx(pPDC); - - //* Reset all Counter register Next buffer first - AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0); - AT91F_PDC_SetTx(pPDC, (char *) 0, 0); - AT91F_PDC_SetRx(pPDC, (char *) 0, 0); - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_SendFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_SendFrame( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsTxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextTxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PDC_ReceiveFrame -//* \brief Close PDC: disable TX and RX reset transfer descriptors -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PDC_ReceiveFrame ( - AT91PS_PDC pPDC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - if (AT91F_PDC_IsRxEmpty(pPDC)) { - //* Buffer and next buffer can be initialized - AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer); - AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer); - return 2; - } - else if (AT91F_PDC_IsNextRxEmpty(pPDC)) { - //* Only one buffer can be initialized - AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer); - return 1; - } - else { - //* All buffer are in use... - return 0; - } -} -/* ***************************************************************************** - SOFTWARE API FOR DBGU - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptEnable -//* \brief Enable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptEnable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be enabled -{ - pDbgu->DBGU_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_InterruptDisable -//* \brief Disable DBGU Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_InterruptDisable( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg dbgu interrupt to be disabled -{ - pDbgu->DBGU_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_GetInterruptMaskStatus -//* \brief Return DBGU Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status - AT91PS_DBGU pDbgu) // \arg pointer to a DBGU controller -{ - return pDbgu->DBGU_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_IsInterruptMasked -//* \brief Test if DBGU Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_DBGU_IsInterruptMasked( - AT91PS_DBGU pDbgu, // \arg pointer to a DBGU controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PIO - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPeriph -//* \brief Enable pins to be drived by peripheral -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPeriph( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int periphAEnable, // \arg PERIPH A to enable - unsigned int periphBEnable) // \arg PERIPH B to enable - -{ - pPio->PIO_ASR = periphAEnable; - pPio->PIO_BSR = periphBEnable; - pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOutput -//* \brief Enable PIO in output mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pioEnable) // \arg PIO to be enabled -{ - pPio->PIO_PER = pioEnable; // Set in PIO mode - pPio->PIO_OER = pioEnable; // Configure in Output -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInput -//* \brief Enable PIO in input mode -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputEnable) // \arg PIO to be enabled -{ - // Disable output - pPio->PIO_ODR = inputEnable; - pPio->PIO_PER = inputEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgOpendrain -//* \brief Configure PIO in open drain -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgOpendrain( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int multiDrvEnable) // \arg pio to be configured in open drain -{ - // Configure the multi-drive option - pPio->PIO_MDDR = ~multiDrvEnable; - pPio->PIO_MDER = multiDrvEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgPullup -//* \brief Enable pullup on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgPullup( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int pullupEnable) // \arg enable pullup on PIO -{ - // Connect or not Pullup - pPio->PIO_PPUDR = ~pullupEnable; - pPio->PIO_PPUER = pullupEnable; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgDirectDrive -//* \brief Enable direct drive on PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgDirectDrive( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int directDrive) // \arg PIO to be configured with direct drive - -{ - // Configure the Direct Drive - pPio->PIO_OWDR = ~directDrive; - pPio->PIO_OWER = directDrive; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_CfgInputFilter -//* \brief Enable input filter on input PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_CfgInputFilter( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int inputFilter) // \arg PIO to be configured with input filter - -{ - // Configure the Direct Drive - pPio->PIO_IFDR = ~inputFilter; - pPio->PIO_IFER = inputFilter; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInput -//* \brief Return PIO input value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInput( // \return PIO input - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputSet -//* \brief Test if PIO is input flag is active -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInput(pPio) & flag); -} - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_SetOutput -//* \brief Set to 1 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_SetOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be set -{ - pPio->PIO_SODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ClearOutput -//* \brief Set to 0 output PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ClearOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be cleared -{ - pPio->PIO_CODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_ForceOutput -//* \brief Force output when Direct drive option is enabled -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_ForceOutput( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg output to be forced -{ - pPio->PIO_ODSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Enable -//* \brief Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Enable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_PER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Disable -//* \brief Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_Disable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_PDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetStatus -//* \brief Return PIO Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsSet -//* \brief Test if PIO is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputEnable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be enabled -{ - pPio->PIO_OER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputDisable -//* \brief Output Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output to be disabled -{ - pPio->PIO_ODR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputStatus -//* \brief Return PIO Output Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOuputSet -//* \brief Test if PIO Output is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterEnable -//* \brief Input Filter Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be enabled -{ - pPio->PIO_IFER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InputFilterDisable -//* \brief Input Filter Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InputFilterDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio input filter to be disabled -{ - pPio->PIO_IFDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInputFilterStatus -//* \brief Return PIO Input Filter Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IFSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInputFilterSet -//* \brief Test if PIO Input filter is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInputFilterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInputFilterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputDataStatus -//* \brief Return PIO Output Data Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ODSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptEnable -//* \brief Enable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be enabled -{ - pPio->PIO_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_InterruptDisable -//* \brief Disable PIO Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_InterruptDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio interrupt to be disabled -{ - pPio->PIO_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptMaskStatus -//* \brief Return PIO Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetInterruptStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ISR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptMasked -//* \brief Test if PIO Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptMasked( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsInterruptSet -//* \brief Test if PIO Interrupt is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsInterruptSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetInterruptStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverEnable -//* \brief Multi Driver Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be enabled -{ - pPio->PIO_MDER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_MultiDriverDisable -//* \brief Multi Driver Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_MultiDriverDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio to be disabled -{ - pPio->PIO_MDDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetMultiDriverStatus -//* \brief Return PIO Multi Driver Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_MDSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsMultiDriverSet -//* \brief Test if PIO MultiDriver is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsMultiDriverSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_A_RegisterSelection -//* \brief PIO A Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_A_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio A register selection -{ - pPio->PIO_ASR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_B_RegisterSelection -//* \brief PIO B Register Selection -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_B_RegisterSelection( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio B register selection -{ - pPio->PIO_BSR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_Get_AB_RegisterStatus -//* \brief Return PIO Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_ABSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsAB_RegisterSet -//* \brief Test if PIO AB Register is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsAB_RegisterSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteEnable -//* \brief Output Write Enable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteEnable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be enabled -{ - pPio->PIO_OWER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_OutputWriteDisable -//* \brief Output Write Disable PIO -//*---------------------------------------------------------------------------- -static inline void AT91F_PIO_OutputWriteDisable( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg pio output write to be disabled -{ - pPio->PIO_OWDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetOutputWriteStatus -//* \brief Return PIO Output Write Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_OWSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputWriteSet -//* \brief Test if PIO OutputWrite is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputWriteSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_GetCfgPullup -//* \brief Return PIO Configuration Pullup -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup - AT91PS_PIO pPio) // \arg pointer to a PIO controller -{ - return pPio->PIO_PPUSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsOutputDataStatusSet -//* \brief Test if PIO Output Data Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsOutputDataStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PIO_GetOutputDataStatus(pPio) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIO_IsCfgPullupStatusSet -//* \brief Test if PIO Configuration Pullup Status is Set -//*---------------------------------------------------------------------------- -static inline int AT91F_PIO_IsCfgPullupStatusSet( - AT91PS_PIO pPio, // \arg pointer to a PIO controller - unsigned int flag) // \arg flag to be tested -{ - return (~AT91F_PIO_GetCfgPullup(pPio) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkEnableReg -//* \brief Configure the System Clock Enable Register of the PMC controller -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgSysClkEnableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCER register - pPMC->PMC_SCER = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgSysClkDisableReg -//* \brief Configure the System Clock Disable Register of the PMC controller -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgSysClkDisableReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - //* Write to the SCDR register - pPMC->PMC_SCDR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetSysClkStatusReg -//* \brief Return the System Clock Status Register of the PMC controller -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetSysClkStatusReg ( - AT91PS_PMC pPMC // pointer to a CAN controller - ) -{ - return pPMC->PMC_SCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePeriphClock -//* \brief Enable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals -{ - pPMC->PMC_PCER = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePeriphClock -//* \brief Disable peripheral clock -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePeriphClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int periphIds) // \arg IDs of peripherals -{ - pPMC->PMC_PCDR = periphIds; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetPeriphClock -//* \brief Get peripheral clock status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetPeriphClock ( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_PCSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static inline void AT91F_CKGR_CfgMainOscillatorReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_MOR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainOscillatorReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetMainOscillatorReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MOR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_EnableMainOscillator -//* \brief Enable the main oscillator -//*---------------------------------------------------------------------------- -static inline void AT91F_CKGR_EnableMainOscillator( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_DisableMainOscillator -//* \brief Disable the main oscillator -//*---------------------------------------------------------------------------- -static inline void AT91F_CKGR_DisableMainOscillator ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_CfgMainOscStartUpTime -//* \brief Cfg MOR Register according to the main osc startup time -//*---------------------------------------------------------------------------- -static inline void AT91F_CKGR_CfgMainOscStartUpTime ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int startup_time, // \arg main osc startup time in microsecond (us) - unsigned int slowClock) // \arg slowClock in Hz -{ - pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT; - pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClockFreqReg -//* \brief Cfg the main oscillator -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetMainClockFreqReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_MCFR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_CKGR_GetMainClock -//* \brief Return Main clock in Hz -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetMainClock ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - return ((pCKGR->CKGR_MCFR & AT91C_CKGR_MAINF) * slowClock) >> 4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgMCKReg -//* \brief Cfg Master Clock Register -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgMCKReg ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int mode) -{ - pPMC->PMC_MCKR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetMCKReg -//* \brief Return Master Clock Register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetMCKReg( - AT91PS_PMC pPMC) // \arg pointer to PMC controller -{ - return pPMC->PMC_MCKR; -} - -//*------------------------------------------------------------------------------ -//* \fn AT91F_PMC_GetMasterClock -//* \brief Return master clock in Hz which correponds to processor clock for ARM7 -//*------------------------------------------------------------------------------ -static inline unsigned int AT91F_PMC_GetMasterClock ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int slowClock) // \arg slowClock in Hz -{ - unsigned int reg = pPMC->PMC_MCKR; - unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2)); - unsigned int pllDivider, pllMultiplier; - - switch (reg & AT91C_PMC_CSS) { - case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected - return slowClock / prescaler; - case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler; - case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected - reg = pCKGR->CKGR_PLLR; - pllDivider = (reg & AT91C_CKGR_DIV); - pllMultiplier = ((reg & AT91C_CKGR_MUL) >> 16) + 1; - return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler; - } - return 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnablePCK -//* \brief Enable Programmable Clock x Output -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck, // \arg Programmable Clock x Output - unsigned int mode) -{ - pPMC->PMC_PCKR[pck] = mode; - pPMC->PMC_SCER = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisablePCK -//* \brief Disable Programmable Clock x Output -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisablePCK ( - AT91PS_PMC pPMC, // \arg pointer to PMC controller - unsigned int pck) // \arg Programmable Clock x Output -{ - pPMC->PMC_SCDR = (1 << pck) << 8; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_EnableIt -//* \brief Enable PMC interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_EnableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pPMC->PMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_DisableIt -//* \brief Disable PMC interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_DisableIt ( - AT91PS_PMC pPMC, // pointer to a PMC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pPMC->PMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetStatus -//* \brief Return PMC Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_GetInterruptMaskStatus -//* \brief Return PMC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status - AT91PS_PMC pPMC) // pointer to a PMC controller -{ - return pPMC->PMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsInterruptMasked -//* \brief Test if PMC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_IsInterruptMasked( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_IsStatusSet -//* \brief Test if PMC Status is Set -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PMC_IsStatusSet( - AT91PS_PMC pPMC, // \arg pointer to a PMC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PMC_GetStatus(pPMC) & flag); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_CfgPLLReg -// \brief Cfg the PLL Register -// ---------------------------------------------------------------------------- -static inline void AT91F_CKGR_CfgPLLReg ( - AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller - unsigned int mode) -{ - pCKGR->CKGR_PLLR = mode; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_CKGR_GetPLLReg -// \brief Get the PLL Register -// ---------------------------------------------------------------------------- -static inline unsigned int AT91F_CKGR_GetPLLReg ( - AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller -{ - return pCKGR->CKGR_PLLR; -} - - - -/* ***************************************************************************** - SOFTWARE API FOR RSTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSoftReset -//* \brief Start Software Reset -//*---------------------------------------------------------------------------- -static inline void AT91F_RSTSoftReset( - AT91PS_RSTC pRSTC, - unsigned int reset) -{ - pRSTC->RSTC_RCR = (0xA5000000 | reset); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTSetMode -//* \brief Set Reset Mode -//*---------------------------------------------------------------------------- -static inline void AT91F_RSTSetMode( - AT91PS_RSTC pRSTC, - unsigned int mode) -{ - pRSTC->RSTC_RMR = (0xA5000000 | mode); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetMode -//* \brief Get Reset Mode -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_RSTGetMode( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTGetStatus -//* \brief Get Reset Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_RSTGetStatus( - AT91PS_RSTC pRSTC) -{ - return (pRSTC->RSTC_RSR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTIsSoftRstActive -//* \brief Return !=0 if software reset is still not completed -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_RSTIsSoftRstActive( - AT91PS_RSTC pRSTC) -{ - return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP); -} -/* ***************************************************************************** - SOFTWARE API FOR RTTC - ***************************************************************************** */ -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_SetRTT_TimeBase() -//* \brief Set the RTT prescaler according to the TimeBase in ms -//*-------------------------------------------------------------------------------------- -static inline unsigned int AT91F_RTTSetTimeBase( - AT91PS_RTTC pRTTC, - unsigned int ms) -{ - if (ms > 2000) - return 1; // AT91C_TIME_OUT_OF_RANGE - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF); - return 0; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTSetPrescaler() -//* \brief Set the new prescaler value -//*-------------------------------------------------------------------------------------- -static inline unsigned int AT91F_RTTSetPrescaler( - AT91PS_RTTC pRTTC, - unsigned int rtpres) -{ - pRTTC->RTTC_RTMR &= ~0xFFFF; - pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF); - return (pRTTC->RTTC_RTMR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTRestart() -//* \brief Restart the RTT prescaler -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTRestart( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST; -} - - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmINT() -//* \brief Enable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTSetAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearAlarmINT() -//* \brief Disable RTT Alarm Interrupt -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTClearAlarmINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetRttIncINT() -//* \brief Enable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTSetRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ClearRttIncINT() -//* \brief Disable RTT INC Interrupt -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTClearRttIncINT( - AT91PS_RTTC pRTTC) -{ - pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_SetAlarmValue() -//* \brief Set RTT Alarm Value -//*-------------------------------------------------------------------------------------- -static inline void AT91F_RTTSetAlarmValue( - AT91PS_RTTC pRTTC, unsigned int alarm) -{ - pRTTC->RTTC_RTAR = alarm; -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_GetAlarmValue() -//* \brief Get RTT Alarm Value -//*-------------------------------------------------------------------------------------- -static inline unsigned int AT91F_RTTGetAlarmValue( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTAR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTTGetStatus() -//* \brief Read the RTT status -//*-------------------------------------------------------------------------------------- -static inline unsigned int AT91F_RTTGetStatus( - AT91PS_RTTC pRTTC) -{ - return(pRTTC->RTTC_RTSR); -} - -//*-------------------------------------------------------------------------------------- -//* \fn AT91F_RTT_ReadValue() -//* \brief Read the RTT value -//*-------------------------------------------------------------------------------------- -static inline unsigned int AT91F_RTTReadValue( - AT91PS_RTTC pRTTC) -{ - register volatile unsigned int val1,val2; - do - { - val1 = pRTTC->RTTC_RTVR; - val2 = pRTTC->RTTC_RTVR; - } - while(val1 != val2); - return(val1); -} -/* ***************************************************************************** - SOFTWARE API FOR PITC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITInit -//* \brief System timer init : period in µsecond, system clock freq in MHz -//*---------------------------------------------------------------------------- -static inline void AT91F_PITInit( - AT91PS_PITC pPITC, - unsigned int period, - unsigned int pit_frequency) -{ - pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10 - pPITC->PITC_PIMR |= AT91C_PITC_PITEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITSetPIV -//* \brief Set the PIT Periodic Interval Value -//*---------------------------------------------------------------------------- -static inline void AT91F_PITSetPIV( - AT91PS_PITC pPITC, - unsigned int piv) -{ - pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITEnableInt -//* \brief Enable PIT periodic interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PITEnableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR |= AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITDisableInt -//* \brief Disable PIT periodic interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PITDisableInt( - AT91PS_PITC pPITC) -{ - pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetMode -//* \brief Read PIT mode register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PITGetMode( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIMR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetStatus -//* \brief Read PIT status register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PITGetStatus( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PISR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIIR -//* \brief Read PIT CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PITGetPIIR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIIR); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITGetPIVR -//* \brief Read System timer CPIV and PICNT without ressetting the counters -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PITGetPIVR( - AT91PS_PITC pPITC) -{ - return(pPITC->PITC_PIVR); -} -/* ***************************************************************************** - SOFTWARE API FOR WDTC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSetMode -//* \brief Set Watchdog Mode Register -//*---------------------------------------------------------------------------- -static inline void AT91F_WDTSetMode( - AT91PS_WDTC pWDTC, - unsigned int Mode) -{ - pWDTC->WDTC_WDMR = Mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTRestart -//* \brief Restart Watchdog -//*---------------------------------------------------------------------------- -static inline void AT91F_WDTRestart( - AT91PS_WDTC pWDTC) -{ - pWDTC->WDTC_WDCR = 0xA5000001; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTSGettatus -//* \brief Get Watchdog Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_WDTSGettatus( - AT91PS_WDTC pWDTC) -{ - return(pWDTC->WDTC_WDSR & 0x3); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTGetPeriod -//* \brief Translate ms into Watchdog Compatible value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_WDTGetPeriod(unsigned int ms) -{ - if ((ms < 4) || (ms > 16000)) - return 0; - return((ms << 8) / 1000); -} -/* ***************************************************************************** - SOFTWARE API FOR VREG - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Enable_LowPowerMode -//* \brief Enable VREG Low Power Mode -//*---------------------------------------------------------------------------- -static inline void AT91F_VREG_Enable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR |= AT91C_VREG_PSTDBY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_Disable_LowPowerMode -//* \brief Disable VREG Low Power Mode -//*---------------------------------------------------------------------------- -static inline void AT91F_VREG_Disable_LowPowerMode( - AT91PS_VREG pVREG) -{ - pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY; -}/* ***************************************************************************** - SOFTWARE API FOR MC - ***************************************************************************** */ - -#define AT91C_MC_CORRECT_KEY ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_Remap -//* \brief Make Remap -//*---------------------------------------------------------------------------- -static inline void AT91F_MC_Remap (void) // -{ - AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC; - - pMC->MC_RCR = AT91C_MC_RCB; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_CfgModeReg -//* \brief Configure the EFC Mode Register of the MC controller -//*---------------------------------------------------------------------------- -static inline void AT91F_MC_EFC_CfgModeReg ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int mode) // mode register -{ - // Write to the FMR register - pMC->MC_FMR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetModeReg -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_MC_EFC_GetModeReg( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_ComputeFMCN -//* \brief Return MC EFC Mode Regsiter -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_MC_EFC_ComputeFMCN( - int master_clock) // master clock in Hz -{ - return (master_clock/1000000 +2); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_PerformCmd -//* \brief Perform EFC Command -//*---------------------------------------------------------------------------- -static inline void AT91F_MC_EFC_PerformCmd ( - AT91PS_MC pMC, // pointer to a MC controller - unsigned int transfer_cmd) -{ - pMC->MC_FCR = transfer_cmd; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_GetStatus -//* \brief Return MC EFC Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_MC_EFC_GetStatus( - AT91PS_MC pMC) // pointer to a MC controller -{ - return pMC->MC_FSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptMasked -//* \brief Test if EFC MC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_MC_EFC_IsInterruptMasked( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetModeReg(pMC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_EFC_IsInterruptSet -//* \brief Test if EFC MC Interrupt is Set -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_MC_EFC_IsInterruptSet( - AT91PS_MC pMC, // \arg pointer to a MC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_MC_EFC_GetStatus(pMC) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR SPI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgCs -//* \brief Configure SPI chip select register -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgCs ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int cs, // SPI cs number (0 to 3) - int val) // chip select register -{ - //* Write to the CSR register - *(pSPI->SPI_CSR + cs) = val; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_EnableIt -//* \brief Enable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_EnableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pSPI->SPI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_DisableIt -//* \brief Disable SPI interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_DisableIt ( - AT91PS_SPI pSPI, // pointer to a SPI controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pSPI->SPI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Reset -//* \brief Reset the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Reset ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Enable -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Enable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Disable -//* \brief Disable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Disable ( - AT91PS_SPI pSPI // pointer to a SPI controller - ) -{ - //* Write to the CR register - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgMode -//* \brief Enable the SPI controller -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgMode ( - AT91PS_SPI pSPI, // pointer to a SPI controller - int mode) // mode register -{ - //* Write to the MR register - pSPI->SPI_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPCS -//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPCS ( - AT91PS_SPI pSPI, // pointer to a SPI controller - char PCS_Device) // PCS of the Device -{ - //* Write to the MR register - pSPI->SPI_MR &= 0xFFF0FFFF; - pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS ); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_ReceiveFrame ( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_SendFrame( - AT91PS_SPI pSPI, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSPI->SPI_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_Close -//* \brief Close SPI: disable IT disable transfert, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_Close ( - AT91PS_SPI pSPI) // \arg pointer to a SPI controller -{ - //* Reset all the Chip Select register - pSPI->SPI_CSR[0] = 0 ; - pSPI->SPI_CSR[1] = 0 ; - pSPI->SPI_CSR[2] = 0 ; - pSPI->SPI_CSR[3] = 0 ; - - //* Reset the SPI mode - pSPI->SPI_MR = 0 ; - - //* Disable all interrupts - pSPI->SPI_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pSPI->SPI_CR = AT91C_SPI_SPIDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_PutChar ( - AT91PS_SPI pSPI, - unsigned int character, - unsigned int cs_number ) -{ - unsigned int value_for_cs; - value_for_cs = (~(1 << cs_number)) & 0xF; //Place a zero among a 4 ONEs number - pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_GetChar ( - const AT91PS_SPI pSPI) -{ - return((pSPI->SPI_RDR) & 0xFFFF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_GetInterruptMaskStatus -//* \brief Return SPI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status - AT91PS_SPI pSpi) // \arg pointer to a SPI controller -{ - return pSpi->SPI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_IsInterruptMasked -//* \brief Test if SPI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SPI_IsInterruptMasked( - AT91PS_SPI pSpi, // \arg pointer to a SPI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR ADC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableIt -//* \brief Enable ADC interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_EnableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be enabled -{ - //* Write to the IER register - pADC->ADC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableIt -//* \brief Disable ADC interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_DisableIt ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int flag) // IT to be disabled -{ - //* Write to the IDR register - pADC->ADC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetStatus -//* \brief Return ADC Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetInterruptMaskStatus -//* \brief Return ADC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status - AT91PS_ADC pADC) // pointer to a ADC controller -{ - return pADC->ADC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsInterruptMasked -//* \brief Test if ADC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_IsInterruptMasked( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_IsStatusSet -//* \brief Test if ADC Status is Set -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_IsStatusSet( - AT91PS_ADC pADC, // \arg pointer to a ADC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_ADC_GetStatus(pADC) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgModeReg -//* \brief Configure the Mode Register of the ADC controller -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_CfgModeReg ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mode) // mode register -{ - //* Write to the MR register - pADC->ADC_MR = mode; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetModeReg -//* \brief Return the Mode Register of the ADC controller value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetModeReg ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_MR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgTimings -//* \brief Configure the different necessary timings of the ADC controller -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_CfgTimings ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int mck_clock, // in MHz - unsigned int adc_clock, // in MHz - unsigned int startup_time, // in us - unsigned int sample_and_hold_time) // in ns -{ - unsigned int prescal,startup,shtim; - - prescal = mck_clock/(2*adc_clock) - 1; - startup = adc_clock*startup_time/8 - 1; - shtim = adc_clock*sample_and_hold_time/1000 - 1; - - //* Write to the MR register - pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_EnableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_EnableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHER register - pADC->ADC_CHER = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_DisableChannel -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_DisableChannel ( - AT91PS_ADC pADC, // pointer to a ADC controller - unsigned int channel) // mode register -{ - //* Write to the CHDR register - pADC->ADC_CHDR = channel; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetChannelStatus -//* \brief Return ADC Timer Register Value -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetChannelStatus ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CHSR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_StartConversion -//* \brief Software request for a analog to digital conversion -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_StartConversion ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_START; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_SoftReset -//* \brief Software reset -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_SoftReset ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - pADC->ADC_CR = AT91C_ADC_SWRST; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetLastConvertedData -//* \brief Return the Last Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetLastConvertedData ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_LCDR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH0 -//* \brief Return the Channel 0 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH0 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH1 -//* \brief Return the Channel 1 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH1 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR1; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH2 -//* \brief Return the Channel 2 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH2 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR2; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH3 -//* \brief Return the Channel 3 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH3 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR3; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH4 -//* \brief Return the Channel 4 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH4 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR4; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH5 -//* \brief Return the Channel 5 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH5 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR5; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH6 -//* \brief Return the Channel 6 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH6 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR6; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_GetConvertedDataCH7 -//* \brief Return the Channel 7 Converted Data -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_ADC_GetConvertedDataCH7 ( - AT91PS_ADC pADC // pointer to a ADC controller - ) -{ - return pADC->ADC_CDR7; -} - -/* ***************************************************************************** - SOFTWARE API FOR SSC - ***************************************************************************** */ -//* Define the standard I2S mode configuration - -//* Configuration to set in the SSC Transmit Clock Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - AT91C_SSC_CKS_DIV +\ - AT91C_SSC_CKO_CONTINOUS +\ - AT91C_SSC_CKG_NONE +\ - AT91C_SSC_START_FALL_RF +\ - AT91C_SSC_STTOUT +\ - ((1<<16) & AT91C_SSC_STTDLY) +\ - ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24)) - - -//* Configuration to set in the SSC Transmit Frame Mode Register -//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits -//* nb_slot_by_frame : number of channels -#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\ - (nb_bit_by_slot-1) +\ - AT91C_SSC_MSBF +\ - (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\ - (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\ - AT91C_SSC_FSOS_NEGATIVE) - - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_SetBaudrate ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg SSC baudrate -{ - unsigned int baud_value; - //* Define the baud rate divisor register - if (speed == 0) - baud_value = 0; - else - { - baud_value = (unsigned int) (mainClock * 10)/(2*speed); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - } - - pSSC->SSC_CMR = baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_Configure -//* \brief Configure SSC -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_Configure ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int syst_clock, // \arg System Clock Frequency - unsigned int baud_rate, // \arg Expected Baud Rate Frequency - unsigned int clock_rx, // \arg Receiver Clock Parameters - unsigned int mode_rx, // \arg mode Register to be programmed - unsigned int clock_tx, // \arg Transmitter Clock Parameters - unsigned int mode_tx) // \arg mode Register to be programmed -{ - //* Disable interrupts - pSSC->SSC_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ; - - //* Define the Clock Mode Register - AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate); - - //* Write the Receive Clock Mode Register - pSSC->SSC_RCMR = clock_rx; - - //* Write the Transmit Clock Mode Register - pSSC->SSC_TCMR = clock_tx; - - //* Write the Receive Frame Mode Register - pSSC->SSC_RFMR = mode_rx; - - //* Write the Transmit Frame Mode Register - pSSC->SSC_TFMR = mode_tx; - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR)); - - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableRx -//* \brief Enable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable receiver - pSSC->SSC_CR = AT91C_SSC_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableRx -//* \brief Disable receiving datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableRx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable receiver - pSSC->SSC_CR = AT91C_SSC_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableTx -//* \brief Enable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Enable transmitter - pSSC->SSC_CR = AT91C_SSC_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableTx -//* \brief Disable sending datas -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableTx ( - AT91PS_SSC pSSC) // \arg pointer to a SSC controller -{ - //* Disable transmitter - pSSC->SSC_CR = AT91C_SSC_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_EnableIt -//* \brief Enable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_EnableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pSSC->SSC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_DisableIt -//* \brief Disable SSC IT -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_DisableIt ( - AT91PS_SSC pSSC, // \arg pointer to a SSC controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pSSC->SSC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_ReceiveFrame ( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_SendFrame( - AT91PS_SSC pSSC, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pSSC->SSC_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_GetInterruptMaskStatus -//* \brief Return SSC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status - AT91PS_SSC pSsc) // \arg pointer to a SSC controller -{ - return pSsc->SSC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_IsInterruptMasked -//* \brief Test if SSC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_SSC_IsInterruptMasked( - AT91PS_SSC pSsc, // \arg pointer to a SSC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR USART - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Calculate the baudrate -//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_EXT ) - -//* Standard Synchronous Mode : 8 bits , 1 stop , no parity -#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \ - AT91C_US_USMODE_NORMAL + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//* SCK used Label -#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT) - -//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity -#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \ - AT91C_US_CLKS_CLOCK +\ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_EVEN + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CKLO +\ - AT91C_US_OVER) - -//* Standard IRDA mode -#define AT91C_US_ASYNC_IRDA_MODE ( AT91C_US_USMODE_IRDA + \ - AT91C_US_NBSTOP_1_BIT + \ - AT91C_US_PAR_NONE + \ - AT91C_US_CHRL_8_BITS + \ - AT91C_US_CLKS_CLOCK ) - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Baudrate -//* \brief Caluculate baud_value according to the main clock and the baud rate -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Baudrate ( - const unsigned int main_clock, // \arg peripheral clock - const unsigned int baud_rate) // \arg UART baudrate -{ - unsigned int baud_value = ((main_clock*10)/(baud_rate * 16)); - if ((baud_value % 10) >= 5) - baud_value = (baud_value / 10) + 1; - else - baud_value /= 10; - return baud_value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetBaudrate -//* \brief Set the baudrate according to the CPU clock -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetBaudrate ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int speed) // \arg UART baudrate -{ - //* Define the baud rate divisor register - pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetTimeguard -//* \brief Set USART timeguard -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetTimeguard ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int timeguard) // \arg timeguard value -{ - //* Write the Timeguard Register - pUSART->US_TTGR = timeguard ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableIt -//* \brief Enable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUSART->US_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableIt -//* \brief Disable USART IT -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableIt ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IER register - pUSART->US_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Configure -//* \brief Configure USART -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Configure ( - AT91PS_USART pUSART, // \arg pointer to a USART controller - unsigned int mainClock, // \arg peripheral clock - unsigned int mode , // \arg mode Register to be programmed - unsigned int baudRate , // \arg baudrate to be programmed - unsigned int timeguard ) // \arg timeguard to be programmed -{ - //* Disable interrupts - pUSART->US_IDR = (unsigned int) -1; - - //* Reset receiver and transmitter - pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ; - - //* Define the baud rate divisor register - AT91F_US_SetBaudrate(pUSART, mainClock, baudRate); - - //* Write the Timeguard Register - AT91F_US_SetTimeguard(pUSART, timeguard); - - //* Clear Transmit and Receive Counters - AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Define the USART mode - pUSART->US_MR = mode ; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableRx -//* \brief Enable receiving characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_EnableTx -//* \brief Enable sending characters -//*---------------------------------------------------------------------------- -static inline void AT91F_US_EnableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetRx -//* \brief Reset Receiver and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset receiver - pUSART->US_CR = AT91C_US_RSTRX; - //* Re-Enable receiver - pUSART->US_CR = AT91C_US_RXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ResetTx -//* \brief Reset Transmitter and re-enable it -//*---------------------------------------------------------------------------- -static inline void AT91F_US_ResetTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset transmitter - pUSART->US_CR = AT91C_US_RSTTX; - //* Enable transmitter - pUSART->US_CR = AT91C_US_TXEN; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableRx -//* \brief Disable Receiver -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableRx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable receiver - pUSART->US_CR = AT91C_US_RXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_DisableTx -//* \brief Disable Transmitter -//*---------------------------------------------------------------------------- -static inline void AT91F_US_DisableTx ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Disable transmitter - pUSART->US_CR = AT91C_US_TXDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Close -//* \brief Close USART: disable IT disable receiver and transmitter, close PDC -//*---------------------------------------------------------------------------- -static inline void AT91F_US_Close ( - AT91PS_USART pUSART) // \arg pointer to a USART controller -{ - //* Reset the baud rate divisor register - pUSART->US_BRGR = 0 ; - - //* Reset the USART mode - pUSART->US_MR = 0 ; - - //* Reset the Timeguard Register - pUSART->US_TTGR = 0; - - //* Disable all interrupts - pUSART->US_IDR = 0xFFFFFFFF ; - - //* Abort the Peripheral Data Transfers - AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR)); - - //* Disable receiver and transmitter and stop any activity immediately - pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_TxReady -//* \brief Return 1 if a character can be written in US_THR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_TxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_TXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_RxReady -//* \brief Return 1 if a character can be read in US_RHR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_RxReady ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & AT91C_US_RXRDY); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_Error -//* \brief Return the error flag -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_Error ( - AT91PS_USART pUSART ) // \arg pointer to a USART controller -{ - return (pUSART->US_CSR & - (AT91C_US_OVRE | // Overrun error - AT91C_US_FRAME | // Framing error - AT91C_US_PARE)); // Parity error -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_PutChar -//* \brief Send a character,does not check if ready to send -//*---------------------------------------------------------------------------- -static inline void AT91F_US_PutChar ( - AT91PS_USART pUSART, - int character ) -{ - pUSART->US_THR = (character & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_GetChar -//* \brief Receive a character,does not check if a character is available -//*---------------------------------------------------------------------------- -static inline int AT91F_US_GetChar ( - const AT91PS_USART pUSART) -{ - return((pUSART->US_RHR) & 0x1FF); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SendFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_SendFrame( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_SendFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_ReceiveFrame -//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_US_ReceiveFrame ( - AT91PS_USART pUSART, - char *pBuffer, - unsigned int szBuffer, - char *pNextBuffer, - unsigned int szNextBuffer ) -{ - return AT91F_PDC_ReceiveFrame( - (AT91PS_PDC) &(pUSART->US_RPR), - pBuffer, - szBuffer, - pNextBuffer, - szNextBuffer); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US_SetIrdaFilter -//* \brief Set the value of IrDa filter tregister -//*---------------------------------------------------------------------------- -static inline void AT91F_US_SetIrdaFilter ( - AT91PS_USART pUSART, - unsigned char value -) -{ - pUSART->US_IF = value; -} - -/* ***************************************************************************** - SOFTWARE API FOR TWI - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_EnableIt -//* \brief Enable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_EnableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pTWI->TWI_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_DisableIt -//* \brief Disable TWI IT -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_DisableIt ( - AT91PS_TWI pTWI, // \arg pointer to a TWI controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pTWI->TWI_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_Configure -//* \brief Configure TWI in master mode -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI ) // \arg pointer to a TWI controller -{ - //* Disable interrupts - pTWI->TWI_IDR = (unsigned int) -1; - - //* Reset peripheral - pTWI->TWI_CR = AT91C_TWI_SWRST; - - //* Set Master mode - pTWI->TWI_CR = AT91C_TWI_MSEN; - -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_GetInterruptMaskStatus -//* \brief Return TWI Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status - AT91PS_TWI pTwi) // \arg pointer to a TWI controller -{ - return pTwi->TWI_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_IsInterruptMasked -//* \brief Test if TWI Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TWI_IsInterruptMasked( - AT91PS_TWI pTwi, // \arg pointer to a TWI controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR TC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptEnable -//* \brief Enable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptEnable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be enabled -{ - pTc->TC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_InterruptDisable -//* \brief Disable TC Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_TC_InterruptDisable( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg TC interrupt to be disabled -{ - pTc->TC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_GetInterruptMaskStatus -//* \brief Return TC Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status - AT91PS_TC pTc) // \arg pointer to a TC controller -{ - return pTc->TC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC_IsInterruptMasked -//* \brief Test if TC Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_TC_IsInterruptMasked( - AT91PS_TC pTc, // \arg pointer to a TC controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag); -} - -/* ***************************************************************************** - SOFTWARE API FOR PWMC - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetStatus -//* \brief Return PWM Interrupt Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status - AT91PS_PWMC pPWM) // pointer to a PWM controller -{ - return pPWM->PWMC_SR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptEnable -//* \brief Enable PWM Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_InterruptEnable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be enabled -{ - pPwm->PWMC_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_InterruptDisable -//* \brief Disable PWM Interrupt -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_InterruptDisable( - AT91PS_PWMC pPwm, // \arg pointer to a PWM controller - unsigned int flag) // \arg PWM interrupt to be disabled -{ - pPwm->PWMC_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_GetInterruptMaskStatus -//* \brief Return PWM Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status - AT91PS_PWMC pPwm) // \arg pointer to a PWM controller -{ - return pPwm->PWMC_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsInterruptMasked -//* \brief Test if PWM Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PWMC_IsInterruptMasked( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_IsStatusSet -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_PWMC_IsStatusSet( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_PWMC_GetStatus(pPWM) & flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_CfgChannel -//* \brief Test if PWM Interrupt is Set -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CfgChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int mode, // \arg PWM mode - unsigned int period, // \arg PWM period - unsigned int duty) // \arg PWM duty cycle -{ - pPWM->PWMC_CH[channelId].PWMC_CMR = mode; - pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty; - pPWM->PWMC_CH[channelId].PWMC_CPRDR = period; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StartChannel -//* \brief Enable channel -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_StartChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_ENA = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_StopChannel -//* \brief Disable channel -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_StopChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int flag) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_DIS = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWM_UpdateChannel -//* \brief Update Period or Duty Cycle -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_UpdateChannel( - AT91PS_PWMC pPWM, // \arg pointer to a PWM controller - unsigned int channelId, // \arg PWM channel ID - unsigned int update) // \arg Channels IDs to be enabled -{ - pPWM->PWMC_CH[channelId].PWMC_CUPDR = update; -} - -/* ***************************************************************************** - SOFTWARE API FOR UDP - ***************************************************************************** */ -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableIt -//* \brief Enable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be enabled -{ - //* Write to the IER register - pUDP->UDP_IER = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableIt -//* \brief Disable UDP IT -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableIt ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg IT to be disabled -{ - //* Write to the IDR register - pUDP->UDP_IDR = flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetAddress -//* \brief Set UDP functional address -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetAddress ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char address) // \arg new UDP address -{ - pUDP->UDP_FADDR = (AT91C_UDP_FEN | address); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EnableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_DisableEp -//* \brief Enable Endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableEp ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_SetState -//* \brief Set UDP Device state -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_SetState ( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg new UDP address -{ - pUDP->UDP_GLBSTATE &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG); - pUDP->UDP_GLBSTATE |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetState -//* \brief return UDP Device state -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state - AT91PS_UDP pUDP) // \arg pointer to a UDP controller -{ - return (pUDP->UDP_GLBSTATE & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_ResetEp -//* \brief Reset UDP endpoint -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_ResetEp ( // \return the UDP device state - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned int flag) // \arg Endpoints to be reset -{ - pUDP->UDP_RSTEP = flag; - pUDP->UDP_RSTEP = 0; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStall -//* \brief Endpoint will STALL requests -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpStall( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpWrite -//* \brief Write value in the DPR -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpWrite( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned char value) // \arg value to be written in the DPR -{ - pUDP->UDP_FDR[endpoint] = value; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpRead -//* \brief Return value from the DPR -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpRead( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_FDR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpEndOfWr -//* \brief Notify the UDP that values in DPR are ready to be sent -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpEndOfWr( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpClear -//* \brief Clear flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpClear( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] &= ~(flag); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpSet -//* \brief Set flag in the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_EpSet( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint, // \arg endpoint number - unsigned int flag) // \arg flag to be cleared -{ - pUDP->UDP_CSR[endpoint] |= flag; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_EpStatus -//* \brief Return the endpoint CSR register -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_EpStatus( - AT91PS_UDP pUDP, // \arg pointer to a UDP controller - unsigned char endpoint) // \arg endpoint number -{ - return pUDP->UDP_CSR[endpoint]; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_GetInterruptMaskStatus -//* \brief Return UDP Interrupt Mask Status -//*---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_GetInterruptMaskStatus( - AT91PS_UDP pUdp) // \arg pointer to a UDP controller -{ - return pUdp->UDP_IMR; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_IsInterruptMasked -//* \brief Test if UDP Interrupt is Masked -//*---------------------------------------------------------------------------- -static inline int AT91F_UDP_IsInterruptMasked( - AT91PS_UDP pUdp, // \arg pointer to a UDP controller - unsigned int flag) // \arg flag to be tested -{ - return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag); -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptStatusRegister -// \brief Return the Interrupt Status Register -// ---------------------------------------------------------------------------- -static inline unsigned int AT91F_UDP_InterruptStatusRegister( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - return pUDP->UDP_ISR; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_InterruptClearRegister -// \brief Clear Interrupt Register -// ---------------------------------------------------------------------------- -static inline void AT91F_UDP_InterruptClearRegister ( - AT91PS_UDP pUDP, // \arg pointer to UDP controller - unsigned int flag) // \arg IT to be cleat -{ - pUDP->UDP_ICR = flag; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_EnableTransceiver -// \brief Enable transceiver -// ---------------------------------------------------------------------------- -static inline void AT91F_UDP_EnableTransceiver( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC &= ~AT91C_UDP_TXVDIS; -} - -// ---------------------------------------------------------------------------- -// \fn AT91F_UDP_DisableTransceiver -// \brief Disable transceiver -// ---------------------------------------------------------------------------- -static inline void AT91F_UDP_DisableTransceiver( - AT91PS_UDP pUDP ) // \arg pointer to a UDP controller -{ - pUDP->UDP_TXVC = AT91C_UDP_TXVDIS; -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_MC_CfgPMC -//* \brief Enable Peripheral clock in PMC for MC -//*---------------------------------------------------------------------------- -static inline void AT91F_MC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPMC -//* \brief Enable Peripheral clock in PMC for DBGU -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_DBGU_CfgPIO -//* \brief Configure PIO controllers to drive DBGU signals -//*---------------------------------------------------------------------------- -static inline void AT91F_DBGU_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA10_DTXD ) | - ((unsigned int) AT91C_PA9_DRXD ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH3_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH3 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CH3_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA14_PWM3 ) | - ((unsigned int) AT91C_PA7_PWM3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH2_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CH2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA2_PWM2 ), // Peripheral A - ((unsigned int) AT91C_PA25_PWM2 ) | - ((unsigned int) AT91C_PA13_PWM2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH1_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CH1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA1_PWM1 ), // Peripheral A - ((unsigned int) AT91C_PA24_PWM1 ) | - ((unsigned int) AT91C_PA12_PWM1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CH0_CfgPIO -//* \brief Configure PIO controllers to drive PWMC_CH0 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CH0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA0_PWM0 ), // Peripheral A - ((unsigned int) AT91C_PA23_PWM0 ) | - ((unsigned int) AT91C_PA11_PWM0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_VREG_CfgPMC -//* \brief Enable Peripheral clock in PMC for VREG -//*---------------------------------------------------------------------------- -static inline void AT91F_VREG_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPMC -//* \brief Enable Peripheral clock in PMC for SSC -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SSC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SSC_CfgPIO -//* \brief Configure PIO controllers to drive SSC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SSC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA17_TD ) | - ((unsigned int) AT91C_PA15_TF ) | - ((unsigned int) AT91C_PA19_RK ) | - ((unsigned int) AT91C_PA18_RD ) | - ((unsigned int) AT91C_PA20_RF ) | - ((unsigned int) AT91C_PA16_TK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPMC -//* \brief Enable Peripheral clock in PMC for SPI -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SPI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_SPI_CfgPIO -//* \brief Configure PIO controllers to drive SPI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_SPI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA11_NPCS0 ) | - ((unsigned int) AT91C_PA13_MOSI ) | - ((unsigned int) AT91C_PA31_NPCS1 ) | - ((unsigned int) AT91C_PA12_MISO ) | - ((unsigned int) AT91C_PA14_SPCK ), // Peripheral A - ((unsigned int) AT91C_PA9_NPCS1 ) | - ((unsigned int) AT91C_PA30_NPCS2 ) | - ((unsigned int) AT91C_PA10_NPCS2 ) | - ((unsigned int) AT91C_PA22_NPCS3 ) | - ((unsigned int) AT91C_PA3_NPCS3 ) | - ((unsigned int) AT91C_PA5_NPCS3 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PWMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PWMC -//*---------------------------------------------------------------------------- -static inline void AT91F_PWMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PWMC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC0 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC0_CfgPIO -//* \brief Configure PIO controllers to drive TC0 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TC0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA0_TIOA0 ) | - ((unsigned int) AT91C_PA1_TIOB0 ) | - ((unsigned int) AT91C_PA4_TCLK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC1 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC1_CfgPIO -//* \brief Configure PIO controllers to drive TC1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TC1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA15_TIOA1 ) | - ((unsigned int) AT91C_PA16_TIOB1 ) | - ((unsigned int) AT91C_PA28_TCLK1 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPMC -//* \brief Enable Peripheral clock in PMC for TC2 -//*---------------------------------------------------------------------------- -static inline void AT91F_TC2_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TC2)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TC2_CfgPIO -//* \brief Configure PIO controllers to drive TC2 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TC2_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA26_TIOA2 ) | - ((unsigned int) AT91C_PA27_TIOB2 ) | - ((unsigned int) AT91C_PA29_TCLK2 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PITC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PITC -//*---------------------------------------------------------------------------- -static inline void AT91F_PITC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPMC -//* \brief Enable Peripheral clock in PMC for PMC -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PMC_CfgPIO -//* \brief Configure PIO controllers to drive PMC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_PMC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA17_PCK1 ) | - ((unsigned int) AT91C_PA21_PCK1 ) | - ((unsigned int) AT91C_PA31_PCK2 ) | - ((unsigned int) AT91C_PA18_PCK2 ) | - ((unsigned int) AT91C_PA6_PCK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPMC -//* \brief Enable Peripheral clock in PMC for ADC -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_ADC)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_ADC_CfgPIO -//* \brief Configure PIO controllers to drive ADC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_ADC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - 0, // Peripheral A - ((unsigned int) AT91C_PA8_ADTRG )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RSTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RSTC -//*---------------------------------------------------------------------------- -static inline void AT91F_RSTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_RTTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for RTTC -//*---------------------------------------------------------------------------- -static inline void AT91F_RTTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_PIOA_CfgPMC -//* \brief Enable Peripheral clock in PMC for PIOA -//*---------------------------------------------------------------------------- -static inline void AT91F_PIOA_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_PIOA)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPMC -//* \brief Enable Peripheral clock in PMC for TWI -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_TWI)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_TWI_CfgPIO -//* \brief Configure PIO controllers to drive TWI signals -//*---------------------------------------------------------------------------- -static inline void AT91F_TWI_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA3_TWD ) | - ((unsigned int) AT91C_PA4_TWCK ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_WDTC_CfgPMC -//* \brief Enable Peripheral clock in PMC for WDTC -//*---------------------------------------------------------------------------- -static inline void AT91F_WDTC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_SYS)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPMC -//* \brief Enable Peripheral clock in PMC for US1 -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US1_CfgPIO -//* \brief Configure PIO controllers to drive US1 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US1_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA21_RXD1 ) | - ((unsigned int) AT91C_PA27_DTR1 ) | - ((unsigned int) AT91C_PA26_DCD1 ) | - ((unsigned int) AT91C_PA22_TXD1 ) | - ((unsigned int) AT91C_PA24_RTS1 ) | - ((unsigned int) AT91C_PA23_SCK1 ) | - ((unsigned int) AT91C_PA28_DSR1 ) | - ((unsigned int) AT91C_PA29_RI1 ) | - ((unsigned int) AT91C_PA25_CTS1 ), // Peripheral A - 0); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPMC -//* \brief Enable Peripheral clock in PMC for US0 -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_US0)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_US0_CfgPIO -//* \brief Configure PIO controllers to drive US0 signals -//*---------------------------------------------------------------------------- -static inline void AT91F_US0_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA5_RXD0 ) | - ((unsigned int) AT91C_PA6_TXD0 ) | - ((unsigned int) AT91C_PA7_RTS0 ) | - ((unsigned int) AT91C_PA8_CTS0 ), // Peripheral A - ((unsigned int) AT91C_PA2_SCK0 )); // Peripheral B -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_UDP_CfgPMC -//* \brief Enable Peripheral clock in PMC for UDP -//*---------------------------------------------------------------------------- -static inline void AT91F_UDP_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_UDP)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPMC -//* \brief Enable Peripheral clock in PMC for AIC -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_CfgPMC (void) -{ - AT91F_PMC_EnablePeriphClock( - AT91C_BASE_PMC, // PIO controller base address - ((unsigned int) 1 << AT91C_ID_IRQ0) | - ((unsigned int) 1 << AT91C_ID_FIQ) | - ((unsigned int) 1 << AT91C_ID_IRQ1)); -} - -//*---------------------------------------------------------------------------- -//* \fn AT91F_AIC_CfgPIO -//* \brief Configure PIO controllers to drive AIC signals -//*---------------------------------------------------------------------------- -static inline void AT91F_AIC_CfgPIO (void) -{ - // Configure PIO controllers to periph mode - AT91F_PIO_CfgPeriph( - AT91C_BASE_PIOA, // PIO controller base address - ((unsigned int) AT91C_PA30_IRQ1 ), // Peripheral A - ((unsigned int) AT91C_PA20_IRQ0 ) | - ((unsigned int) AT91C_PA19_FIQ )); // Peripheral B -} - -#endif // lib_AT91SAM7S256_H |