diff options
| author | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-08-08 20:10:20 +0000 |
|---|---|---|
| committer | (no author) <(no author)@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2006-08-08 20:10:20 +0000 |
| commit | bc7d72bf05d8e84c207f9be30abab23b3023408f (patch) | |
| tree | 465949459f39c2a6053d306c3b5010845c78e773 /openpcd/firmware/src/tc.c | |
| parent | 812c69de2e0b968bd0ff431adf40b09086da39aa (diff) | |
major rework of carrier division signals:
1) RFID_RESET moved PA29 -> PA5
2) MFIN (PWM0 output) moved PA0 -> PA23
3) PA0 recondfigured as TIOA0 output (CDIV_HELP)
4) PA29 reconfigured as TCLK2 input
5) TIOA0 (PA0) interconnected with TCLK2 (PA29)
6) PA1 reconfigured as TIOB0 output (CARRIER_DIV)
7) TIOB0 (PA1) interconnected with SSC_RK (PA19)
git-svn-id: https://svn.openpcd.org:2342/trunk@87 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpcd/firmware/src/tc.c')
| -rw-r--r-- | openpcd/firmware/src/tc.c | 25 |
1 files changed, 17 insertions, 8 deletions
diff --git a/openpcd/firmware/src/tc.c b/openpcd/firmware/src/tc.c index 4ee28ba..5318644 100644 --- a/openpcd/firmware/src/tc.c +++ b/openpcd/firmware/src/tc.c @@ -31,9 +31,12 @@ void tc_cdiv_phase_add(int16_t inc) void tc_cdiv_init(void) { - /* Cfg PIO28 as Periph B */ - AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, OPENPCD_PIO_CARRIER| - OPENPCD_PIO_CARRIER_DIV); + /* Cfg PA28(TCLK1), PA0(TIOA0), PA1(TIOB0), PA20(TCLK2) as Periph B */ + AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, 0, + OPENPCD_PIO_CARRIER_IN | + OPENPCD_PIO_CARRIER_DIV_OUT | + OPENPCD_PIO_CDIV_HELP_OUT | + OPENPCD_PIO_CDIV_HELP_IN); AT91F_PMC_EnablePeriphClock(AT91C_BASE_PMC, ((unsigned int) 1 << AT91C_ID_TC0)); @@ -41,13 +44,19 @@ void tc_cdiv_init(void) /* Enable Clock for TC0 */ tcb->TCB_TC0.TC_CCR = AT91C_TC_CLKEN; - /* Connect TCLK1 to XC1 */ - tcb->TCB_BMR &= ~AT91C_TCB_TC1XC1S; - tcb->TCB_BMR |= AT91C_TCB_TC1XC1S_TCLK1; + /* Connect TCLK1 to XC1, TCLK2 to XC2 */ + tcb->TCB_BMR &= ~(AT91C_TCB_TC1XC1S | AT91C_TCB_TC2XC2S); + tcb->TCB_BMR |= (AT91C_TCB_TC1XC1S_TCLK1 | AT91C_TCB_TC2XC2S_TCLK2); + /* Clock XC1, Wave mode, Reset on RC comp + * TIOA0 on RA comp = set, * TIOA0 on RC comp = clear, + * TIOB0 on EEVT = set, TIOB0 on RB comp = clear, + * EEVT = XC2 (TIOA0) */ tcb->TCB_TC0.TC_CMR = AT91C_TC_CLKS_XC1 | AT91C_TC_WAVE | - AT91C_TC_WAVESEL_UP_AUTO | AT91C_TC_ACPC_SET | - AT91C_TC_BCPC_CLEAR | AT91C_TC_EEVT_XC0; + AT91C_TC_WAVESEL_UP_AUTO | + AT91C_TC_ACPA_SET | AT91C_TC_ACPC_CLEAR | + AT91C_TC_BEEVT_SET | AT91C_TC_BCPB_CLEAR | + AT91C_TC_EEVT_XC2 | AT91C_TC_ETRGEDG_RISING; tc_cdiv_set_divider(128); |