diff options
| author | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-12 01:50:14 +0000 |
|---|---|---|
| committer | henryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1> | 2007-12-12 01:50:14 +0000 |
| commit | 202b56a42c5e6a171ee43b469be48525d0e8e350 (patch) | |
| tree | 84260eadbedd8575f158b95a43c3a481c35362ec /openpicc/os/boot | |
| parent | 3d0e1db9d118f85441a9d559ba2fa7baa7195eee (diff) | |
Add new miller decoder (not working yet)
Vastly improve timing through CPU cycle counting. Jitter is now like 40ns (the SSC_DATA edge detection fuzziness) in 2 main clusters 4 CPU cycles (83ns) apart, plus an occasional glitch adding 4 CPU cycles in either direction
git-svn-id: https://svn.openpcd.org:2342/trunk@385 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc/os/boot')
| -rw-r--r-- | openpicc/os/boot/boot.s | 31 |
1 files changed, 30 insertions, 1 deletions
diff --git a/openpicc/os/boot/boot.s b/openpicc/os/boot/boot.s index 0000479..c065a6d 100644 --- a/openpicc/os/boot/boot.s +++ b/openpicc/os/boot/boot.s @@ -250,10 +250,39 @@ my_fiq_handler: ldr r11, =ssc_tx_fiq_fdt_cdiv ldr r11, [r11] /* r11 == ssc_tx_fiq_fdt_cdiv */ +/* Problem: LDR from the timer still takes too long and causes us to miss the exact time. + * Strategy: Spin on TC2 till we are very near the actual time. Then load the timer value, calculate + * the difference to the target, then do a countdown spin without reading the timer. + * + * At 47.923200 MHz 7 processor cycles are 2 carrier cycles of the 13.56MHz carrier + */ + .equ SUB_TIME, 20 /* subtract 20 carrier cycles == 70 processor cycles */ + .equ ADD_TIME, (70-20) /* Add x processor cycles */ + + mov r8, #SUB_TIME + sub r11, r11, r8 + .wait_for_fdt_cdiv: ldr r8, [r12, #TC2_CV] cmp r8, r11 - bmi .wait_for_fdt_cdiv /* spin while TC2.CV is less fdt_cdiv */ + bmi .wait_for_fdt_cdiv /* spin while TC2.CV is less fdt_cdiv-SUB_TIM */ + + ldr r8, [r12, #TC2_CV] + sub r11, r11, r8 /* r11 == fdt_cdiv-SUB_TIME - TC2.CV */ + + mov r8, #0x07 + mul r11, r8, r11 /* r11 = r11 * 7 */ + mov r11, r11, ASR #1 /* r11 = r11 / 2 */ + + mov r8, #ADD_TIME + add r11, r11, r8 /* r11 = r11 + ADD_TIME */ + + mov r11, r11, ASR #2 /* r11 = r11 / 4 (4 is the number of cycles per loop run below) */ + + mov r8, #1 +.wait_for_my_time: + subs r11, r11, r8 + bge .wait_for_my_time str r9, [r12, #TC_CCR] /* SWTRG on TC0 */ |