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* Add complicated mechanism that should have brought clock cycle accurate measu...henryk2007-12-121-3/+37
* Add new miller decoder (not working yet)henryk2007-12-121-1/+30
* Several modifications to enable spinning until the correct phase is reached i...henryk2007-12-112-12/+35
* Prevent late frames by spinning in SSC CP0 IRQ till end of short frame receptionhenryk2007-12-091-1/+9
* Add (#ifdef'ed out) code to measure critical section timing with an LEDhenryk2007-12-041-1/+6
* Fix FIQ code for SSC TF emulationhenryk2007-12-031-8/+7
* Fix SSC TX registers (especially the clock source selection), peripheral conf...henryk2007-11-291-0/+24
* Switch to hardcoded fiq handler implementation directly in the vector table (...henryk2007-11-291-79/+14
* Prepare transmission codehenryk2007-11-261-1/+1
* Add a work around to have each pio data change fiq followed by a regular IRQ ...henryk2007-11-231-10/+15
* Commit status quo (pending cleanup of the debug and experimental code that I ...henryk2007-11-234-21/+70
* Add tragically failed (and commented out) attempt to remap ram to addr 0henryk2007-11-211-0/+16
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-212-2/+97
* Checking in status quo: Can currently receive and print frames in ssc continu...henryk2007-11-211-1/+2
* Fix device name in USB descriptorhenryk2007-11-111-6/+6
* Revert 313 and 315 again, I'm too stupid to get DFU working, focus on the app...henryk2007-11-113-706/+39
* Start working at dfu by copying from main openpcd repository (with modificati...henryk2007-11-073-39/+706
* Initial import of FreeRTOS code for OpenPICChenryk2007-11-0638-0/+16058
personal git repositories of Harald Welte. Your mileage may vary