diff options
| author | Harald Welte <laforge@gnumonks.org> | 2011-12-01 19:53:03 +0100 |
|---|---|---|
| committer | Harald Welte <laforge@gnumonks.org> | 2011-12-01 19:53:03 +0100 |
| commit | eebb6cc1217260d7b29478a83008ee070d57738e (patch) | |
| tree | 4500a69e35d081161875e2320d351911edcac24b | |
initial checkin of usb-device-audio-speaker-project for sam3u-ek
| -rw-r--r-- | external_libs/cmsis/core_cm3.c | 805 | ||||
| -rw-r--r-- | external_libs/cmsis/core_cm3.h | 1265 | ||||
| -rw-r--r-- | usb-device-audio-speaker-project/Makefile | 241 | ||||
| -rw-r--r-- | usb-device-audio-speaker-project/bin/.empty_dir | 0 | ||||
| -rw-r--r-- | usb-device-audio-speaker-project/main.c | 835 | ||||
| -rw-r--r-- | usb-device-audio-speaker-project/obj/.empty_dir | 0 |
6 files changed, 3146 insertions, 0 deletions
diff --git a/external_libs/cmsis/core_cm3.c b/external_libs/cmsis/core_cm3.c new file mode 100644 index 0000000..a64aa5c --- /dev/null +++ b/external_libs/cmsis/core_cm3.c @@ -0,0 +1,805 @@ +/******************************************************************************
+ * @file: core_cm3.c
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Source File
+ * @version: V1.10
+ * @date: 24. Feb. 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+
+#include <stdint.h>
+
+
+/* define compiler specific symbols */
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for armcc */
+ #define __INLINE __inline /*!< inline keyword for armcc */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for iarcc */
+ #define __INLINE inline /*!< inline keyword for iarcc. Only avaiable in High optimization mode! */
+ #define __nop __no_operation /*!< no operation intrinsic in iarcc */
+
+#elif defined ( __GNUC__ )
+ #define __ASM asm /*!< asm keyword for gcc */
+ #define __INLINE inline /*!< inline keyword for gcc */
+#endif
+
+
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+__ASM uint32_t __get_PSP(void)
+{
+ mrs r0, psp
+ bx lr
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+__ASM void __set_PSP(uint32_t topOfProcStack)
+{
+ msr psp, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+__ASM uint32_t __get_MSP(void)
+{
+ mrs r0, msp
+ bx lr
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+__ASM void __set_MSP(uint32_t mainStackPointer)
+{
+ msr msp, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+__ASM uint32_t __REV16(uint16_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+__ASM int32_t __REVSH(int16_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+__ASM void __CLREX(void)
+{
+ clrex
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+__ASM uint32_t __get_BASEPRI(void)
+{
+ mrs r0, basepri
+ bx lr
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+__ASM void __set_BASEPRI(uint32_t basePri)
+{
+ msr basepri, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+__ASM uint32_t __get_PRIMASK(void)
+{
+ mrs r0, primask
+ bx lr
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+__ASM void __set_PRIMASK(uint32_t priMask)
+{
+ msr primask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+__ASM uint32_t __get_FAULTMASK(void)
+{
+ mrs r0, faultmask
+ bx lr
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+__ASM void __set_FAULTMASK(uint32_t faultMask)
+{
+ msr faultmask, r0
+ bx lr
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+__ASM uint32_t __get_CONTROL(void)
+{
+ mrs r0, control
+ bx lr
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+__ASM void __set_CONTROL(uint32_t control)
+{
+ msr control, r0
+ bx lr
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+#pragma diag_suppress=Pe940
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ __ASM("mrs r0, psp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM("msr psp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ __ASM("mrs r0, msp");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM("msr msp, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ __ASM("rev16 r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ __ASM("rbit r0, r0");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ __ASM("ldrexb r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ __ASM("ldrexh r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ __ASM("ldrex r0, [r0]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ __ASM("strexb r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ __ASM("strexh r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ __ASM("strex r0, r0, [r1]");
+ __ASM("bx lr");
+}
+
+#pragma diag_default=Pe940
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+uint32_t __get_PSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, psp" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) );
+}
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+uint32_t __get_MSP(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, msp" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) );
+}
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+uint32_t __get_BASEPRI(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+uint32_t __get_PRIMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+uint32_t __REV(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+uint32_t __REV16(uint16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int32_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+int32_t __REVSH(int16_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint8_t __LDREXB(uint8_t *addr)
+{
+ uint8_t result=0;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint16_t __LDREXH(uint16_t *addr)
+{
+ uint16_t result=0;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+uint32_t __LDREXW(uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXB(uint8_t value, uint8_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXH(uint16_t value, uint16_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+uint32_t __STREXW(uint32_t value, uint32_t *addr)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+uint32_t __get_CONTROL(void)
+{
+ uint32_t result=0;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+#endif
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/external_libs/cmsis/core_cm3.h b/external_libs/cmsis/core_cm3.h new file mode 100644 index 0000000..9f83c1c --- /dev/null +++ b/external_libs/cmsis/core_cm3.h @@ -0,0 +1,1265 @@ +/******************************************************************************
+ * @file: core_cm3.h
+ * @purpose: CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version: V1.10
+ * @date: 24. Feb. 2009
+ *----------------------------------------------------------------------------
+ *
+ * Copyright (C) 2009 ARM Limited. All rights reserved.
+ *
+ * ARM Limited (ARM) is supplying this software for use with Cortex-Mx
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+
+
+
+#ifndef __CM3_CORE_H__
+#define __CM3_CORE_H__
+
+
+#define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
+#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
+
+#define __CORTEX_M (0x03) /*!< Cortex core */
+
+/**
+ * Lint configuration \n
+ * ----------------------- \n
+ *
+ * The following Lint messages will be suppressed and not shown: \n
+ * \n
+ * --- Error 10: --- \n
+ * register uint32_t __regBasePri __asm("basepri"); \n
+ * Error 10: Expecting ';' \n
+ * \n
+ * --- Error 530: --- \n
+ * return(__regBasePri); \n
+ * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
+ * \n
+ * --- Error 550: --- \n
+ * __regBasePri = (basePri & 0x1ff); \n
+ * } \n
+ * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
+ * \n
+ * --- Error 754: --- \n
+ * uint32_t RESERVED0[24]; \n
+ * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 750: --- \n
+ * #define __CM3_CORE_H__ \n
+ * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 528: --- \n
+ * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
+ * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
+ * \n
+ * --- Error 751: --- \n
+ * } InterruptType_Type; \n
+ * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
+ * \n
+ * \n
+ * Note: To re-enable a Message, insert a space before 'lint' * \n
+ *
+ */
+
+/*lint -save */
+/*lint -e10 */
+/*lint -e530 */
+/*lint -e550 */
+/*lint -e754 */
+/*lint -e750 */
+/*lint -e528 */
+/*lint -e751 */
+
+
+#include <stdint.h> /* Include standard types */
+
+#if defined (__ICCARM__)
+ #include <intrinsics.h> /* IAR Intrinsics */
+#endif
+
+
+#ifndef __NVIC_PRIO_BITS
+ #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
+#endif
+
+
+
+
+/**
+ * IO definitions
+ *
+ * define access restrictions to peripheral registers
+ */
+
+#define __I volatile const /*!< defines 'read only' permissions */
+#define __O volatile /*!< defines 'write only' permissions */
+#define __IO volatile /*!< defines 'read / write' permissions */
+
+
+
+/*******************************************************************************
+ * Register Abstraction
+ ******************************************************************************/
+
+
+/* System Reset */
+#define NVIC_VECTRESET 0 /*!< Vector Reset Bit */
+#define NVIC_SYSRESETREQ 2 /*!< System Reset Request */
+#define NVIC_AIRCR_VECTKEY (0x5FA << 16) /*!< AIRCR Key for write access */
+#define NVIC_AIRCR_ENDIANESS 15 /*!< Endianess */
+
+/* Core Debug */
+#define CoreDebug_DEMCR_TRCENA (1 << 24) /*!< DEMCR TRCENA enable */
+#define ITM_TCR_ITMENA 1 /*!< ITM enable */
+
+
+
+
+/* memory mapping struct for Nested Vectored Interrupt Controller (NVIC) */
+typedef struct
+{
+ __IO uint32_t ISER[8]; /*!< Interrupt Set Enable Register */
+ uint32_t RESERVED0[24];
+ __IO uint32_t ICER[8]; /*!< Interrupt Clear Enable Register */
+ uint32_t RSERVED1[24];
+ __IO uint32_t ISPR[8]; /*!< Interrupt Set Pending Register */
+ uint32_t RESERVED2[24];
+ __IO uint32_t ICPR[8]; /*!< Interrupt Clear Pending Register */
+ uint32_t RESERVED3[24];
+ __IO uint32_t IABR[8]; /*!< Interrupt Active bit Register */
+ uint32_t RESERVED4[56];
+ __IO uint8_t IP[240]; /*!< Interrupt Priority Register, 8Bit wide */
+ uint32_t RESERVED5[644];
+ __O uint32_t STIR; /*!< Software Trigger Interrupt Register */
+} NVIC_Type;
+
+
+/* memory mapping struct for System Control Block */
+typedef struct
+{
+ __I uint32_t CPUID; /*!< CPU ID Base Register */
+ __IO uint32_t ICSR; /*!< Interrupt Control State Register */
+ __IO uint32_t VTOR; /*!< Vector Table Offset Register */
+ __IO uint32_t AIRCR; /*!< Application Interrupt / Reset Control Register */
+ __IO uint32_t SCR; /*!< System Control Register */
+ __IO uint32_t CCR; /*!< Configuration Control Register */
+ __IO uint8_t SHP[12]; /*!< System Handlers Priority Registers (4-7, 8-11, 12-15) */
+ __IO uint32_t SHCSR; /*!< System Handler Control and State Register */
+ __IO uint32_t CFSR; /*!< Configurable Fault Status Register */
+ __IO uint32_t HFSR; /*!< Hard Fault Status Register */
+ __IO uint32_t DFSR; /*!< Debug Fault Status Register */
+ __IO uint32_t MMFAR; /*!< Mem Manage Address Register */
+ __IO uint32_t BFAR; /*!< Bus Fault Address Register */
+ __IO uint32_t AFSR; /*!< Auxiliary Fault Status Register */
+ __I uint32_t PFR[2]; /*!< Processor Feature Register */
+ __I uint32_t DFR; /*!< Debug Feature Register */
+ __I uint32_t ADR; /*!< Auxiliary Feature Register */
+ __I uint32_t MMFR[4]; /*!< Memory Model Feature Register */
+ __I uint32_t ISAR[5]; /*!< ISA Feature Register */
+} SCB_Type;
+
+
+/* memory mapping struct for SysTick */
+typedef struct
+{
+ __IO uint32_t CTRL; /*!< SysTick Control and Status Register */
+ __IO uint32_t LOAD; /*!< SysTick Reload Value Register */
+ __IO uint32_t VAL; /*!< SysTick Current Value Register */
+ __I uint32_t CALIB; /*!< SysTick Calibration Register */
+} SysTick_Type;
+
+
+/* memory mapping structur for ITM */
+typedef struct
+{
+ __O union
+ {
+ __O uint8_t u8; /*!< ITM Stimulus Port 8-bit */
+ __O uint16_t u16; /*!< ITM Stimulus Port 16-bit */
+ __O uint32_t u32; /*!< ITM Stimulus Port 32-bit */
+ } PORT [32]; /*!< ITM Stimulus Port Registers */
+ uint32_t RESERVED0[864];
+ __IO uint32_t TER; /*!< ITM Trace Enable Register */
+ uint32_t RESERVED1[15];
+ __IO uint32_t TPR; /*!< ITM Trace Privilege Register */
+ uint32_t RESERVED2[15];
+ __IO uint32_t TCR; /*!< ITM Trace Control Register */
+ uint32_t RESERVED3[29];
+ __IO uint32_t IWR; /*!< ITM Integration Write Register */
+ __IO uint32_t IRR; /*!< ITM Integration Read Register */
+ __IO uint32_t IMCR; /*!< ITM Integration Mode Control Register */
+ uint32_t RESERVED4[43];
+ __IO uint32_t LAR; /*!< ITM Lock Access Register */
+ __IO uint32_t LSR; /*!< ITM Lock Status Register */
+ uint32_t RESERVED5[6];
+ __I uint32_t PID4; /*!< ITM Product ID Registers */
+ __I uint32_t PID5;
+ __I uint32_t PID6;
+ __I uint32_t PID7;
+ __I uint32_t PID0;
+ __I uint32_t PID1;
+ __I uint32_t PID2;
+ __I uint32_t PID3;
+ __I uint32_t CID0;
+ __I uint32_t CID1;
+ __I uint32_t CID2;
+ __I uint32_t CID3;
+} ITM_Type;
+
+
+/* memory mapped struct for Interrupt Type */
+typedef struct
+{
+ uint32_t RESERVED0;
+ __I uint32_t ICTR; /*!< Interrupt Control Type Register */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+ __IO uint32_t ACTLR; /*!< Auxiliary Control Register */
+#else
+ uint32_t RESERVED1;
+#endif
+} InterruptType_Type;
+
+
+/* Memory Protection Unit */
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+typedef struct
+{
+ __I uint32_t TYPE; /*!< MPU Type Register */
+ __IO uint32_t CTRL; /*!< MPU Control Register */
+ __IO uint32_t RNR; /*!< MPU Region RNRber Register */
+ __IO uint32_t RBAR; /*!< MPU Region Base Address Register */
+ __IO uint32_t RASR; /*!< MPU Region Attribute and Size Register */
+ __IO uint32_t RBAR_A1; /*!< MPU Alias 1 Region Base Address Register */
+ __IO uint32_t RASR_A1; /*!< MPU Alias 1 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A2; /*!< MPU Alias 2 Region Base Address Register */
+ __IO uint32_t RASR_A2; /*!< MPU Alias 2 Region Attribute and Size Register */
+ __IO uint32_t RBAR_A3; /*!< MPU Alias 3 Region Base Address Register */
+ __IO uint32_t RASR_A3; /*!< MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+#endif
+
+
+/* Core Debug Register */
+typedef struct
+{
+ __IO uint32_t DHCSR; /*!< Debug Halting Control and Status Register */
+ __O uint32_t DCRSR; /*!< Debug Core Register Selector Register */
+ __IO uint32_t DCRDR; /*!< Debug Core Register Data Register */
+ __IO uint32_t DEMCR; /*!< Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE (0xE000E000) /*!< System Control Space Base Address */
+#define ITM_BASE (0xE0000000) /*!< ITM Base Address */
+#define CoreDebug_BASE (0xE000EDF0) /*!< Core Debug Base Address */
+#define SysTick_BASE (SCS_BASE + 0x0010) /*!< SysTick Base Address */
+#define NVIC_BASE (SCS_BASE + 0x0100) /*!< NVIC Base Address */
+#define SCB_BASE (SCS_BASE + 0x0D00) /*!< System Control Block Base Address */
+
+#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
+#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
+#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
+#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
+#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
+#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
+
+#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1)
+ #define MPU_BASE (SCS_BASE + 0x0D90) /*!< Memory Protection Unit */
+ #define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
+#endif
+
+
+
+/*******************************************************************************
+ * Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+#if defined ( __CC_ARM )
+ #define __ASM __asm /*!< asm keyword for ARM Compiler */
+ #define __INLINE __inline /*!< inline keyword for ARM Compiler */
+
+#elif defined ( __ICCARM__ )
+ #define __ASM __asm /*!< asm keyword for IAR Compiler */
+ #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+ #define __NOP __no_operation /*!< no operation intrinsic in IAR Compiler */
+
+#elif defined ( __GNUC__ )
+ #define __ASM asm /*!< asm keyword for GNU Compiler */
+ #define __INLINE inline /*!< inline keyword for GNU Compiler */
+
+#endif
+
+
+/* ################### Compiler specific Intrinsics ########################### */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#define __enable_fault_irq __enable_fiq
+#define __disable_fault_irq __disable_fiq
+
+#define __NOP __nop
+#define __WFI __wfi
+#define __WFE __wfe
+#define __SEV __sev
+#define __ISB() __isb(0)
+#define __DSB() __dsb(0)
+#define __DMB() __dmb(0)
+#define __REV __rev
+#define __RBIT __rbit
+#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
+#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
+#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
+#define __STREXB(value, ptr) __strex(value, ptr)
+#define __STREXH(value, ptr) __strex(value, ptr)
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+ /* intrinsic unsigned long long __ldrexd(volatile void *ptr) */
+ /* intrinsic int __strexd(unsigned long long val, volatile void *ptr) */
+ /* intrinsic void __enable_irq(); */
+ /* intrinsic void __disable_irq(); */
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+
+#if (__ARMCC_VERSION < 400000)
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+extern void __CLREX(void);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+#else /* (__ARMCC_VERSION >= 400000) */
+
+
+/**
+ * @brief Remove the exclusive lock created by ldrex
+ *
+ * @param none
+ * @return none
+ *
+ * Removes the exclusive lock which is created by ldrex.
+ */
+#define __CLREX __clrex
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0x1ff);
+}
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & 1);
+}
+
+/**
+ * @brief Return the Control Register value
+ *
+ * @param none
+ * @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+#endif /* __ARMCC_VERSION */
+
+
+
+#elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#define __enable_irq __enable_interrupt /*!< global Interrupt enable */
+#define __disable_irq __disable_interrupt /*!< global Interrupt disable */
+
+static __INLINE void __enable_fault_irq() { __ASM ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM ("cpsid f"); }
+
+static __INLINE void __WFI() { __ASM ("wfi"); }
+static __INLINE void __WFE() { __ASM ("wfe"); }
+static __INLINE void __SEV() { __ASM ("sev"); }
+static __INLINE void __CLREX() { __ASM ("clrex"); }
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+/* intrinsic void __set_PRIMASK(); */
+/* intrinsic void __get_PRIMASK(); */
+/* intrinsic void __set_FAULTMASK(); */
+/* intrinsic void __get_FAULTMASK(); */
+/* intrinsic uint32_t __REV(uint32_t value); */
+/* intrinsic uint32_t __REVSH(uint32_t value); */
+/* intrinsic unsigned long __STREX(unsigned long, unsigned long); */
+/* intrinsic unsigned long __LDREX(unsigned long *); */
+
+
+
+#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+static __INLINE void __NOP() { __ASM volatile ("nop"); }
+static __INLINE void __enable_irq() { __ASM volatile ("cpsie i"); }
+static __INLINE void __disable_irq() { __ASM volatile ("cpsid i"); }
+
+static __INLINE void __enable_fault_irq() { __ASM volatile ("cpsie f"); }
+static __INLINE void __disable_fault_irq() { __ASM volatile ("cpsid f"); }
+
+static __INLINE void __WFI() { __ASM volatile ("wfi"); }
+static __INLINE void __WFE() { __ASM volatile ("wfe"); }
+static __INLINE void __SEV() { __ASM volatile ("sev"); }
+static __INLINE void __ISB(arg) { __ASM volatile ("isb"); }
+static __INLINE void __DSB(arg) { __ASM volatile ("dsb"); }
+static __INLINE void __DMB(arg) { __ASM volatile ("dmb"); }
+static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
+
+
+/**
+ * @brief Return the Process Stack Pointer
+ *
+ * @param none
+ * @return uint32_t ProcessStackPointer
+ *
+ * Return the actual process stack pointer
+ */
+extern uint32_t __get_PSP(void);
+
+/**
+ * @brief Set the Process Stack Pointer
+ *
+ * @param uint32_t Process Stack Pointer
+ * @return none
+ *
+ * Assign the value ProcessStackPointer to the MSP
+ * (process stack pointer) Cortex processor register
+ */
+extern void __set_PSP(uint32_t topOfProcStack);
+
+/**
+ * @brief Return the Main Stack Pointer
+ *
+ * @param none
+ * @return uint32_t Main Stack Pointer
+ *
+ * Return the current value of the MSP (main stack pointer)
+ * Cortex processor register
+ */
+extern uint32_t __get_MSP(void);
+
+/**
+ * @brief Set the Main Stack Pointer
+ *
+ * @param uint32_t Main Stack Pointer
+ * @return none
+ *
+ * Assign the value mainStackPointer to the MSP
+ * (main stack pointer) Cortex processor register
+ */
+extern void __set_MSP(uint32_t topOfMainStack);
+
+/**
+ * @brief Return the Base Priority value
+ *
+ * @param none
+ * @return uint32_t BasePriority
+ *
+ * Return the content of the base priority register
+ */
+extern uint32_t __get_BASEPRI(void);
+
+/**
+ * @brief Set the Base Priority value
+ *
+ * @param uint32_t BasePriority
+ * @return none
+ *
+ * Set the base priority register
+ */
+extern void __set_BASEPRI(uint32_t basePri);
+
+/**
+ * @brief Return the Priority Mask value
+ *
+ * @param none
+ * @return uint32_t PriMask
+ *
+ * Return the state of the priority mask bit from the priority mask
+ * register
+ */
+extern uint32_t __get_PRIMASK(void);
+
+/**
+ * @brief Set the Priority Mask value
+ *
+ * @param uint32_t PriMask
+ * @return none
+ *
+ * Set the priority mask bit in the priority mask register
+ */
+extern void __set_PRIMASK(uint32_t priMask);
+
+/**
+ * @brief Return the Fault Mask value
+ *
+ * @param none
+ * @return uint32_t FaultMask
+ *
+ * Return the content of the fault mask register
+ */
+extern uint32_t __get_FAULTMASK(void);
+
+/**
+ * @brief Set the Fault Mask value
+ *
+ * @param uint32_t faultMask value
+ * @return none
+ *
+ * Set the fault mask register
+ */
+extern void __set_FAULTMASK(uint32_t faultMask);
+
+/**
+ * @brief Return the Control Register value
+*
+* @param none
+* @return uint32_t Control value
+ *
+ * Return the content of the control register
+ */
+extern uint32_t __get_CONTROL(void);
+
+/**
+ * @brief Set the Control Register value
+ *
+ * @param uint32_t Control value
+ * @return none
+ *
+ * Set the control register
+ */
+extern void __set_CONTROL(uint32_t control);
+
+/**
+ * @brief Reverse byte order in integer value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in integer value
+ */
+extern uint32_t __REV(uint32_t value);
+
+/**
+ * @brief Reverse byte order in unsigned short value
+ *
+ * @param uint16_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse byte order in unsigned short value
+ */
+extern uint32_t __REV16(uint16_t value);
+
+/*
+ * Reverse byte order in signed short value with sign extension to integer
+ *
+ * @param int16_t value to reverse
+ * @return int32_t reversed value
+ *
+ * @brief Reverse byte order in signed short value with sign extension to integer
+ */
+extern int32_t __REVSH(int16_t value);
+
+/**
+ * @brief Reverse bit order of value
+ *
+ * @param uint32_t value to reverse
+ * @return uint32_t reversed value
+ *
+ * Reverse bit order of value
+ */
+extern uint32_t __RBIT(uint32_t value);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint8_t* address
+ * @return uint8_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint8_t __LDREXB(uint8_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint16_t* address
+ * @return uint16_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint16_t __LDREXH(uint16_t *addr);
+
+/**
+ * @brief LDR Exclusive
+ *
+ * @param uint32_t* address
+ * @return uint32_t value of (*address)
+ *
+ * Exclusive LDR command
+ */
+extern uint32_t __LDREXW(uint32_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint8_t *address
+ * @param uint8_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXB(uint8_t value, uint8_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint16_t *address
+ * @param uint16_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXH(uint16_t value, uint16_t *addr);
+
+/**
+ * @brief STR Exclusive
+ *
+ * @param uint32_t *address
+ * @param uint32_t value to store
+ * @return uint32_t successful / failed
+ *
+ * Exclusive STR command
+ */
+extern uint32_t __STREXW(uint32_t value, uint32_t *addr);
+
+
+#endif
+
+
+
+/* ########################## NVIC functions #################################### */
+
+/**
+ * @brief Set the Priority Grouping in NVIC Interrupt Controller
+ *
+ * @param uint32_t priority_grouping is priority grouping field
+ * @return
+ *
+ * Set the priority grouping field using the required unlock sequence.
+ * The parameter priority_grouping is assigned to the field
+ * SCB->AIRCR [10:8] PRIGROUP field.
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t priority_grouping)
+{
+ uint32_t reg_value=0;
+
+ reg_value = SCB->AIRCR; /* read old register configuration */
+ reg_value &= ~((0xFFFFU << 16) | (0x0F << 8)); /* clear bits to change */
+ reg_value = ((reg_value | NVIC_AIRCR_VECTKEY | (priority_grouping << 8))); /* Insert write key and priorty group */
+ SCB->AIRCR = reg_value;
+}
+
+/**
+ * @brief Enable Interrupt in NVIC Interrupt Controller
+ *
+ * @param IRQn_Type IRQn specifies the interrupt number
+ * @return none
+ *
+ * Enable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+/**
+ * @brief Disable the interrupt line for external interrupt specified
+ *
+ * @param IRQn_Type IRQn is the positive number of the external interrupt
+ * @return none
+ *
+ * Disable a device specific interupt in the NVIC interrupt controller.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+/**
+ * @brief Read the interrupt pending bit for a device specific interrupt source
+ *
+ * @param IRQn_Type IRQn is the number of the device specifc interrupt
+ * @return IRQn_Type Number of pending interrupt or zero
+ *
+ * Read the pending register in NVIC and return the number of the
+ * specified interrupt if its status is pending, otherwise it returns
+ * zero. The interrupt number cannot be a negative value.
+ */
+static __INLINE IRQn_Type NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+ return((IRQn_Type) (NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interrupt bit or 'zero' */
+}
+
+/**
+ * @brief Set the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Set the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+/**
+ * @brief Clear the pending bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return none
+ *
+ * Clear the pending bit for the specified interrupt.
+ * The interrupt number cannot be a negative value.
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+ NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+/**
+ * @brief Read the active bit for an external interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return IRQn_Type Number of pending interrupt or zero
+ *
+ * Read the active register in NVIC and returns the number of the
+ * specified interrupt if its status is active, otherwise it
+ * returns zero. The interrupt number cannot be a negative value.
+ */
+static __INLINE IRQn_Type NVIC_GetActive(IRQn_Type IRQn)
+{
+ return((IRQn_Type)(NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))); /* Return Interruptnumber or 'zero' */
+}
+
+/**
+ * @brief Set the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @param priority is the priority for the interrupt
+ * @return none
+ *
+ * Set the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt. \n
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, int32_t priority)
+{
+ if(IRQn < 0) {
+ SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M3 System Interrupts */
+ else {
+ //NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
+ NVIC->IP[(uint32_t)(IRQn)] = (priority & 0xff); } /* set Priority for device specific Interrupts */
+}
+
+/**
+ * @brief Read the priority for an interrupt
+ *
+ * @param IRQn_Type IRQn is the Number of the interrupt
+ * @return priority is the priority for the interrupt
+ *
+ * Read the priority for the specified interrupt. The interrupt
+ * number can be positive to specify an external (device specific)
+ * interrupt, or negative to specify an internal (core) interrupt.
+ *
+ * The returned priority value is automatically aligned to the implemented
+ * priority bits of the microcontroller.
+ *
+ * Note: The priority cannot be set for every core interrupt.
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+ if(IRQn < 0) {
+ return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M3 system interrupts */
+ else {
+ return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
+}
+
+
+
+/* ################################## SysTick function ############################################ */
+
+#if (!defined (__Vendor_SysTickConfig)) || (__Vendor_SysTickConfig == 0)
+
+/* SysTick constants */
+#define SYSTICK_ENABLE 0 /* Config-Bit to start or stop the SysTick Timer */
+#define SYSTICK_TICKINT 1 /* Config-Bit to enable or disable the SysTick interrupt */
+#define SYSTICK_CLKSOURCE 2 /* Clocksource has the offset 2 in SysTick Control and Status Register */
+#define SYSTICK_MAXCOUNT ((1<<24) -1) /* SysTick MaxCount */
+
+/**
+ * @brief Initialize and start the SysTick counter and its interrupt.
+ *
+ * @param uint32_t ticks is the number of ticks between two interrupts
+ * @return none
+ *
+ * Initialise the system tick timer and its interrupt and start the
+ * system tick timer / counter in free running mode to generate
+ * periodical interrupts.
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+ if (ticks > SYSTICK_MAXCOUNT) return (1); /* Reload value impossible */
+
+ SysTick->LOAD = (ticks & SYSTICK_MAXCOUNT) - 1; /* set reload register */
+ NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
+ SysTick->VAL = (0x00); /* Load the SysTick Counter Value */
+ SysTick->CTRL = (1 << SYSTICK_CLKSOURCE) | (1<<SYSTICK_ENABLE) | (1<<SYSTICK_TICKINT); /* Enable SysTick IRQ and SysTick Timer */
+ return (0); /* Function successful */
+}
+
+#endif
+
+
+
+
+
+/* ################################## Reset function ############################################ */
+
+/**
+ * @brief Initiate a system reset request.
+ *
+ * @param none
+ * @return none
+ *
+ * Initialize a system reset request to reset the MCU
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+ SCB->AIRCR = (NVIC_AIRCR_VECTKEY | (SCB->AIRCR & (0x700)) | (1<<NVIC_SYSRESETREQ)); /* Keep priority group unchanged */
+}
+
+
+/* ################################## Debug Output function ############################################ */
+
+
+/**
+ * @brief Outputs a character via the ITM channel 0
+ *
+ * @param uint32_t character to output
+ * @return uint32_t input character
+ *
+ * The function outputs a character via the ITM channel 0.
+ * The function returns when no debugger is connected that has booked the output.
+ * It is blocking when a debugger is connected, but the previous character send is not transmitted.
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+ if(ch == '\n') ITM_SendChar('\r');
+
+ if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA) &&
+ (ITM->TCR & ITM_TCR_ITMENA) &&
+ (ITM->TER & (1UL << 0)) )
+ {
+ while (ITM->PORT[0].u32 == 0);
+ ITM->PORT[0].u8 = (uint8_t) ch;
+ }
+ return (ch);
+}
+
+#endif
+
+/*lint -restore */
diff --git a/usb-device-audio-speaker-project/Makefile b/usb-device-audio-speaker-project/Makefile new file mode 100644 index 0000000..2baa56e --- /dev/null +++ b/usb-device-audio-speaker-project/Makefile @@ -0,0 +1,241 @@ +# ----------------------------------------------------------------------------
+# ATMEL Microcontroller Software Support
+# ----------------------------------------------------------------------------
+# Copyright (c) 2008, Atmel Corporation
+#
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# - Redistributions of source code must retain the above copyright notice,
+# this list of conditions and the disclaimer below.
+#
+# Atmel's name may not be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+# ----------------------------------------------------------------------------
+
+# Makefile for compiling the usb-device-core-project project
+
+#-------------------------------------------------------------------------------
+# User-modifiable options
+#-------------------------------------------------------------------------------
+
+# Chip & board used for compilation
+# (can be overriden by adding CHIP=chip and BOARD=board to the command-line)
+CHIP = at91sam3u4 +BOARD = at91sam3u-ek
+
+# Trace level used for compilation
+# (can be overriden by adding TRACE_LEVEL=#number to the command-line)
+# TRACE_LEVEL_DEBUG 5
+# TRACE_LEVEL_INFO 4
+# TRACE_LEVEL_WARNING 3
+# TRACE_LEVEL_ERROR 2
+# TRACE_LEVEL_FATAL 1
+# TRACE_LEVEL_NO_TRACE 0
+TRACE_LEVEL = 4
+
+# Optimization level, put in comment for debugging
+OPTIMIZATION = -Os
+
+# AT91 library directory
+AT91LIB = ../../at91lib
+
+# External library
+EXT_LIBS= ../external_libs
+
+# Output file basename
+OUTPUT = usb-device-core-project-$(BOARD)-$(CHIP)
+
+# Compile with chip specific features
+include $(AT91LIB)/boards/$(BOARD)/$(CHIP)/chip.mak
+
+# Compile for all memories available on the board (this sets $(MEMORIES))
+include $(AT91LIB)/boards/$(BOARD)/board.mak
+
+# Output directories
+BIN = bin
+OBJ = obj
+
+#-------------------------------------------------------------------------------
+# Tools
+#-------------------------------------------------------------------------------
+
+# Tool suffix when cross-compiling
+CROSS_COMPILE = arm-none-eabi-
+
+# Compilation tools
+CC = $(CROSS_COMPILE)gcc
+SIZE = $(CROSS_COMPILE)size
+STRIP = $(CROSS_COMPILE)strip
+OBJCOPY = $(CROSS_COMPILE)objcopy
+
+# Flags
+INCLUDES += -I$(AT91LIB)/boards/$(BOARD)
+INCLUDES += -I$(AT91LIB)/peripherals
+INCLUDES += -I$(AT91LIB)/components
+INCLUDES += -I$(AT91LIB)/drivers +INCLUDES += -I$(AT91LIB)
+INCLUDES += -I$(EXT_LIBS)
+INCLUDES += -I$(EXT_LIBS)/cmsis
+
+ifeq ($(CHIP_CORE), cortexm3)
+TARGET_OPTS = -mcpu=cortex-m3 -mthumb
+else
+TARGET_OPTS =
+endif
+
+CFLAGS += $(TARGET_OPTS)
+CFLAGS += -Wall -mlong-calls -ffunction-sections
+CFLAGS += -g $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -DTRACE_LEVEL=$(TRACE_LEVEL)
+ASFLAGS = $(TARGET_OPTS) -Wall -g $(OPTIMIZATION) $(INCLUDES) -D$(CHIP) -D__ASSEMBLY__
+LDFLAGS = -g $(OPTIMIZATION) -nostartfiles $(TARGET_OPTS) -Wl,--gc-sections
+
+#-------------------------------------------------------------------------------
+# Files
+#-------------------------------------------------------------------------------
+
+# Directories where source files can be found
+PERIPH = $(AT91LIB)/peripherals
+BOARDS = $(AT91LIB)/boards
+UTILITY = $(AT91LIB)/utility
+COMP = $(AT91LIB)/components +DRIVER = $(AT91LIB)/drivers +USB = $(AT91LIB)/usb
+
+VPATH += $(COMP)/codec-wm8731 +VPATH += $(UTILITY) +VPATH += $(PERIPH)/dbgu
+VPATH += $(PERIPH)/pio
+VPATH += $(PERIPH)/irq
+VPATH += $(PERIPH)/ssc
+VPATH += $(PERIPH)/twi
+VPATH += $(PERIPH)/pmc
+VPATH += $(PERIPH)/cp15
+VPATH += $(BOARDS)/$(BOARD)
+VPATH += $(BOARDS)/$(BOARD)/$(CHIP)
+VPATH += $(DRIVER)/twi +VPATH += $(PERIPH)/mci +VPATH += $(PERIPH)/dma +VPATH += $(DRIVER)/dmad +VPATH += $(EXT_LIBS)/cmsis
+ +VPATH += $(USB)/device/audio-speaker +VPATH += $(USB)/device/core
+VPATH += $(USB)/common/core
+VPATH += $(USB)/common/audio +
+# Objects built from C source files
+C_OBJECTS += main.o
+C_OBJECTS += wm8731.o
+C_OBJECTS += USBD_UDPHS.o
+C_OBJECTS += USBDDriver.o
+C_OBJECTS += USBDCallbacks_Initialized.o
+C_OBJECTS += USBDCallbacks_Reset.o
+#C_OBJECTS += USBDCallbacks_Resumed.o
+#C_OBJECTS += USBDCallbacks_Suspended.o
+C_OBJECTS += USBDDriverCb_CfgChanged.o
+#C_OBJECTS += USBDDriverCb_IfSettingChanged.o
+C_OBJECTS += USBInterfaceRequest.o
+C_OBJECTS += USBFeatureRequest.o
+C_OBJECTS += USBGenericRequest.o
+C_OBJECTS += USBGetDescriptorRequest.o
+C_OBJECTS += USBSetAddressRequest.o
+C_OBJECTS += USBSetConfigurationRequest.o
+C_OBJECTS += USBGenericDescriptor.o
+C_OBJECTS += USBConfigurationDescriptor.o
+C_OBJECTS += USBEndpointDescriptor.o
+C_OBJECTS += dbgu.o
+C_OBJECTS += pio.o
+C_OBJECTS += pio_it.o
+C_OBJECTS += ssc.o +C_OBJECTS += twi.o
+C_OBJECTS += pmc.o
+C_OBJECTS += led.o
+C_OBJECTS += twid.o
+C_OBJECTS += string.o
+C_OBJECTS += stdio.o
+C_OBJECTS += math.o +C_OBJECTS += trace.o +C_OBJECTS += board_memories.o
+C_OBJECTS += board_lowlevel.o
+ +C_OBJECTS += AUDDSpeakerDriverDescriptors.o AUDDSpeakerDriver.o +C_OBJECTS += AUDDSpeakerChannel.o +C_OBJECTS += AUDGenericRequest.o AUDFeatureUnitRequest.o + +
+# Objects for different chips
+ifeq ($(CHIP_CORE), cortexm3)
+C_OBJECTS += nvic.o
+C_OBJECTS += exceptions.o
+C_OBJECTS += board_cstartup_gnu.o
+C_OBJECTS += core_cm3.o
+else
+C_OBJECTS += aic.o
+C_OBJECTS += cp15.o
+endif
+ +ifeq ($(CHIP_IP_MCI), MCI_DMA) +C_OBJECTS += dmad.o +C_OBJECTS += dma.o +C_OBJECTS += mci_hs.o +else +C_OBJECTS += mci.o +endif +
+# Objects built from Assembly source files
+ifneq ($(CHIP_CORE), cortexm3)
+ASM_OBJECTS += board_cstartup.o
+ASM_OBJECTS += cp15_asm.o
+endif
+
+# Append OBJ and BIN directories to output filename
+OUTPUT := $(BIN)/$(OUTPUT)
+
+#-------------------------------------------------------------------------------
+# Rules
+#-------------------------------------------------------------------------------
+
+all: $(BIN) $(OBJ) $(MEMORIES)
+
+$(BIN) $(OBJ):
+ mkdir $@
+
+define RULES
+C_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(C_OBJECTS))
+ASM_OBJECTS_$(1) = $(addprefix $(OBJ)/$(1)_, $(ASM_OBJECTS))
+
+$(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1))
+ $(CC) $(LDFLAGS) -T"$(AT91LIB)/boards/$(BOARD)/$(CHIP)/$$@.lds" -o $(OUTPUT)-$$@.elf $$^
+ $(OBJCOPY) -O binary $(OUTPUT)-$$@.elf $(OUTPUT)-$$@.bin
+ $(SIZE) $$^ $(OUTPUT)-$$@.elf
+
+$$(C_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.c Makefile $(OBJ) $(BIN)
+ $(CC) $(CFLAGS) -D$(1) -c -o $$@ $$<
+
+$$(ASM_OBJECTS_$(1)): $(OBJ)/$(1)_%.o: %.S Makefile $(OBJ) $(BIN)
+ $(CC) $(ASFLAGS) -D$(1) -c -o $$@ $$<
+
+debug_$(1): $(1)
+ perl ../resources/gdb/debug.pl $(OUTPUT)-$(1).elf
+
+endef
+
+$(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY))))
+
+clean:
+ -rm -f $(OBJ)/*.o $(BIN)/*.bin $(BIN)/*.elf
+
diff --git a/usb-device-audio-speaker-project/bin/.empty_dir b/usb-device-audio-speaker-project/bin/.empty_dir new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/usb-device-audio-speaker-project/bin/.empty_dir diff --git a/usb-device-audio-speaker-project/main.c b/usb-device-audio-speaker-project/main.c new file mode 100644 index 0000000..46e651a --- /dev/null +++ b/usb-device-audio-speaker-project/main.c @@ -0,0 +1,835 @@ +/* ----------------------------------------------------------------------------
+ * ATMEL Microcontroller Software Support
+ * ----------------------------------------------------------------------------
+ * Copyright (c) 2008, Atmel Corporation
+ * Copyright (c) 2011, Harald Welte <laforge@gnumonks.org>
+ *
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * - Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the disclaimer below.
+ *
+ * Atmel's name may not be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+ * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+ * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+ * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+ * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+ * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * ----------------------------------------------------------------------------
+ */
+
+//-----------------------------------------------------------------------------
+/// \dir "USB audio speaker"
+///
+/// !!!Purpose
+///
+/// The USB Audio Speaker Project will help you to get familiar with the
+/// USB Device Port(UDP) and SSC interface on AT91SAM microcontrollers. Also
+/// it can help you to be familiar with the USB Framework that is used for
+/// rapid development of USB-compliant class drivers such as USB Audio Device
+/// class.
+///
+/// You can find following information depends on your needs:
+/// - Sample usage of USB Audio Device Class driver and SSC-I2S driver.
+/// - USB Audio Class driver development based on the AT91 USB Framework.
+/// - USB enumerate sequence, the standard and class-specific descriptors and
+/// requests handling.
+/// - The initialize sequence and usage of UDP interface.
+/// - The initialize sequence and usage of SSC interface with PDC.
+///
+/// !See
+/// - ssc: SSC interface driver
+/// - "i2s-wm8731: I2S codec wm8731 driver
+/// - usb: USB Framework, Audio Device Class driver and UDP interface driver
+/// - "AT91 USB device framework"
+/// - "USBD API"
+/// - "audio-speaker"
+///
+/// !!!Requirements
+///
+/// This package can be used with all Atmel evaluation kits that have both
+/// UDP and SSC interface.
+///
+/// The current supported board list:
+/// - at91sam3u-ek
+///
+/// !!!Description
+///
+/// When an EK running this program connected to a host (PC for example), with
+/// USB cable, the EK appears as a desktop speaker for the host. Then the host
+/// can play sound through host software. The %audio stream from the host is
+/// then sent to the EK, and eventually sent to %audio DAC connected to AC97
+/// of AT91SAM chips. At the same time, the %audio stream received is also sent
+/// back to host from EK for recording.
+///
+/// !!!Usage
+///
+/// -# Build the program and download it inside the evaluation board. Please
+/// refer to the
+/// <a href="http://www.atmel.com/dyn/resources/prod_documents/doc6224.pdf">
+/// SAM-BA User Guide</a>, the
+/// <a href="http://www.atmel.com/dyn/resources/prod_documents/doc6310.pdf">
+/// GNU-Based Software Development</a> application note or to the
+/// <a href="ftp://ftp.iar.se/WWWfiles/arm/Guides/EWARM_UserGuide.ENU.pdf">
+/// IAR EWARM User Guide</a>, depending on your chosen solution.
+/// -# On the computer, open and configure a terminal application
+/// (e.g. HyperTerminal on Microsoft Windows) with these settings:
+/// - 115200 bauds
+/// - 8 bits of data
+/// - No parity
+/// - 1 stop bit
+/// - No flow control
+/// -# Start the application.
+/// -# In the terminal window, the following text should appear:
+/// \code
+/// -- USB Device Audio Speaker Project xxx --
+/// -- AT91xxxxxx-xx
+/// -- Compiled: xxx xx xxxx xx:xx:xx --
+/// \endcode
+/// -# When connecting USB cable to windows, the LED blinks, and the host
+/// reports a new USB %device attachment (if it's the first time you connect
+/// an %audio speaker demo board to your host). You can find new
+/// "USB Composite Device" and "USB Audio Device" appear in the hardware
+/// %device list.
+/// -# You can play sound in host side through the USB Audio Device, and it
+/// can be heard from the earphone connected to the EK.
+/// -# When playing sound, you can also record through the USB Audio Device on
+/// the host.
+///
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+/// \unit
+///
+/// !Purpose
+///
+/// This file contains all the specific code for the
+/// usb-device-audio-speaker-project
+///
+/// !Contents
+///
+/// The code can be roughly broken down as follows:
+/// - Configuration functions
+/// - VBus_Configure
+/// - PIO & Clock configurations in start of main
+/// - Interrupt handlers
+/// - ISR_SSC
+/// - Callback functions
+/// - AUDDSpeakerChannel_MuteChanged
+/// - FrameReceived
+/// - The main function, which implements the program behavior
+///
+/// Please refer to the list of functions in the #Overview# tab of this unit
+/// for more detailed information.
+//-----------------------------------------------------------------------------
+
+//-----------------------------------------------------------------------------
+// Headers
+//------------------------------------------------------------------------------
+
+#include <board.h>
+#include <board_memories.h>
+#include <pio/pio.h>
+#include <pio/pio_it.h>
+#include <ssc/ssc.h>
+#include <irq/irq.h>
+#include <codec-wm8731/wm8731.h>
+#include <twi/twi.h>
+#include <twi/twid.h>
+#include <aic/aic.h>
+#include <dbgu/dbgu.h>
+#include <utility/trace.h>
+#include <utility/led.h>
+#include <usb/device/core/USBD.h>
+#include <usb/device/audio-speaker/AUDDSpeakerDriver.h>
+#include <usb/device/audio-speaker/AUDDSpeakerChannel.h>
+#include <pmc/pmc.h>
+
+#include <string.h>
+#include <stdio.h>
+
+#define AUDIO_USING_DMA
+#if defined(AUDIO_USING_DMA)
+#include <dmad/dmad.h>
+#include <dma/dma.h>
+#endif
+
+//------------------------------------------------------------------------------
+// Definitions
+//------------------------------------------------------------------------------
+
+/// Master clock frequency in Hz
+#define SSC_MCK 49152000
+
+// TWI clock
+#define TWI_CLOCK 100000
+
+/// Number of available audio buffers.
+#define BUFFER_NUMBER 5
+/// Size of one buffer in bytes.
+#define BUFFER_SIZE (AUDDSpeakerDriver_BYTESPERFRAME + \
+ AUDDSpeakerDriver_BYTESPERSUBFRAME)
+
+/// Delay in ms for starting the DAC transmission after a frame has been received.
+#define DAC_DELAY 2
+
+#define SAMPLE_RATE (48000)
+#define SLOT_BY_FRAME (2)
+#define BITS_BY_SLOT (16)
+
+#define AT91C_I2S_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ AT91C_SSC_CKS_DIV +\
+ AT91C_SSC_CKO_CONTINOUS +\
+ AT91C_SSC_START_FALL_RF +\
+ ((1<<16) & AT91C_SSC_STTDLY) +\
+ ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+#define AT91C_I2S_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+ (nb_bit_by_slot-1) +\
+ AT91C_SSC_MSBF +\
+ (((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB) +\
+ (((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+ AT91C_SSC_FSOS_NEGATIVE)
+
+// PMC define
+#define AT91C_CKGR_PLLR AT91C_CKGR_PLLAR
+#define AT91C_PMC_LOCK AT91C_PMC_LOCKA
+
+#define AT91C_CKGR_MUL_SHIFT 16
+#define AT91C_CKGR_OUT_SHIFT 14
+#define AT91C_CKGR_PLLCOUNT_SHIFT 8
+#define AT91C_CKGR_DIV_SHIFT 0
+
+/// Use for power management
+#define STATE_IDLE 0
+/// The USB device is in suspend state
+#define STATE_SUSPEND 4
+/// The USB device is in resume state
+#define STATE_RESUME 5
+
+//------------------------------------------------------------------------------
+// Internal variables
+//------------------------------------------------------------------------------
+/// State of USB, for suspend and resume
+unsigned char USBState = STATE_IDLE;
+
+/// Data buffers for receiving audio frames from the USB host.
+static unsigned char buffers[BUFFER_NUMBER][BUFFER_SIZE];
+/// Number of bytes stored in each data buffer.
+static volatile unsigned int bufferSizes[BUFFER_NUMBER];
+/// Next buffer in which USB data can be stored.
+static volatile unsigned int inBufferIndex = 0;
+/// Next buffer which should be sent to the DAC.
+static volatile unsigned int outBufferIndex = 0;
+/// Number of buffers that can be sent to the DAC.
+static volatile unsigned int numBuffersToSend = 0;
+
+/// Current state of the DAC transmission.
+static volatile unsigned int isDacActive = 0;
+/// Number of buffers to wait for before the DAC starts to transmit data.
+static volatile unsigned int dacDelay;
+
+/// List of pins to configure for the application.
+static const Pin pins[] = {PINS_TWI0, PINS_SSC_CODEC, PIN_PCK0};
+
+static Twid twid;
+
+//------------------------------------------------------------------------------
+// VBus monitoring (optional)
+//------------------------------------------------------------------------------
+#if defined(PIN_USB_VBUS)
+
+#define VBUS_CONFIGURE() VBus_Configure()
+
+/// VBus pin instance.
+static const Pin pinVbus = PIN_USB_VBUS;
+
+//------------------------------------------------------------------------------
+/// Handles interrupts coming from PIO controllers.
+//------------------------------------------------------------------------------
+static void ISR_Vbus(const Pin *pPin)
+{
+ // Check current level on VBus
+ if (PIO_Get(&pinVbus)) {
+
+ TRACE_INFO("VBUS conn\n\r");
+ USBD_Connect();
+ }
+ else {
+
+ TRACE_INFO("VBUS discon\n\r");
+ USBD_Disconnect();
+ }
+}
+
+//------------------------------------------------------------------------------
+/// Configures the VBus pin to trigger an interrupt when the level on that pin
+/// changes.
+//------------------------------------------------------------------------------
+static void VBus_Configure( void )
+{
+ TRACE_INFO("VBus configuration\n\r");
+
+ // Configure PIO
+ PIO_Configure(&pinVbus, 1);
+ PIO_ConfigureIt(&pinVbus, ISR_Vbus);
+ PIO_EnableIt(&pinVbus);
+
+ // Check current level on VBus
+ if (PIO_Get(&pinVbus)) {
+
+ // if VBUS present, force the connect
+ TRACE_INFO("VBUS conn\n\r");
+ USBD_Connect();
+ }
+ else {
+ TRACE_INFO("VBUS discon\n\r");
+ USBD_Disconnect();
+ }
+}
+
+#else
+ #define VBUS_CONFIGURE() USBD_Connect()
+#endif //#if defined(PIN_USB_VBUS)
+
+#if defined (CP15_PRESENT)
+//------------------------------------------------------------------------------
+/// Put the CPU in 32kHz, disable PLL, main oscillator
+/// Put voltage regulator in standby mode
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ PMC_CPUInIdleMode();
+}
+//------------------------------------------------------------------------------
+/// Put voltage regulator in normal mode
+/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+}
+
+#elif defined(at91sam7a3)
+//------------------------------------------------------------------------------
+/// Put the CPU in 32kHz, disable PLL, main oscillator
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ // MCK=48MHz to MCK=32kHz
+ // MCK = SLCK/2 : change source first from 48 000 000 to 18. / 2 = 9M
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=SLCK : then change prescaler
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // disable PLL
+ AT91C_BASE_PMC->PMC_PLLR = 0;
+ // Disable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = 0;
+
+ PMC_DisableProcessorClock();
+}
+//------------------------------------------------------------------------------
+/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+ // MCK=32kHz to MCK=48MHz
+ // enable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = (( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS ) );
+
+ // enable PLL@96MHz
+ AT91C_BASE_PMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) |
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+ (AT91C_CKGR_MUL & (0x48<<16)));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK ) );
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;
+ // MCK=SLCK/2 : change prescaler first
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=PLLCK/2 : then change source
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+}
+
+#elif defined (at91sam7se)
+//------------------------------------------------------------------------------
+/// Put the CPU in 32kHz, disable PLL, main oscillator
+/// Put voltage regulator in standby mode
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ // MCK=48MHz to MCK=32kHz
+ // MCK = SLCK/2 : change source first from 48 000 000 to 18. / 2 = 9M
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=SLCK : then change prescaler
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // disable PLL
+ AT91C_BASE_PMC->PMC_PLLR = 0;
+ // Disable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = 0;
+
+ // Voltage regulator in standby mode : Enable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR |= AT91C_VREG_PSTDBY;
+
+ PMC_DisableProcessorClock();
+}
+//------------------------------------------------------------------------------
+/// Put voltage regulator in normal mode
+/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+ // Voltage regulator in normal mode : Disable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+
+ // MCK=32kHz to MCK=48MHz
+ // enable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = (( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS ) );
+
+ // enable PLL@96MHz
+ AT91C_BASE_PMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) |
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+ (AT91C_CKGR_MUL & (0x48<<16)));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK ) );
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;
+ // MCK=SLCK/2 : change prescaler first
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=PLLCK/2 : then change source
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+}
+
+#elif defined (at91sam7s)
+//------------------------------------------------------------------------------
+/// Put the CPU in 32kHz, disable PLL, main oscillator
+/// Put voltage regulator in standby mode
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ // MCK=48MHz to MCK=32kHz
+ // MCK = SLCK/2 : change source first from 48 000 000 to 18. / 2 = 9M
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=SLCK : then change prescaler
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // disable PLL
+ AT91C_BASE_PMC->PMC_PLLR = 0;
+ // Disable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = 0;
+
+ // Voltage regulator in standby mode : Enable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR |= AT91C_VREG_PSTDBY;
+
+ PMC_DisableProcessorClock();
+}
+
+//------------------------------------------------------------------------------
+/// Put voltage regulator in normal mode
+/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+ // Voltage regulator in normal mode : Disable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+
+ // MCK=32kHz to MCK=48MHz
+ // enable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = (( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS ) );
+
+ // enable PLL@96MHz
+ AT91C_BASE_PMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) |
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+ (AT91C_CKGR_MUL & (0x48<<16)));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK ) );
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;
+ // MCK=SLCK/2 : change prescaler first
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=PLLCK/2 : then change source
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+
+}
+
+#elif defined (at91sam7x) || defined (at91sam7xc)
+//------------------------------------------------------------------------------
+/// Put the CPU in 32kHz, disable PLL, main oscillator
+/// Put voltage regulator in standby mode
+//------------------------------------------------------------------------------
+void LowPowerMode(void)
+{
+ // MCK=48MHz to MCK=32kHz
+ // MCK = SLCK/2 : change source first from 48 000 000 to 18. / 2 = 9M
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=SLCK : then change prescaler
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // disable PLL
+ AT91C_BASE_PMC->PMC_PLLR = 0;
+ // Disable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = 0;
+
+ // Voltage regulator in standby mode : Enable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR |= AT91C_VREG_PSTDBY;
+
+ PMC_DisableProcessorClock();
+}
+
+//------------------------------------------------------------------------------
+/// Put voltage regulator in normal mode
+/// Return the CPU to normal speed 48MHz, enable PLL, main oscillator
+//------------------------------------------------------------------------------
+void NormalPowerMode(void)
+{
+ // Voltage regulator in normal mode : Disable VREG Low Power Mode
+ AT91C_BASE_VREG->VREG_MR &= ~AT91C_VREG_PSTDBY;
+
+ // MCK=32kHz to MCK=48MHz
+ // enable Main Oscillator
+ AT91C_BASE_PMC->PMC_MOR = (( (AT91C_CKGR_OSCOUNT & (0x06 <<8)) | AT91C_CKGR_MOSCEN ));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MOSCS ) );
+
+ // enable PLL@96MHz
+ AT91C_BASE_PMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x0E) |
+ (AT91C_CKGR_PLLCOUNT & (28<<8)) |
+ (AT91C_CKGR_MUL & (0x48<<16)));
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK ) );
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ AT91C_BASE_CKGR->CKGR_PLLR |= AT91C_CKGR_USBDIV_1 ;
+ // MCK=SLCK/2 : change prescaler first
+ AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+ // MCK=PLLCK/2 : then change source
+ AT91C_BASE_PMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
+ while( !( AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY ) );
+}
+#else
+//------------------------------------------------------------------------------
+/// Put the CPU in low power mode (for customer)
+//------------------------------------------------------------------------------
+static void LowPowerMode(void)
+{
+}
+
+//------------------------------------------------------------------------------
+/// Return the CPU to normal speed (for customer)
+//------------------------------------------------------------------------------
+static void NormalPowerMode(void)
+{
+}
+#endif
+
+
+//------------------------------------------------------------------------------
+// Callbacks re-implementation
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+/// Invoked when the USB device leaves the Suspended state. By default,
+/// configures the LEDs.
+//------------------------------------------------------------------------------
+void USBDCallbacks_Resumed(void)
+{
+ // Initialize LEDs
+ LED_Configure(USBD_LEDPOWER);
+ LED_Set(USBD_LEDPOWER);
+ LED_Configure(USBD_LEDUSB);
+ LED_Clear(USBD_LEDUSB);
+ USBState = STATE_RESUME;
+}
+
+//------------------------------------------------------------------------------
+/// Invoked when the USB device gets suspended. By default, turns off all LEDs.
+//------------------------------------------------------------------------------
+void USBDCallbacks_Suspended(void)
+{
+ // Turn off LEDs
+ LED_Clear(USBD_LEDPOWER);
+ LED_Clear(USBD_LEDUSB);
+ USBState = STATE_SUSPEND;
+}
+
+
+//------------------------------------------------------------------------------
+/// Invoked when an audio channel get muted or unmuted. Mutes/unmutes the
+/// channel at the DAC level.
+/// \param channel Pointer to an AUDDSpeakerChannel instance.
+/// \param muted Indicates the new mute status of the channel.
+//------------------------------------------------------------------------------
+void AUDDSpeakerChannel_MuteChanged(
+ AUDDSpeakerChannel *channel,
+ unsigned char muted)
+{
+ // Master channel
+ if (AUDDSpeakerChannel_GetNumber(channel) == AUDDSpeakerDriver_MASTERCHANNEL) {
+
+ if (muted) {
+
+ TRACE_INFO("MuteMaster ");
+ //AT73C213_SetMuteStatus(1, 1);
+ }
+ else {
+
+ TRACE_INFO("UnmuteMaster ");
+ //AT73C213_SetMuteStatus(0, 0);
+ }
+ }
+}
+
+//------------------------------------------------------------------------------
+// Internal functions
+//------------------------------------------------------------------------------
+
+#if 0
+//------------------------------------------------------------------------------
+/// Handles interrupts coming from the SSC. Sends remaining audio buffers
+/// or stops the DAC transmission.
+//------------------------------------------------------------------------------
+static void ISR_SSC(void)
+{
+ if ((AT91C_BASE_SSC0->SSC_SR & AT91C_SSC_TXBUFE) != 0) {
+
+ // End of transmission
+ TRACE_DEBUG("End ");
+ SSC_DisableInterrupts(AT91C_BASE_SSC0,
+ AT91C_SSC_TXBUFE
+ | AT91C_SSC_ENDTX);
+ AT91C_BASE_SSC0->SSC_PTCR = AT91C_PDC_TXTDIS;
+ isDacActive = 0;
+ }
+ else if (numBuffersToSend > 0) {
+
+ // Check the number of available buffers
+ if (numBuffersToSend > DAC_DELAY) {
+
+ // Strip one sample on all channels
+ bufferSizes[outBufferIndex] -= AUDDSpeakerDriver_NUMCHANNELS;
+ }
+ else if (numBuffersToSend < DAC_DELAY) {
+
+ // Copy the last sample on all channels
+ memcpy(&buffers[outBufferIndex][bufferSizes[outBufferIndex]],
+ &buffers[outBufferIndex][bufferSizes[outBufferIndex] - AUDDSpeakerDriver_BYTESPERSUBFRAME],
+ AUDDSpeakerDriver_BYTESPERSUBFRAME);
+ bufferSizes[outBufferIndex] += AUDDSpeakerDriver_NUMCHANNELS;
+ }
+
+ // Load next buffer
+ SSC_WriteBuffer(AT91C_BASE_SSC0
+ buffers[outBufferIndex],
+ bufferSizes[outBufferIndex]);
+ outBufferIndex = (outBufferIndex + 1) % BUFFER_NUMBER;
+ numBuffersToSend--;
+ }
+ else {
+
+ SSC_DisableInterrupts(AT91C_BASE_SSC0,
+ AT91C_SSC_ENDTX);
+ }
+}
+#endif
+
+#if defined(AUDIO_USING_DMA)
+void HDMA_IrqHandler(void)
+{
+ unsigned intFlag = 1 << (BOARD_SSC_DMA_CHANNEL + 8);
+ if (numBuffersToSend > 0) {
+ SSC_WriteBuffer(AT91C_BASE_SSC0, buffers[outBufferIndex], bufferSizes[outBufferIndex]);
+ outBufferIndex = (outBufferIndex + 1) % BUFFER_NUMBER;
+
+ DMA_EnableIt(intFlag);
+ DMA_EnableChannel(BOARD_SSC_DMA_CHANNEL);
+ numBuffersToSend--;
+ } else {
+ DMA_DisableIt(intFlag);
+ DMA_DisableChannel(BOARD_SSC_DMA_CHANNEL);
+ SSC_DisableTransmitter(AT91C_BASE_SSC0);
+ }
+}
+#endif
+
+//------------------------------------------------------------------------------
+/// Invoked when a frame has been received.
+//------------------------------------------------------------------------------
+static void FrameReceived(unsigned int unused,
+ char status,
+ unsigned int transferred,
+ unsigned int remaining)
+{
+ bufferSizes[inBufferIndex] = transferred / AUDDSpeakerDriver_BYTESPERSAMPLE;
+ inBufferIndex = (inBufferIndex + 1) % BUFFER_NUMBER;
+ numBuffersToSend++;
+
+ TRACE_DEBUG("FrameReceived ");
+
+ // Start DAc transmission if necessary
+ if (!isDacActive) {
+
+ TRACE_DEBUG("Start ");
+ dacDelay = DAC_DELAY;
+ isDacActive = 1;
+ }
+ // Wait until a few buffers have been received
+ else if (dacDelay > 0) {
+
+ dacDelay--;
+ }
+ // Start sending buffers
+ else {
+#if defined(AUDIO_USING_DMA)
+ SSC_EnableTransmitter(AT91C_BASE_SSC0);
+
+ unsigned intFlag = 1 << (BOARD_SSC_DMA_CHANNEL + 8);
+ DMA_DisableIt(intFlag);
+ DMA_DisableChannel(BOARD_SSC_DMA_CHANNEL);
+
+ SSC_WriteBuffer(AT91C_BASE_SSC0,
+ buffers[outBufferIndex],
+ bufferSizes[outBufferIndex]);
+ outBufferIndex = (outBufferIndex + 1) % BUFFER_NUMBER;
+ numBuffersToSend--;
+#if 0
+ SSC_WriteBuffer(AT91C_BASE_SSC0,
+ buffers[outBufferIndex],
+ bufferSizes[outBufferIndex]);
+ outBufferIndex = (outBufferIndex + 1) % BUFFER_NUMBER;
+ numBuffersToSend--;
+#endif
+
+ DMA_EnableIt(intFlag);
+ DMA_EnableChannel(BOARD_SSC_DMA_CHANNEL);
+#else
+#error DMA required for audio!!
+#endif
+ }
+
+ // Receive next packet
+ AUDDSpeakerDriver_Read(buffers[inBufferIndex],
+ AUDDSpeakerDriver_BYTESPERFRAME,
+ (TransferCallback) FrameReceived,
+ 0); // No optional argument
+}
+
+//------------------------------------------------------------------------------
+// Exported functions
+//------------------------------------------------------------------------------
+
+//------------------------------------------------------------------------------
+/// Starts the driver and waits for an audio input stream to forward to the SSC.
+//------------------------------------------------------------------------------
+int main(void)
+{
+ TRACE_CONFIGURE(DBGU_STANDARD, 115200, BOARD_MCK);
+ printf("-- USB Device Audio Speaker Project %s --\n\r", SOFTPACK_VERSION);
+ printf("-- %s\n\r", BOARD_NAME);
+ printf("-- Compiled: %s %s --\n\r", __DATE__, __TIME__);
+
+ // Initialize all PIOs
+ PIO_Configure(pins, PIO_LISTSIZE(pins));
+
+ // Initialize PSRAM
+ BOARD_ConfigurePsram();
+
+ // Switch to Main clock
+ AT91C_BASE_PMC->PMC_MCKR = (AT91C_BASE_PMC->PMC_MCKR & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
+
+ // Configure PLL to 98.285MHz
+ *AT91C_CKGR_PLLR = ((1 << 29) | (171 << AT91C_CKGR_MUL_SHIFT) \
+ | (0x0 << AT91C_CKGR_OUT_SHIFT) |(0x3f << AT91C_CKGR_PLLCOUNT_SHIFT) \
+ | (21 << AT91C_CKGR_DIV_SHIFT));
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCK) == 0);
+
+ // Configure master clock in two operations
+ AT91C_BASE_PMC->PMC_MCKR = (( AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLLA_CLK) & ~AT91C_PMC_CSS) | AT91C_PMC_CSS_MAIN_CLK;
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
+ AT91C_BASE_PMC->PMC_MCKR = ( AT91C_PMC_PRES_CLK_2 | AT91C_PMC_CSS_PLLA_CLK);
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) == 0);
+
+ // DBGU reconfiguration
+ DBGU_Configure(DBGU_STANDARD, 115200, SSC_MCK);
+
+ // Configure and enable the TWI (required for accessing the DAC)
+ *AT91C_PMC_PCER = (1<< AT91C_ID_TWI0);
+ TWI_ConfigureMaster(AT91C_BASE_TWI0, TWI_CLOCK, SSC_MCK);
+ TWID_Initialize(&twid, AT91C_BASE_TWI0);
+
+ // Enable the DAC master clock
+ AT91C_BASE_PMC->PMC_PCKR[0] = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK_8;
+ AT91C_BASE_PMC->PMC_SCER = AT91C_PMC_PCK0;
+ while ((AT91C_BASE_PMC->PMC_SR & AT91C_PMC_PCKRDY0) == 0);
+
+ // Initialize the audio DAC
+ WM8731_DAC_Init(&twid, WM8731_SLAVE_ADDRESS);
+
+ // Configure SSC
+ SSC_Configure(AT91C_BASE_SSC0,
+ AT91C_ID_SSC0,
+ SAMPLE_RATE * BITS_BY_SLOT * 2,
+ SSC_MCK);
+ SSC_ConfigureReceiver(AT91C_BASE_SSC0, 0, 0);
+ SSC_ConfigureTransmitter(AT91C_BASE_SSC0,
+ AT91C_I2S_MASTER_TX_SETTING(BITS_BY_SLOT, SLOT_BY_FRAME),
+ AT91C_I2S_TX_FRAME_SETTING( BITS_BY_SLOT, SLOT_BY_FRAME));
+ SSC_DisableTransmitter(AT91C_BASE_SSC0);
+
+#if defined(AUDIO_USING_DMA)
+ // Initialize DMA controller.
+ DMAD_Initialize(BOARD_SSC_DMA_CHANNEL, 0);
+ // Configure and enable the SSC interrupt
+ IRQ_ConfigureIT(AT91C_ID_HDMA, 0, HDMA_IrqHandler);
+ IRQ_EnableIT(AT91C_ID_HDMA);
+#endif
+
+ // USB audio driver initialization
+ AUDDSpeakerDriver_Initialize();
+
+ // connect if needed
+ VBUS_CONFIGURE();
+ while (USBD_GetState() < USBD_STATE_CONFIGURED);
+
+ // Infinite loop
+ while (1) {
+
+ if( USBState == STATE_SUSPEND ) {
+ TRACE_DEBUG("suspend !\n\r");
+ LowPowerMode();
+ USBState = STATE_IDLE;
+ }
+ if( USBState == STATE_RESUME ) {
+ // Return in normal MODE
+ TRACE_DEBUG("resume !\n\r");
+ NormalPowerMode();
+ USBState = STATE_IDLE;
+ }
+ // Read the incoming audio stream
+ AUDDSpeakerDriver_Read(buffers[inBufferIndex],
+ AUDDSpeakerDriver_BYTESPERFRAME,
+ (TransferCallback) FrameReceived,
+ 0); // No optional argument
+ }
+
+ return 0;
+}
+
diff --git a/usb-device-audio-speaker-project/obj/.empty_dir b/usb-device-audio-speaker-project/obj/.empty_dir new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/usb-device-audio-speaker-project/obj/.empty_dir |