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-rw-r--r--resources/gdb/at91sam7se-ek-sdram.gdb78
-rw-r--r--resources/gdb/at91sam9260-ek-sdram.gdb70
-rw-r--r--resources/gdb/at91sam9260-ek-sram.gdb26
-rw-r--r--resources/gdb/at91sam9263-ek-sdram.gdb78
-rw-r--r--resources/gdb/at91sam9263-ek-sram.gdb25
-rw-r--r--resources/gdb/at91sam9g20-ek-sdram.gdb75
-rw-r--r--resources/gdb/at91sam9g20-ek-sram.gdb26
-rw-r--r--resources/gdb/at91sam9rl-ek-sdram.gdb65
-rw-r--r--resources/gdb/at91sam9rl-ek-sram.gdb25
-rw-r--r--resources/gdb/at91sam9xe-ek-sdram.gdb70
-rw-r--r--resources/gdb/at91sam9xe-ek-sram.gdb26
-rw-r--r--resources/gdb/debug.pl93
12 files changed, 657 insertions, 0 deletions
diff --git a/resources/gdb/at91sam7se-ek-sdram.gdb b/resources/gdb/at91sam7se-ek-sdram.gdb
new file mode 100644
index 0000000..3fba949
--- /dev/null
+++ b/resources/gdb/at91sam7se-ek-sdram.gdb
@@ -0,0 +1,78 @@
+# SDRAM initialization script for the AT91SAM7SE
+#-----------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Enable PLL
+set *0xFFFFFC2C = 0x1048100E
+while ((*0xFFFFFC68 & 0x4) == 0)
+end
+
+# Select prescaler value
+set *0xFFFFFC30 = 0x00000004
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000007
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFFF80 = 0x2
+
+# Enable EBI pios
+# PMC
+set *0xFFFFFC10 = 0x1C
+# PIOA
+set *0xFFFFF404 = 0x3F800000
+set *0xFFFFF474 = 0x3F800000
+# PIOB
+set *0xFFFFF604 = 0x0003FFFF
+set *0xFFFFF674 = 0x0003FFFF
+# PIOC
+set *0xFFFFF804 = 0x0000FFFF
+set *0xFFFFF870 = 0x0000FFFF
+
+# SDRAM configuration (see corresponding application note)
+set *0xFFFFFFB8 = 0x21922159
+
+set *0xFFFFFFB0 = 0x11
+set *0x20000000 = 0
+
+set *0xFFFFFFB0 = 0x12
+set *0x20000000 = 0
+
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+set *0xFFFFFFB0 = 0x14
+set *0x20000000 = 0
+
+set *0xFFFFFFB0 = 0x13
+set *0x20000000 = 0
+
+set *0xFFFFFFB0 = 0x10
+set *0x20000000 = 0
+
+set *0xFFFFFFB4 = 0x150
+
+echo SDRAM configuration ok.\n \ No newline at end of file
diff --git a/resources/gdb/at91sam9260-ek-sdram.gdb b/resources/gdb/at91sam9260-ek-sdram.gdb
new file mode 100644
index 0000000..29aa5a0
--- /dev/null
+++ b/resources/gdb/at91sam9260-ek-sdram.gdb
@@ -0,0 +1,70 @@
+# SDRAM initialization script for the AT91SAM9260
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x2060BF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Set PLLB for USB usage
+set *0xFFFFFC2C = 0x207C3F0C
+while ((*0xFFFFFC68 & 0x4) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFEF1C = 0x2
+
+# SDRAM configuration
+set *0xFFFFEA08 = 0x85227259
+
+set *0xFFFFEA00 = 0x1
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x2
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x3
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x0
+set *0x20000000 = 0
+
+set *0xFFFFEA04 = 0x2B7
+
+echo SDRAM configuration ok.\n \ No newline at end of file
diff --git a/resources/gdb/at91sam9260-ek-sram.gdb b/resources/gdb/at91sam9260-ek-sram.gdb
new file mode 100644
index 0000000..05355e0
--- /dev/null
+++ b/resources/gdb/at91sam9260-ek-sram.gdb
@@ -0,0 +1,26 @@
+# MCK initialization script for the AT91SAM9260
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x2060BF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+
diff --git a/resources/gdb/at91sam9263-ek-sdram.gdb b/resources/gdb/at91sam9263-ek-sdram.gdb
new file mode 100644
index 0000000..b0e139f
--- /dev/null
+++ b/resources/gdb/at91sam9263-ek-sdram.gdb
@@ -0,0 +1,78 @@
+# SDRAM initialization script for the AT91SAM9263
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x206DBF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Set PLLB for USB usage
+set *0xFFFFFC2C = 0x20AF3F0F
+while ((*0xFFFFFC68 & 0x4) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Configure PIOD as peripheral (D16/D31)
+# __writeMemory32(0xFFFF0000,0xFFFFF870,"Memory");
+set *0xFFFFF870 = 0xFFFF0000
+# __writeMemory32(0x00000000,0xFFFFF874,"Memory");
+set *0xFFFFF874 = 0x00000000
+# __writeMemory32(0xFFFF0000,0xFFFFF804,"Memory");
+set *0xFFFFF804 = 0xFFFF0000
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFED20 = 0x2
+
+# SDRAM configuration
+set *0xFFFFE208 = 0x85227259
+
+set *0xFFFFE200 = 0x1
+set *0x20000000 = 0
+
+set *0xFFFFE200 = 0x2
+set *0x20000000 = 0
+
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+set *0xFFFFE200 = 0x4
+set *0x20000000 = 0
+
+set *0xFFFFE200 = 0x3
+set *0x20000000 = 0
+
+set *0xFFFFE200 = 0x0
+set *0x20000000 = 0
+
+set *0xFFFFE204 = 0x2B7
+
+echo SDRAM configuration ok.\n
diff --git a/resources/gdb/at91sam9263-ek-sram.gdb b/resources/gdb/at91sam9263-ek-sram.gdb
new file mode 100644
index 0000000..a1627c9
--- /dev/null
+++ b/resources/gdb/at91sam9263-ek-sram.gdb
@@ -0,0 +1,25 @@
+# MCK initialization script for the AT91SAM9263
+#------------------------------------------------
+
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x206DBF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
diff --git a/resources/gdb/at91sam9g20-ek-sdram.gdb b/resources/gdb/at91sam9g20-ek-sdram.gdb
new file mode 100644
index 0000000..a3e685b
--- /dev/null
+++ b/resources/gdb/at91sam9g20-ek-sdram.gdb
@@ -0,0 +1,75 @@
+# SDRAM initialization script for the AT91SAM9G20
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 800MHz
+set *0xFFFFFC28 = 0x202A3F01
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Set PLLB for USB usage
+set *0xFFFFFC2C = 0x10193F05
+while ((*0xFFFFFC68 & 0x4) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00001300
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00001302
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFEF1C = 0x2
+
+# Enable PC16-PC31 pins
+set *0xFFFFF870 = 0xFFFF0000
+set *0xFFFFF874 = 0x00000000
+set *0xFFFFF804 = 0xFFFF0000
+
+# SDRAM configuration
+set *0xFFFFEA08 = 0x96338379
+
+set *0xFFFFEA00 = 0x1
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x2
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x3
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x0
+set *0x20000000 = 0
+
+set *0xFFFFEA04 = 0x39D
+
+echo SDRAM configuration ok.\n
diff --git a/resources/gdb/at91sam9g20-ek-sram.gdb b/resources/gdb/at91sam9g20-ek-sram.gdb
new file mode 100644
index 0000000..4dc6ea1
--- /dev/null
+++ b/resources/gdb/at91sam9g20-ek-sram.gdb
@@ -0,0 +1,26 @@
+# MCK initialization script for the AT91SAM9G20
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 800MHz
+set *0xFFFFFC28 = 0x202A3F01
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00001300
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00001302
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+
diff --git a/resources/gdb/at91sam9rl-ek-sdram.gdb b/resources/gdb/at91sam9rl-ek-sdram.gdb
new file mode 100644
index 0000000..b80fb7f
--- /dev/null
+++ b/resources/gdb/at91sam9rl-ek-sdram.gdb
@@ -0,0 +1,65 @@
+# SDRAM initialization script for the AT91SAM9RL
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLL to 200MHz
+set *0xFFFFFC28 = 0x2031BF03
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFEF20 = 0x2
+
+# SDRAM configuration
+set *0xFFFFEA08 = 0x85227259
+
+set *0xFFFFEA00 = 0x1
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x2
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x3
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x0
+set *0x20000000 = 0
+
+set *0xFFFFEA04 = 0x2BC
+
+echo SDRAM configuration ok.\n \ No newline at end of file
diff --git a/resources/gdb/at91sam9rl-ek-sram.gdb b/resources/gdb/at91sam9rl-ek-sram.gdb
new file mode 100644
index 0000000..bb9d667
--- /dev/null
+++ b/resources/gdb/at91sam9rl-ek-sram.gdb
@@ -0,0 +1,25 @@
+# MCK initialization script for the AT91SAM9RL
+#------------------------------------------------
+
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLL to 200MHz
+set *0xFFFFFC28 = 0x0031BF03
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
diff --git a/resources/gdb/at91sam9xe-ek-sdram.gdb b/resources/gdb/at91sam9xe-ek-sdram.gdb
new file mode 100644
index 0000000..cf2cb3c
--- /dev/null
+++ b/resources/gdb/at91sam9xe-ek-sdram.gdb
@@ -0,0 +1,70 @@
+# SDRAM initialization script for the AT91SAM9XE
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x2060BF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Set PLLB for USB usage
+set *0xFFFFFC2C = 0x207C7F0C
+while ((*0xFFFFFC68 & 0x4) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+echo Configuring the SDRAM controller...\n
+
+# Enable EBI chip select for the SDRAM
+set *0xFFFFEF1C = 0x2
+
+# SDRAM configuration
+set *0xFFFFEA08 = 0x85227259
+
+set *0xFFFFEA00 = 0x1
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x2
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+set *0xFFFFEA00 = 0x4
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x3
+set *0x20000000 = 0
+
+set *0xFFFFEA00 = 0x0
+set *0x20000000 = 0
+
+set *0xFFFFEA04 = 0x2B7
+
+echo SDRAM configuration ok.\n
diff --git a/resources/gdb/at91sam9xe-ek-sram.gdb b/resources/gdb/at91sam9xe-ek-sram.gdb
new file mode 100644
index 0000000..24fadd0
--- /dev/null
+++ b/resources/gdb/at91sam9xe-ek-sram.gdb
@@ -0,0 +1,26 @@
+# MCK initialization script for the AT91SAM9XE
+#------------------------------------------------
+# Configure master clock
+echo Configuring the master clock...\n
+# Enable main oscillator
+set *0xFFFFFC20 = 0x00004001
+while ((*0xFFFFFC68 & 0x1) == 0)
+end
+
+# Set PLLA to 200MHz
+set *0xFFFFFC28 = 0x2060BF09
+while ((*0xFFFFFC68 & 0x2) == 0)
+end
+
+# Select prescaler
+set *0xFFFFFC30 = 0x00000100
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+# Select master clock
+set *0xFFFFFC30 = 0x00000102
+while ((*0xFFFFFC68 & 0x8) == 0)
+end
+
+echo Master clock ok.\n
+
diff --git a/resources/gdb/debug.pl b/resources/gdb/debug.pl
new file mode 100644
index 0000000..5bca69a
--- /dev/null
+++ b/resources/gdb/debug.pl
@@ -0,0 +1,93 @@
+# Perl script to easily launch AT91 debug sessions.
+
+use File::Basename;
+
+# List of supported boards
+my @boards = ("at91sam7se-ek",
+ "at91sam9260-ek",
+ "at91sam9261-ek",
+ "at91sam9263-ek",
+ "at91sam9rl-ek",
+ "at91sam9xe-ek",
+ "at91sam9g20-ek",
+ "at91sam9m10-ek",
+ "at91cap9-dk",
+ "at91cap9-stk"
+ );
+
+# Check that an argument has been provided
+if (!@ARGV[0]) {
+
+ print("Usage: " . basename($0) . " <elf-file>\n");
+ exit(1);
+}
+
+# Parse file name
+my $file = @ARGV[0];
+my $script = "";
+my $gdb = dirname($0);
+
+# Check #2: this must be an elf file
+if ($file !~ m/.*.elf/i) {
+
+ print(".elf file expected.\n");
+ exit(2);
+}
+
+# Check #1: 'sdram' or 'ddram' or 'bcram' token in filename
+if (($file =~ m/.*sdram.*/i) or ($file =~ m/.*ddram.*/i) or ($file =~ m/.*bcram.*/i) or ($file =~ m/.*sam9.*/i) or ($file =~ m/.*cap9.*/i) ) {
+
+ # Find board basename
+ foreach $board (@boards) {
+
+ if (index($file, $board) != -1) {
+
+ $script = "$gdb\\$board";
+ }
+ }
+
+ # Add -ek-mck or -ek-sdram depending on need
+ if ($file =~ m/.*sdram.*/i) {
+
+ $script .= "-sdram.gdb";
+ }
+ elsif ($file =~ m/.*ddram.*/i) {
+
+ $script .= "-ddram.gdb";
+ }
+ elsif ($file =~ m/.*bcram.*/i) {
+
+ $script .= "-bcram.gdb";
+ }
+ else {
+
+ $script .= "-sram.gdb";
+ }
+}
+
+# Create command file to define "reset" command
+open(CMD, ">cmd.gdb") or die("Could not create command file:\n$!");
+print(CMD "define reset\n");
+print(CMD " target remote localhost:2331\n");
+print(CMD " monitor reset\n");
+if ($script) {
+
+ print(CMD " source $script\n");
+}
+print(CMD " load\n");
+print(CMD "end");
+close(CMD);
+
+# Launch GDB
+$pid = fork();
+if ($pid == 0) {
+
+ exec("arm-none-eabi-gdb -x cmd.gdb -ex \"reset\" $file");
+}
+else {
+
+ $SIG{INT} = 'IGNORE';
+ $res = waitpid($pid, 0);
+}
+print("Done\n");
+unlink("cmd.gdb");
personal git repositories of Harald Welte. Your mileage may vary