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authorhenryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2007-11-23 17:32:14 +0000
committerhenryk <henryk@6dc7ffe9-61d6-0310-9af1-9938baff3ed1>2007-11-23 17:32:14 +0000
commitaa804cf4ef8ed3236ae0065952d1faef735b3824 (patch)
treeae0b5069cf266016f7aa4fa307845a0828156df7 /openpicc/os/boot/boot.s
parent062f55ca3ea77ebcace83aab4772c9cd3f28ec34 (diff)
Add a work around to have each pio data change fiq followed by a regular IRQ in order to enable some code to be run synchronized with critical sections
git-svn-id: https://svn.openpcd.org:2342/trunk@348 6dc7ffe9-61d6-0310-9af1-9938baff3ed1
Diffstat (limited to 'openpicc/os/boot/boot.s')
-rw-r--r--openpicc/os/boot/boot.s25
1 files changed, 15 insertions, 10 deletions
diff --git a/openpicc/os/boot/boot.s b/openpicc/os/boot/boot.s
index 8faf7f3..a7e9c32 100644
--- a/openpicc/os/boot/boot.s
+++ b/openpicc/os/boot/boot.s
@@ -3,7 +3,7 @@
.extern main
.extern exit
.extern AT91F_LowLevelInit
- .extern ssc_rcmr_on_start
+ .extern pio_irq_isr_value
.text
.code 32
@@ -59,6 +59,9 @@
.equ PIO_LED1, (1 << 25)
.equ PIO_LED2, (1 << 12)
.equ MC_RCR, 0xFFFFFF00
+.equ AIC_ISCR, (0x12C)
+.equ PIO_SECONDARY_IRQ, 31
+.equ PIO_SECONDARY_IRQ_BIT, (1 << PIO_SECONDARY_IRQ)
/* FIQ latency is approx 1us. At 13.56 MHz carrier frequency this means that
* 13.56 cycles of the carrier have passed when the FIQ kicks in and this is
@@ -265,9 +268,8 @@ fiq_handler:
.func my_fiq_handler
my_fiq_handler:
/* code that uses pre-initialized FIQ reg */
- /* r8 AT91C_BASE_AIC (dfu init)
+ /* r8 tmp
r9 AT91C_TC_SWTRG
- //r9 AT91C_BASE_SSC
r10 AT91C_BASE_PIOA
r11 tmp
r12 AT91C_BASE_TC0
@@ -280,20 +282,23 @@ my_fiq_handler:
str r11, [r10, #PIOA_CODR] /* enable LED */
#endif
ldr r8, [r10, #PIOA_ISR]
+
+ /* Store the retrieved PIO ISR value into pio_irq_isr_value */
+ ldr r11, =pio_irq_isr_value
+ str r8, [r11]
+
tst r8, #PIO_DATA /* check for PIO_DATA change */
ldrne r11, [r10, #PIOA_PDSR]
tstne r11, #PIO_DATA /* check for PIO_DATA == 1 */
strne r9, [r12, #TC_CCR] /* software trigger */
- /*movne r11, #TC0_FRAME_OFFSET
- strne r11, [r12, #0x10] /* Set TC0_CV to TC0_FRAME_OFFSET */
-
- /* Enable SSC Rx clock from RK */
- /*ldrne r11, =ssc_rcmr_on_start
- ldrne r11, [r11]
- strne r11, [r9, #SSC_RCMR]*/
movne r11, #PIO_DATA
strne r11, [r10, #PIOA_IDR] /* disable further PIO_DATA FIQ */
+
+ /* Trigger PIO_SECONDARY_IRQ */
+ mov r11, #PIO_SECONDARY_IRQ_BIT
+ ldr r8, =AT91C_BASE_AIC
+ str r11, [r8, #AIC_ISCR]
#ifdef LED_TRIGGER
mov r11, #PIO_LED1
personal git repositories of Harald Welte. Your mileage may vary