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* Copy over the relevant changes from the sniffonly branch pending integrationhenryk2008-03-051-108/+42
* Commit status quo. Partly or severely broken.henryk2008-02-021-0/+1
* New hardware versionhenryk2007-12-191-1/+1
* Implement unrolled loop, have not yet measured performancehenryk2007-12-151-59/+42
* Add complicated mechanism that should have brought clock cycle accurate measu...henryk2007-12-121-3/+37
* Add new miller decoder (not working yet)henryk2007-12-121-1/+30
* Several modifications to enable spinning until the correct phase is reached i...henryk2007-12-111-10/+33
* Prevent late frames by spinning in SSC CP0 IRQ till end of short frame receptionhenryk2007-12-091-1/+9
* Fix FIQ code for SSC TF emulationhenryk2007-12-031-8/+7
* Fix SSC TX registers (especially the clock source selection), peripheral conf...henryk2007-11-291-0/+24
* Switch to hardcoded fiq handler implementation directly in the vector table (...henryk2007-11-291-79/+14
* Add a work around to have each pio data change fiq followed by a regular IRQ ...henryk2007-11-231-10/+15
* Commit status quo (pending cleanup of the debug and experimental code that I ...henryk2007-11-231-15/+63
* Add tragically failed (and commented out) attempt to remap ram to addr 0henryk2007-11-211-0/+16
* Commit status quo: Start adding iso 14443 layer 3a codehenryk2007-11-211-2/+91
* Initial import of FreeRTOS code for OpenPICChenryk2007-11-061-0/+161
personal git repositories of Harald Welte. Your mileage may vary